70V05L15JGI [IDT]
Dual-Port SRAM, 8KX8, 15ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-68;
| 型号： | 70V05L15JGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 8KX8, 15ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-68 静态存储器 内存集成电路 |
| 文件： | 总22页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT70V05S/L
HIGH-SPEED 3.3V
8K x 8 DUAL-PORT
STATIC RAM
Features
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
◆
◆
◆
◆
◆
–
–
Commercial: 15/20/25/35/55ns (max.)
Industrial:20ns (max.)
◆
Low-power operation
Full on-chip hardware support of semaphore signaling
between ports
–
IDT70V05S
◆
◆
◆
◆
Active:400mW(typ.)
Standby: 3.3mW (typ.)
IDT70V05L
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
–
Active:380mW(typ.)
Standby: 660µW (typ.)
IDT70V05 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
◆
◆
Green parts available, see ordering information
Functional Block Diagram
OEL
OER
CE
L
CE
R/W
R
R/W
L
R
,
I/O0L- I/O7L
I/O0R-I/O7R
I/O
Control
I/O
Control
(1,2)
L
(1,2)
R
BUSY
BUSY
A
12L
A
12R
0R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
0L
A
13
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
L
L
CE
OE
R/W
R
R
R
R/W
L
SEM
L
SEM
R
M/S
(2)
(2)
INTL
INTR
2942 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
OCTOBER 2008
1
DSC 2941/9
©2008IntegratedDeviceTechnology,Inc.
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
reads or writes to any location in memory. An automatic power down
featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
FabricatedusingIDT’sCMOShigh-performancetechnology,these
devices typicallyoperate ononly400mWofpower.
The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The
IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port
SRAMorasacombinationMASTER/SLAVEDual-PortSRAMfor16-bit-
or-morewordsystems. UsingtheIDTMASTER/SLAVEDual-PortSRAM
approach in 16-bit or wider memory system applications results in full-
speed,error-freeoperationwithouttheneedforadditionaldiscretelogic.
This device provides two independent ports with separate control,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
The IDT70V05 is packaged in a ceramic 68-pin PGA and PLCC
and a 64-pin thin quad flatpack (TQFP).
Pin Configurations(1,2,3)
12/03/01
INDEX
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
I/O2L
I/O3L
I/O4L
I/O5L
A
A
A
A
A
A
INT
BUSY
V
M/S
BUSY
INT
A
A
A
A
A
5L
4L
3L
2L
1L
0L
10
11
12
13
14
15
16
17
18
19
59
58
57
56
55
VSS
I/O6L
I/O7L
IDT70V05J
J68-1(4)
54
53
52
51
50
49
48
47
46
45
44
L
VDD
L
68-Pin PLCC
Top View(5)
VSS
SS
I/O0R
I/O1R 20
I/O2R
,
R
R
21
22
23
24
25
26
VDD
0R
I/O3R
I/O4R
I/O5R
I/O6R
1R
2R
3R
4R
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2941 drw 02
12/03/01
INDEX
A
A
A
A
A
4L
3L
2L
1L
0L
1
2
3
4
5
6
48
47
46
I/O2L
I/O3L
I/O4L
I/O5L
45
44
43
42
41
V
SS
INT
L
,
70V05PF
PN-64(4)
I/O6L
I/O7L
BUSY
L
7
8
9
VDD
V
SS
64-Pin TQFP
Top View(5)
VSS
M/S
40
39
38
37
10
11
12
BUSY
R
I/O0R
I/O1R
I/O2R
INT
R
A
A
A
A
A
0R
VDD
13
14
15
16
1R
2R
3R
4R
36
35
34
33
I/O3R
I/O4R
I/O5R
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
2941 drw 03
6.42
2
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
12/03/01
51
50
48
A
46
A
44
BUSY
42
M/S
40
INT
38
36
11
10
09
08
07
06
05
04
03
02
01
A4L
2L
1L
0L
A1R
A3R
L
R
A
5L
53
A
52
49
47
A
45
INT
43
41
BUSYR
39
37
35
34
L
V
SS
A4R
7L
A3L
A0R
A2R
A
5R
6R
A
6L
55
A
54
32
33
A
A7R
9L
A
8L
57
A
56
A
30
31
A9R
A
8R
11L
10L
12L
59
58
A
28
29
A
A
11R
10R
12R
V
DD
IDT70V05G
G68-1(4)
61
60
26
27
A
V
SS
N/C
63
SEM
N/C
62
68-Pin PGA
Top View(5)
24
N/C
25
N/C
L
CE
L
65
OE
64
22
SEM
23
R
CER
L
R/W
66
L
67
I/O0L
20
OE
21
R
R/W
R
N/C
1
3
5
7
I/O7L
9
68
I/O1L
11
13
V
15
18
I/O7R
19
N/C
VSS
V
SS
DD
I/O4L
I/O2L
I/O1R
I/O4R
2
4
6
8
10
12
14
16
17
I/O5L
I/O0R I/O2R I/O3R I/O5R I/O6R
V
DD
I/O6L
I/O3L
A
B
C
D
E
F
G
H
J
K
L
INDEX
NOTES:
2941 drw 04
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking.
PinNames
Left Port
Right Port
Names
Chip Enable
CE
R/W
OE
L
CE
R/W
OE
R
L
R
Read/Write Enable
Output Enable
Address
L
R
A
0L
- A12
L
A
0R
- A12
R
I/O
SEM
INT
BUSY
0
L
- I/O
7L
I/O
SEM
INT
BUSY
M/S
0
R
- I/O
7R
Data Input/Output
Semaphore Enable
Interrupt Flag
L
R
L
R
Busy Flag
L
R
Master or Slave Select
Power (3.3v)
V
V
DD
SS
Ground (0v)
2941 tbl 00
6.42
3
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
R/W
Outputs
I/O0-7
Mode
CE
H
L
OE
X
SEM
H
X
L
High-Z
DATAIN
DATAOUT
High-Z
Deselected: Power-Down
Write to Memory
X
H
L
H
X
L
H
Read Memory
X
H
X
Outputs Disabled
2941 tbl 02
NOTE:
1. A0L — A12L≠ A0R — A12R
Truth Table II: Semaphore Read/Write Control(1)
Inputs(1)
R/W
Outputs
I/O0-7
Mode
CE
H
OE
L
SEM
H
↑
X
L
L
L
DATAOUT
Read Data in Semaphore Flag
Writ I/O into Semaphore Flag
Not Allowed
H
X
DATAIN
e
0
____
L
X
2941 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from I/O0 -I/O7. These eight semaphores are addressed by A0-A2.
6.42
4
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AbsoluteMaximumRatings(1)
MaximumOperatingTemperature
andSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
Commercial
Industrial
Ambient Temperature
GND
VDD
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
0OC to +70OC
0V
3.3V
3.3V
+
0.3V
-40OC to +85OC
0V
+
0.3V
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
T
BIAS
2941 tbl 05
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
Storage
Temperature
TSTG
DC Output
Current
mA
IOUT
2941 tbl 04
NOTES:
RecommendedDCOperating
Conditions
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 0.3V.
Symbol
Parameter
Supply Voltage
Ground
Min.
Typ.
Max.
Unit
V
V
V
DD
SS
3.0
3.3
3.6
0
0
0
V
DD+0.3(2)
0.8
V
____
V
IH
IL
Input High Voltage
Input Low Voltage
2.0
V
-0.5(1)
V
____
V
Capacitance(TA = +25°C, f = 1.0MHz)
2941 tbl 06
NOTES:
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
1. VIL> -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD +0.3V.
C
IN
V
9
pF
COUT
V
10
pF
2941 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitznce when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V05S
70V05L
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
DD = 3.6V, VIN = 0V to VDD
OUT = 0V to VDD
Min.
Max.
10
Min.
Max.
Unit
µA
µA
V
___
___
|
V
V
5
5
___
___
___
___
|
10
V
OL
OH
I
OL = +4mA
0.4
0.4
___
___
V
Output High Voltage
I
OH = -4mA
2.4
2.4
V
2941 tbl 08
NOTE:
1. At VDD < 2.0V input leakages are undefined.
6.42
5
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V ± 0.3V)
70V05X15
70V05X20
70V05X25
Com'l Only
Com'l Only
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
IDD
Dynamic Operating
Current
(Both Ports Active)
S
L
150
140
215
185
140
130
200
175
130
125
190
165
mA
CE = VIL, Outputs Disabled
SEM = VIH
(3)
f = fMAX
____
____
____
____
____
____
____
____
IND
S
L
140
130
225
195
mA
mA
mA
mA
mA
mA
mA
mA
mA
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
25
20
35
30
20
15
30
25
16
13
30
25
CE
SEM
f = fMAX
R
= CE
L
= VIH
= VIH
R
= SEM
L
(3)
____
____
____
____
____
____
____
____
S
L
20
15
45
40
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
85
80
120
110
80
75
110
100
75
72
110
95
CEL
or CE
R
= VIH
Active Port Outputs Disabled,
(3)
f=fMAX
____
____
____
____
____
____
____
____
S
L
80
75
130
115
ISB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
CE > VDD - 0.2V,
IN > VDD - 0.2V or
IN < 0.2V, f = 0(4)
= SEM > VDD - 0.2V
L
and
COM'L
IND
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
R
V
V
SEM
____
____
____
____
____
____
____
____
S
L
1.0
0.2
15
5
R
L
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
One Port CEL or
R
COM'L
IND
S
L
85
80
125
105
80
75
115
100
75
70
105
90
CE > VDD - 0.2V
SEM = SEM > VDD - 0.2V
R
L
____
____
____
____
S
L
80
75
130
115
V
IN > VDD - 0.2V or VIN < 0.2V
____
____
____
____
Active Port Outputs Disabled,
(3)
f = fMAX
2941 tbl 09a
70V05X35
Com'l Only
70V05X55
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Unit
I
DD
Dynamic Operating
Current
COM'L
S
120
115
180
155
120
115
180
155
mA
CE = VIL, Outputs Disabled
SEM = VIH
L
(3)
(Both Ports Active)
f = fMAX
IND
S
L
120
115
200
170
120
115
200
170
mA
mA
mA
mA
mA
mA
mA
mA
mA
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
13
11
25
20
13
11
25
20
CE
SEM
f = fMAX
R
= CE
L
= VIH
R
= SEM
L
= VIH
(3)
S
L
13
11
40
35
13
11
40
35
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
70
65
100
90
70
65
100
90
CEL
or CE
R
= VIH
Active Port Outputs Disabled,
(3)
f=fMAX
S
L
70
65
120
105
70
65
120
105
ISB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
CE > VDD - 0.2V,
IN > VDD - 0.2V or
IN < 0.2V, f = 0(4)
= SEM > VDD - 0.2V
L
and
COM'L
IND
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
R
V
V
SEM
S
L
1.0
0.2
15
5
1.0
0.2
15
5
R
L
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
One Port CEL or
COM'L
IND
S
L
65
60
100
85
65
60
100
85
CE > VDD - 0.2V
R
SEM = SEM > VDD - 0.2V
R
L
S
L
65
60
115
100
65
60
115
100
V
IN > VDD - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
(3)
f = fMAX
2941 tbl 09b
NOTES:
1. “X” in part number indicates power rating (S or L)
2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 115mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
6.42
6
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
3.3V
3.3V
AC Test Conditions
Input Pulse Levels
GND to 3.0V
590Ω
590Ω
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
3ns Max.
1.5V
DATAOUT
BUSY
INT
DATAOUT
5pF*
435Ω
1.5V
30pF
435Ω
Figures 1 and 2
2941 drw 05
2941 tbl 10
Figure 2. Output Test Load
*Including scope and jig.
(For tLZ, tHZ, tWZ, tOW)
Figure 1. AC Output Test Load
Timing of Power-Up Power-Down
CE
tPU
tPD
I
CC
50%
50%
I
SB
2941 drw 06
6.42
7
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
70V05X15
70V05X20
70V05X25
Com'l Only
Com'l
& Ind
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
15
20
25
ns
ns
ns
____
____
____
t
Address Access Time
15
15
20
20
25
25
____
____
____
____
____
____
Chip Enable Access Time(3)
t
Output Enable Access Time(3)
t
10
12
13
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Output Hold from Address Change
3
3
3
____
____
____
Output Low-Z Time(1,2)
t
3
3
3
____
____
____
Output High-Z Time(1,2)
t
10
12
15
____
____
____
Chip Enable to Power Up Time(1,2)
t
0
0
0
____
____
____
Chip Disable to Power Down Time(1,2)
t
15
20
25
____
____
____
t
Semaphore Flag Update Pulse (OE or SEM)
10
10
10
____
____
____
Semaphore Address Access(3)
t
15
20
25
ns
2941 tbl 11a
70V05X35
Com'l Only
70V05X55
Com'l Only
Symbol
READ CYCLE
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
35
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
Address Access Time
35
35
55
55
Chip Enable Access Time(3)
Output Enable Access Time(3)
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
t
t
20
30
____
____
t
3
3
____
____
t
3
3
Output High-Z Time(1,2)
15
25
____
____
t
t
Chip Enable to Power Up Time(1,2)
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access(3)
0
0
____
____
____
____
t
35
50
____
____
t
15
15
____
____
t
35
55
ns
2941 tbl 11b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization but is not production tested.
3. To access SRAM, CE = VIL, SEM = VIH.
4. 'X' in part number indicates power rating (S or L).
6.42
8
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.42
9
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
70V05X20
Com'l
& Ind
70V05X15
Com'l Only
70V05X25
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
15
12
12
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
12
0
15
0
20
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
10
15
15
____
____
____
t
10
12
15
____
____
____
t
0
0
0
(1,2)
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
12
15
____
____
____
t
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
t
t
ns
2941 tbl 12a
70V05X35
Com'l Only
70V05X55
Com'l Only
Symbol
WRITE CYCLE
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
35
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
25
0
40
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
15
30
____
____
t
15
25
____
____
t
0
0
(1,2)
____
____
t
Write Enable to Output in High-Z
15
25
t
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
0
5
5
0
5
5
____
____
____
____
____
____
t
t
ns
2941 tbl 12b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization but is not production tested.
3. To access SRAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. “X” in part number indicates power rating (S or L).
6.42
10
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,3,5,8)
tWC
ADDRESS
(7)
tHZ
OE
tAW
(9)
or
CE
SEM
(3)
WR
(2)
(6)
t
tAS
tWP
R/W
(7)
tWZ
tOW
(4)
(4)
DATAOUT
DATAIN
tDW
tDH
2941 drw 08
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,3,5,8)
tWC
ADDRESS
tAW
CE or SEM(9)
R/W
(6)
AS
(2)
(3)
tWR
t
tEW
tDW
tDH
DATAIN
2941 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE, or R/W.
7. Timing depends on which enable signal is de-asserted first, CE, or R/W.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIN. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.42
11
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
tOH
A0-A2
VALID ADDRESS
VALID ADDRESS
tAW
tWR
tACE
tEW
SEM
tDW
tSOP
OUT
DATA
DATA
0
DATAIN VALID
VALID(2)
tAS
tWP
tDH
R/W
tSWRD
tAOE
OE
tSOP
Write Cycle
Read Cycle
2941 drw 10
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
2941 drw 11
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.42
12
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6)
70V05X15
Com'l Ony
70V05X20
Com'l
& Ind
70V05X25
Com'l Only
Symbol
BUSY TIMING (M/S = VIH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
)
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
t
t
t
15
17
17
____
____
____
t
5
5
5
____
____
____
BUSY Disable to Valid Data(3)
t
18
30
30
t
Write Hold After BUSY(5)
12
15
17
____
____
____
BUSY TIMING (M/S = VIL
)
____
____
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
0
0
ns
ns
tWH
12
15
17
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
30
25
45
35
50
35
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
2941 tbl 13a
70V05X35
Com'l Only
70V05X55
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH
)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
20
20
20
45
40
40
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
t
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
t
t
20
35
____
____
t
5
5
____
____
BUSY Disable to Valid Data(3)
t
35
40
t
Write Hold After BUSY(5)
25
25
____
____
BUSY TIMING (M/S = VIL
)
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
0
ns
ns
tWH
25
25
PORT-TO-PORT DELAY TIMING
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
60
45
80
65
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
2941 tbl 13b
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to “Timing Waveform of Read With BUSY (M/S = VIH)” or “Timing Waveform of Write With Port-
To-Port Delay (M/S = VIL)”.
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' is part number indicates power rating (S or L).
6.42
13
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
TimingWaveformof WritewithPort-to-PortReadwithBUSY(2,4,5)(M/S=VIH)
tWC
MATCH
ADDR"A"
R/W"A"
tWP
tDW
tDH
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBDA
tBDD
tBAA
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
2941 drw 12
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE) then BUSY is input. For this example, BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the port opposite from Port “A”.
6.42
14
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
tWH
(2)
R/W"B"
2941 drw 13
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on port “B” Blocking R/W“B”, until BUSY“B” goes HIGH.
3. tWB is only for the slave version.
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
tAPS
CE"B"
tBAC
tBDC
BUSY"B"
2941 drw 14
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDR"B"
BUSY"B"
ADDRESS "N"
(2)
tAPS
MATCHING ADDRESS "N"
t
BAA
tBDA
2941 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
6.42
15
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
70V05X15
70V05X20
70V05X25
Com'l Only
Com'l Only
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
ns
ns
ns
t
0
0
0
____
____
____
t
15
15
20
20
20
20
____
____
____
t
Interrupt Reset Time
ns
2941 tbl 14a
70V05X35
Com'l Only
70V05X55
Com'l Only
Symbol
INTERRUPT TIMING
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
0
____
____
t
25
25
40
40
____
____
t
Interrupt Reset Time
ns
2941 tbl 14b
NOTES:
1. 'X' in part number indicates power rating (S or L).
6.42
16
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
INTERRUPT SET ADDRESS(2)
ADDR"A"
CE"A"
(3)
(4)
tWR
tAS
R/W"A"
INT"B"
(3)
INS
t
2941 drw 16
tRC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
CE"B"
(3)
tAS
OE"B"
(3)
INR
t
INT"B"
2941 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.42
17
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table III — Interrupt Flag(1)
Left Port
Right Port
R/W
L
L
A
12L-A0L
1FFF
X
R/W
X
R
A
12R-A0R
Function
Set Right INT Flag
H(3) Reset Right INT
Flag
CE
L
L
OE
X
L
INT
X
L
CE
R
OE
R
INT
R
X
X
X
L(2)
R
X
X
X
X
X
L
L
1FFF
1FFE
X
R
X
X
X
X
L(3)
L
L
X
X
X
Set Left INT
L
Flag
Flag
X
L
L
1FFE
H(2)
X
X
X
Reset Left INT
L
2941tbl 15
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
A
12L-A0L
(1)
(1)
A
12R-A0R
Function
Normal
Normal
Normal
CE
L
CE
X
R
BUSY
L
BUSYR
X
NO MATCH
MATCH
H
H
H
H
X
H
X
H
MATCH
H
H
L
L
MATCH
(2)
(2)
Write Inhibit(3)
2941 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V05 are push
pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. VIL if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be low simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving low regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D7
Left
D0
- D7
Right
Status
No Action
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
0
0
1
1
0
1
1
1
0
1
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2941 tbl 17
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V05.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
6.42
18
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
CE
CE
MASTER
SLAVE
Dual Port
SRAM
Dual Port
SRAM
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
MASTER
Dual Port
SRAM
CE
SLAVE
CE
Dual Port
SRAM
BUSY (R)
BUSY (L)
BUSY (L)
BUSY (R)
BUSY (R)
BUSY (L)
2941 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V05 SRAMs.
Functional Description
The IDT70V05 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V05 has an automatic power down
featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry
that permits the respective port to go into a standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
The BUSY outputs on the IDT 70V05 SRAM in master mode, are
push-pull type outputs and do not require pull up resistors to
operate. If these SRAMs are being expanded in depth, then the
BUSY indication for the resulting array requires the use of an external
AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
Interrupts
When expanding an IDT70V05 SRAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT70V05 SRAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)is assignedtoeachport. Theleftportinterrupt
flag (INTL) is set when the right port writes to memory location 1FFE
(HEX). The left port clears the interrupt by reading address location
1FFE. Likewise, the right port interrupt flag (INTR) is set when the left
port writes to memory location 1FFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 1FFF. The
message (8 bits) at 1FFE or 1FFF is user-defined. If the interrupt
function is not used, address locations 1FFE and 1FFF are not used
as mail boxes, but as part of the random access memory. Refer to
Truth Table III for the interrupt operation.
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicatingBUSYononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “busy”. The BUSY pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
Semaphores
The use of BUSY logic is not required or desirable for all applica-
tions. Insome cases itmaybe usefultologicallyORthe BUSYoutputs
The IDT70V05 is a fast Dual-Port 8K x 8 CMOS Static RAM with
togetheranduseanyBUSYindicationasaninterruptsourcetoflagthe anadditional8addresslocationsdedicatedtobinarysemaphoreflags.
event of an illegal or illogical operation. If the write inhibit function of These flags allow either processor on the left or right side of the Dual-
BUSYlogicis notdesirable,the BUSYlogiccanbedisabledbyplacing Port SRAM to claim a privilege over the other processor for functions
the part in slave mode with the M/S pin. Once in slave mode the BUSY defined by the system designer’s software. As an example, the
pinoperates solelyas awriteinhibitinputpin.Normaloperationcanbe semaphore can be used by one processor to inhibit the other from
programmed by tying the BUSY pins HIGH. If desired, unintended accessing a portion of the Dual-Port SRAM or any other shared
write operations can be prevented to a port by tying the BUSY pin for resource.
thatportLOW.
TheDual-PortSRAMfeaturesafastaccesstime,andbothportsare
6.42
19
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
completelyindependentofeachother.Thismeansthattheactivityonthe beaccessedbyeithersidethroughaddresspinsA0–A2.Whenaccessing
leftportinnowayslows theaccess timeoftherightport.Bothports are thesemaphores,noneoftheotheraddresspinshasanyeffect.
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel
oraccessed,atthesametimewiththeonlypossibleconflictarisingfrom iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
thesimultaneouswritingof,orasimultaneousREAD/WRITEof,anon- on that side and a one on the other side (see Truth Table V). That
semaphorelocation. Semaphoresareprotectedagainstsuchambiguous semaphorecannowonlybemodifiedbythesideshowingthezero.When
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
in the non-semaphore portion of the Dual-Port SRAM. These devices settoaoneforbothsides(unlessasemaphorerequestfromtheotherside
haveanautomaticpower-downfeaturecontrolledbyCE,theDual-Port ispending)andthencanbewrittentobybothsides. Thefactthattheside
SRAMenable,andSEM,thesemaphoreenable.TheCEandSEMpins whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites
controlon-chippowerdowncircuitrythatpermitstherespectiveporttogo fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
intostandbymodewhennotselected. Thisistheconditionwhichisshown communications.(Athoroughdiscussionontheuseofthisfeaturefollows
in Truth Table II where CE and SEM are both HIGH.
shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe
SystemswhichcanbestusetheIDT70V05containmultipleprocessors storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis
or controllers and are typically very high-speed systems which are freedbythefirstside.
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
a performance increase offered by the IDT70V05's hardware sema- thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
phores,whichprovidealockoutmechanismwithoutrequiringcomplex azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
programming.
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
Softwarehandshakingbetweenprocessors offers themaximumin signalsgoactive.Thisservestodisallowthesemaphorefromchanging
system flexibility by permitting shared resources to be allocated in stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
varying configurations. The IDT70V05 does not use its semaphore Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
flags to control any resources through hardware, thus allowing the cause either signal (SEM or OE) to go inactive or the output will never
system designer total flexibility in system architecture.
change.
A sequence WRITE/READ must be used by the semaphore in
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred order to guarantee that no system level contention will occur. A
in either processor. This can prove to be a major advantage in very processor requests access to shared resources by attempting to write
high-speed systems.
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Truth Table V). As an example, assume a
processorwritesazerototheleftportatafreesemaphorelocation.On
asubsequentread,theprocessorwillverifythatithas writtensuccess-
fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
factthataonewillbereadfromthatsemaphoreontherightsideduring
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
secondside’s flagwillnowstayLOWuntilits semaphore requestlatch
is written to a one. From this it is easy to understand that, if a
semaphoreisrequestedandtheprocessorwhichrequesteditnolonger
needstheresource,theentiresystemcanhangupuntilaoneiswritten
intothatsemaphorerequestlatch.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dentofthe Dual-PortSRAM. These latches canbe usedtopass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignmentmethodcalled“TokenPassingAllocation.”Inthis method,
thestateofasemaphorelatchisusedasatokenindicatingthatshared
resource is in use. If the left processor wants to use this resource, it
requests the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
Thesemaphoreflagsareactivelow.Atokenisrequestedbywriting
a zero into a semaphore latch and is released when the same side
writes a one to that latch.
The eight semaphore flags reside within the IDT70V05 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOWinput on the SEM pin (which acts
as a chip select for the semaphore flags) and using the other control
pins (Address, OE, and R/W) as they would be used in accessing a
standardStaticRAM.Eachoftheflagshasauniqueaddresswhichcan
6.42
20
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
The criticalcase ofsemaphore timingis whenbothsides requesta theleftside.
single token by attempting to write a zero into it at the same time. The
Once the left side was finished with its task, it would write a one to
semaphore logic is specially designed to resolve this problem. If Semaphore 0 and may then try to gain access to Semaphore 1. If
simultaneous requests are made, the logic guarantees that only one Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo
side receives the token. If one side is earlier than the other in making itssemaphorerequestandperformothertasksuntilitwasabletowrite,then
the request, the first side to make the request will receive the token. If readazerointoSemaphore1.Iftherightprocessorperformsasimilartask
bothrequests arriveatthesametime,theassignmentwillbearbitrarily withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap
made to one port or the other.
4Kblocks ofDual-PortSRAMwitheachother.
One caution that should be noted when using semaphores is that
The blocks do not have to be any particular size and can even be
semaphores alone do not guarantee that access to a resource is variable, depending upon the complexity of the software using the
secure. As with any powerful programming technique, if semaphores semaphore flags. All eight semaphores could be used to divide the
are misused or misinterpreted, a software error can easily happen.
Dual-PortSRAMorothersharedresourcesintoeightparts.Semaphores
Initialization of the semaphores is not automatic and must be canevenbeassigneddifferentmeaningsondifferentsidesratherthan
handled via the initialization program at power-up. Since any sema- being given a common meaning as was shown in the example above.
phore request flag which contains a zero must be reset to a one, all
Semaphores are a useful form of arbitration in systems like disk
semaphores on both sides should have a one written into them at interfaces where the CPU must be locked out of a section of memory
initialization from both sides to assure that they will be free when during a transfer and the I/O device cannot tolerate any wait states.
needed.
With the use of semaphores, once the two devices has determined
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assignedSRAMsegmentsatfullspeed.
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
goinandupdatethedatastructure.Whentheupdateiscompleted,the
data structure blockis released. This allows the interpretingprocessor
to come back and read the complete data structure, thereby guaran-
teeing a consistent data structure.
UsingSemaphores—SomeExamples
Perhaps the simplest application of semaphores is their applica-
tionasresourcemarkersfortheIDT70V05’sDual-PortSRAM.Saythe
8Kx8SRAMwas tobe dividedintotwo4Kx8blocks whichwere tobe
dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
thelowersectionofmemory,andSemaphore1couldbedefinedasthe
indicator for the upper section of memory.
To take a resource, in this example the lower 4K of Dual-Port
SRAM, the processor on the left port could write and then read a
zero in to Semaphore 0. If this task were successfully completed
(a zero was read back rather than a one), the left processor would
assume control of the lower 4K. Meanwhile the right processor was
attempting to gain control of the resource after the left processor, it
would read back a one in response to the zero it had attempted to
write into Semaphore 0. At this point, the software could choose to try
andgaincontrolofthesecond4Ksectionbywriting,thenreadingazero
into Semaphore 1. If it succeeded in gaining control, it would lock out
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
D0
D
D
D0
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
2941 drw 19
Figure 4. IDT70V05 Semaphore Logic
6.42
21
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
XXXXX
A
999
A
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
PF
G
J
64-pin TQFP (PN64-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
15
20
25
35
55
Commercial Only
Commercial & Industrial
Speed in nanoseconds
Commercial Only
Commercial Only
Commercial Only
S
L
Standard Power
Low Power
64K (8K x 8) 3.3V Dual-Port RAM
70V05
2941 drw 20
NOTE:
1. Contact your local sales office for Industrial temp range in other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
DatasheetDocumentHistory
3/11/99:
Initiateddatasheetdocumenthistory
Converted to new format
Cosmetic and typographical corrections
Page 2 and 3 Added additional notes to pin configurations
Changeddrawingformat
6/9/99:
11/10/99:
3/10/00:
Replaced IDT logo
Added 15 & 20ns speed grades
UpgradedDCparameters
AddedIndustrialTemperatureinformation
Changed±200mVto0mVinnotes
Page 5 Increasedstoragetemperatureparameter
ClarifiedTAparameter
5/26/00:
Page 6 DCElectricalparameters2–changedwordingfromopentodisabled
Page 2 & 3 Added date revision to pin configurations
12/04/01:
Page 2, 3, 5 & 6 Changed naming conventions from VCC to VDD and from GND to VSS
Page 6, 8, 10, 13 & 16 Removed industrial temp for 25ns, 35ns and 55ns from DC & AC Electrical Characteristics
Page 22 Removedindustrialtempfrom25ns,35nsand55nsfromorderinginformation
Page 1 & 22 Replaced TM logo with ® logo
07/27/06:
10/23/08:
Page 1 Addedgreenavailabilitytofeatures
Page 22 Addedgreenindicatortoorderinginformation
Page 22 Removed "IDT" from orderable part number
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for SALES:
for Tech Support:
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fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
22
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