709369L12PFGI [IDT]
HIGH-SPEED 32/16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM;
| 型号： | 709369L12PFGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 32/16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM |
| 文件： | 总16页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 32/16K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT709379/69L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features
True Dual-Ported memory cells which allow simultaneous
◆
◆
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
TTL- compatible, single 5V ( 10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
access of the same memory location
High-speed clock to data access
– Commercial:7.5/9/12ns(max.)
– Insustrial:9ns(max.)
Low-power operation
– IDT709379/69L
◆
◆
◆
Active: 1.2W (typ.)
Standby: 2.5mW (typ.)
Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
◆
◆
◆
◆
◆
◆
◆
Available in a 100-pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering information
Functional Block Diagram
R/
W
L
R/W
UB
R
R
UB
L
CE0L
CE1L
CE0R
CE1R
1
0
1
0
0/1
0/1
LB
OE
L
L
LB
OE
R
R
1b 0b
0a 1a
1a 0a
a
0b 1b
FT/PIPE
L
0/1
0/1
b
a
b
FT/PIPER
I/O9L-I/O17L
I/O0L-I/O8L
I/O9R-I/O17R
I/O0R-I/O8R
I/O
Control
I/O
Control
A
14L(1)
0L
A
14R(1)
0R
Counter/
Address
Reg.
Counter/
Address
Reg.
A
MEMORY
ARRAY
A
CLK
ADS
R
CLK
ADS
CNTEN
L
L
R
CNTEN
R
L
L
CNTRST
CNTRST
R
4845 drw 01
NOTE:
1. A14X is a NC for IDT709369.
FEBRUARY 2018
1
DSC-4845/8
©2018 Integrated Device Technology, Inc.
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
Withaninputdataregister,theIDT709379/69hasbeenoptimizedfor
The IDT709379/69 is a high-speed 32/16K x 18 bit synchronous
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by CE0 and CE1, permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using CMOS high-performance technology, these
devicestypicallyoperateononly1.2Wofpower.
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allowsimultaneousaccessofanyaddressfrombothports.Registerson
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
Pin Configurations(1,2,3)
INDEX
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A
9L
1
A
8R
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
A
A
A
A
10L
11L
12L
A
A
9R
10R
3
A
A
A
A
11R
12R
13R
14R
4
13L
(1)
5
A
14L
6
(1)
7
NC
LB
8
NC
LB
L
UB
L
9
R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CE0L
UB
R
709379/69PF
PN100(5)
CE1L
CNTRST
CE0R
L
CE1R
R/W
OE
L
CNTRST
R/W
GND
OE
R
R
100-Pin TQFP
Top View(6)
L
V
CC
FT/PIPE
L
R
.
I/O17L
I/O16L
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
FT/PIPE
I/O17R
GND
I/O16R
I/O15R
I/O14R
R
I/O13R
I/O12R
I/O11R
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4845 drw 02
NOTES:
1. A14x is a NC for IDT709369.
2. All VCC pins must be connected to power supply.
3. All GND pins must be connected to ground.
4. Package body is approximately 14mm x 14mm x 1.4mm
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
2
6.42
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
Chip Enables(3)
CE0L, CE1L
CE0R, CE1R
R/WL
R/WR
Read/Write Enable
Output Enable
Address
OEL
OER
(1)
(1)
A0L - A14L
A0R - A14R
I/O0L - I/O17L
CLKL
I/O0R - I/O17R
CLKR
Data Input/Output
Clock
Upper Byte Select(2)
Lower Byte Selectt(2)
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power
UBL
UBR
LBL
LBR
ADSL
ADSR
CNTENL
CNTRSTL
FT/PIPEL
CNTENR
CNTRSTR
FT/PIPER
NOTES:
1. A14x is a NC for IDT709369.
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CEo and CE1 are single buffered when FT/PIPE = VIL,
CEo and CE1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
V
CC
GND
Ground
4845 tbl 01
Truth Table I—Read/Write and Enable Control(1,2,3)
Upper Byte
I/O9-17
Lower Byte
I/O0-8
CLK
↑
CE
X
1
R/W
X
Mode
Deselected—Power Down
OE
X
X
X
X
X
X
L
CE
0
UB
X
X
H
L
LB
X
X
H
H
L
H
X
L
L
L
L
L
L
L
L
High-Z
High-Z
High-Z
High-Z
L
X
Deselected—Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
↑
H
H
H
H
H
H
H
H
X
High-Z
High-Z
↑
L
DATAIN
High-Z
High-Z
↑
H
L
L
DATAIN
DATAIN
High-Z
↑
L
L
DATAIN
DATAOUT
High-Z
↑
L
H
L
H
H
H
X
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
↑
L
H
L
DATAOUT
DATAOUT
High-Z
↑
L
L
DATAOUT
High-Z
↑
H
X
L
L
Outputs Disabled
4845 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
6.342
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control(1,2,6)
Previous
Internal
Address
Internal
Address
Used
External
Address
MODE
CLK
↑
I/O(3)
ADS CNTEN CNTRST
An
X
X
An
An
L(4)
H
X
H
H
DI/O (n)
External Address Used
An + 1
An + 1
L(5)
H
DI/O(n+1) Counter Enabled—Internal Address generation
↑
↑
X
An + 1
X
H
H
DI/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
X
A
0
X
X
L(4)
DI/O(0)
Counter Reset to Address 0
↑
4845 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
Symbol
Parameter
Min.
Typ.
Max. Unit
Grade
Ambient
GND
VCC
Temperature(2)
V
CC
Supply Voltage
Ground
4.5
5.0
5.5
0
V
V
V
Commercial
0OC to +70OC
0V
0V
5.0V
5.0V
+
+
10%
GND
0
0
Industrial
-40OC to +85OC
10%
V
IH
IL
Input High Voltage
Input Low Voltage
2.2
6.0(1)
0.8
____
4845 tbl 04
-0.5(2)
V
____
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
V
4845 tbl 05
NOTES:
1. VTERM must not exceed VCC + 10%.
2. VIL > -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings(1)
Capacitance(1)
(TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
CIN
V
9
pF
(3)
OUT
C
V
10
pF
4845 tbl 07
T
BIAS
STG
JN
OUT
Temperature Under Bias
Storage Temperature
Junction Temperature
DC Output Current
-55 to +125
-65 to +150
+150
oC
oC
oC
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
T
T
3. COUT also references CI/O.
I
50
mA
4845 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
4
6.42
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
709379/69L
Symbol
|ILI|
Parameter
Input Leakage Current(1)
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
Min.
Max.
Unit
µA
µA
V
___
___
___
5
5
|ILO|
Output Leakage Current
Output Low Voltage
Output High Voltage
CE0 = VIH or CE1 = VIL, VOUT = 0V to VCC
VOL
IOL = +4mA
IOH = -4mA
0.4
___
VOH
2.4
V
4845 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VCC = 5V ± 10%)
709379/69L7
Com'l Only
709379/69L9
Com'l
& Ind
709379/69L12
Com'l Only
Typ.(4)
Typ.(4)
Typ.(4)
Symbol
Parameter
Test Condition
CEL and CER= VIL
Outputs Disabled
Version
COM'L
Max.
440
Max.
400
430
135
160
275
295
Max. Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
mA
mA
mA
L
L
L
L
L
250
250
300
80
230
355
(1)
____
____
____
____
IND
f = fMAX
ISB1
ISB2
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
65
145
70
110
CEL = CER = VIH
f = fMAX
(1)
____
____
____
____
95
Standby Current
(One Port - TTL
Level Inputs)
COM'L
160
295
175
175
150
240
CE"A" = VIL and
(3)
CE"B" = VIH
Active Port Outputs
Disabled, f=fMAX
____
____
____
____
IND
L
(1)
mA
mA
ISB3
ISB4
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CER and
CEL > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L
IND
L
L
0.2
5.0
0.5
0.5
3.0
6.0
0.5
3.0
____
____
____
____
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
IND
L
L
150
290
170
190
270
290
140
225
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
VIN > VCC - 0.2V or
VIN < 0.2V, Active Port
Outputs Disabled, f = fMAX
____
____
____
____
(1)
4845 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VCC = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6.542
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1,2 and 3
4845 tbl 10
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
30pF
347Ω
5pF*
347Ω
4845 drw 04
4845 drw 05
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
8
7
6
5
10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
tCD
tCD
(Typical, ns)
1
,
4
3
2
1
2
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
-1
4845 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6
6.42
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3) (VCC = 5V ± 10%)
709379/69L7
Com'l Only
709379/69L9
Com'l
& Ind
709379/69L12
Com'l Only
Symbol
Parameter
Min.
22
Max.
Min.
25
15
12
12
6
Max.
Min.
30
20
12
12
8
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYC1
Clock Cycle Time (Flow-Through)(2)
Clock Cycle Time (Pipelined)(2)
Clock High Time (Flow-Through)(2)
Clock Low Time (Flow-Through)(2)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(2)
Clock Rise Time
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
CYC2
CH1
CL1
CH2
CL2
R
12
7.5
7.5
5
5
6
8
____
____
____
3
3
3
____
____
____
F
Clock Fall Time
3
3
3
____
____
____
SA
Address Setup Time
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
HA
Address Hold Time
SC
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
HC
SB
HB
SW
HW
SD
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
HD
SAD
ADS Setup Time
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
HAD
SCN
HCN
ADS Hold Time
CNTEN Setup Time
CNTEN Hold Time
SRST
HRST
OE
CNTRST Setup Time
CNTRST Hold Time
0
1
1
____
____
____
Output Enable to Data Valid
Output Enable to Output Low-Z(1)
Output Enable to Output High-Z(1)
7.5
9
12
____
____
____
OLZ
2
2
2
OHZ
CD1
CD2
DC
1
7
1
7
1
7
Clock to Data Valid (Flow-Through)(2)
Clock to Data Valid (Pipelined)(2)
Data Output Hold After Clock High
Clock High to Output High-Z(1)
Clock High to Output Low-Z(1)
18
20
25
____
____
____
____
____
____
7.5
9
12
____
____
____
2
2
2
2
2
2
2
2
2
CKHZ
CKLZ
9
9
9
____
____
____
Port-to-Port Delay
____
____
____
____
____
____
t
CWDD
CCS
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
28
10
35
15
40
15
ns
t
ns
4845 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) to either the Left or Right ports when FT/PIPE = VIH. Flow-Through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for
that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER and FT/PIPEL.
6.742
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for
Flow-Through Output (FT/PIPE"X" = VIL)(3,7)
t
CYC1
t
CH1
tCL1
CLK
CE0
tSC
tHC
tSC
tHC
(4)
CE1
tSB
tHB
UB, LB
R/W
tHB
tSB
tHW
tSW
tSA
t
HA
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
An + 3
(1)
t
DC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2
(1)
(1)
t
CKLZ
tDC
(1)
t
OHZ
t
OLZ
OE (2)
tOE
4845 drw 07
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE"X" = VIH)(3,7)
t
CYC2
tCH2
tCL2
CLK
CE
0
t
SC
tHC
t
SC
t
HC
HB
(4)
CE1
t
SB
tHB
t
SB
t
(6)
UB, LB
R/W
t
HW
HA
t
SW
t
SA
t
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
Qn + 1
Qn + 2 (6)
(1)
tCKLZ
(1)
(1)
t
OHZ
tOLZ
OE(2)
tOE
4845 drw 08
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
7. "X" here denotes Left or Right port. The diagram is with respect to that port.
8
6.42
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
t
CYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A6
A5
A4
A3
A
2
A
0
A1
tSC
tHC
t
SC
tHC
(3)
CKHZ
tCD2
tCD2
t
tCD2
Q
0
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
(3)
(3)
tDC
tCKLZ
t
DC
t
CKHZ
t
SA
tHA
A6
A5
A4
A3
A2
A
0
A1
t
SC
tHC
CE0(B2)
tSC
t
HC
(3)
t
CD2
tCKHZ
t
CD2
(3)
DATAOUT(B2)
Q4
Q2
(3)
t
CKLZ
tCKLZ
4845 drw 09
Timing Waveform of Write with Port-to-Port Flow-Through Read(4,5,7)
CLK "A"
tSW
tHW
R/W "A"
ADDRESS "A"
DATAIN "A"
CLK "B"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(6)
tCCS
tCD1
R/W "B"
tHW
t
SW
t
HA
tSA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
(6)
t
CD1
tCWDD
VALID
VALID
tDC
t
DC
4845 drw 10
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709379/69 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0, UB, LB, and ADS = VIL; CE1 and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
6.942
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 3
An + 4
An
An +1
An + 2
An + 2
ADDRESS
tSA
tHA
tSD
t
HD
DATAIN
Dn + 2
(1)
(1)
tCKLZ
tCD2
tCD2
(2)
tCKHZ
Qn + 3
Qn
DATAOUT
READ
NOP(5)
WRITE
READ
4845 drw 11
Timing Waveforn of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
t
CYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
(1)
CKLZ
tCD2
tCD2
t
(2)
Qn
Qn + 4
DATAOUT
(1)
t
OHZ
OE
READ
WRITE
READ
4845 drw 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1 and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
10
6.42
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
t
CYC1
tCH1
tCL1
CLK
CE0
t
SC
tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 4
An
An + 3
An +1
An + 2
An + 2
ADDRESS
t
SA
tHA
t
SD tHD
DATAIN
Dn + 2
t
CD1
t
CD1
tCD1
tCD1
(2)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
(1)
(1)
t
DC
tDC
tCKLZ
t
CKHZ
NOP(5)
READ
WRITE
4845 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 5
An
tHA
An +1
An + 2
An + 3
Dn + 3
An + 4
ADDRESS
tSA
t
SD tHD
DATAIN
Dn + 2
tOE
tDC
tCD1
tCD1
tCD1
(2)
Qn + 4
Qn
DATAOUT
(1)
CKLZ
(1)
t
tOHZ
tDC
OE
READ
WRITE
READ
4845 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1 and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
61.412
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
ADDRESS
An
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 3
Qn + 1
Qn
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
4845 drw 15
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tCD1
Qn + 3(2)
Qx(2)
Qn
Qn + 4
Qn + 1
Qn + 2
DATAOUT
tDC
READ
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
WITH
COUNTER
4845 drw 16
NOTES:
1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output
remains constant for subsequent clocks.
12
6.42
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
ADDRESS
An
INTERNAL(3)
ADDRESS
An(7)
An + 4
An + 2
An + 1
An + 3
tSAD tHAD
ADS
CNTEN
t
SD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
4845 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
t
CYC2
tCH2
tCL2
CLK
tSA tHA
ADDRESS(4)
An + 2
An
An + 1
INTERNAL(3)
ADDRESS
Ax(6)
0
An + 1
1
An
t
SW tHW
R/W
ADS
CNTEN
tSRST
tHRST
CNTRST
t
SD
tHD
D0
DATAIN
(5)
Qn
Q1
Q0
DATAOUT
.
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
READ
READ
ADDRESS 1
ADDRESS n ADDRESS n+1
4845 drw 18
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
CE0, UB, LB = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’ Address is written
to during this cycle.
61.432
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Depth and Width Expansion
A Functional Description
The IDT709379/69 features dual chip enables (refer to Truth Table
I)inordertofacilitaterapidandsimpledepthexpansionwithnorequire-
ments for external logic. Figure 4 illustrates how to control the various
chip enables in order to expand two devices in depth.
The IDT709379/69 can also be used in applications requiring ex-
pandedwidth,asindicatedinFigure4.Sincethebanksareallocatedat
thediscretionoftheuser,theexternalcontrollercanbesetuptodrivethe
input signals for the various devices as required to allow for 36-bit
or wider applications.
The IDT709379/69 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory appli-
cations.
CE0 = VIH or CE1 = VIL for one clock cycle will power down the
internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT709379/69's for depth
expansion configurations. When the Pipelined output mode is en-
abled, two cycles are required with CE0 = VIL and CE1 = VIH to re-
activate the outputs.
(1)
A15/A14
IDT709379/69
IDT709379/69
CE
0
1
CE
0
CE
CE1
VCC
VCC
Control Inputs
Control Inputs
IDT709379/69
IDT709379/69
CE1
CE1
CE0
CE0
CNTRST
CLK
Control Inputs
Control Inputs
ADS
CNTEN
4845 drw 19
R/W
LB, UB
OE
Figure 4. Depth and Width Expansion with IDT709379/69
NOTE:
1. A14 is for IDT709369.
14
6.42
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
XXXXX
A
99
A
A
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Tube or Tray
Tape & Reel
Blank
8
Blank
I(1)
Commercial (0 C to +70 C)
Industrial (-40 C to +85 C)
G(2)
PF
Green
)
100-pin TQFP (PN100
Commercial Only
Commercial & Industrial
Commercial Only
7
9
12
Speed in nanoseconds
L
Low Power
576K (32K x 18-Bit) Synchronous Dual-Port RAM
288K (16K x 18-Bit) Synchronous Dual-Port RAM
4845 drw 20
709379
709369
NOTES:
1. Industrial temperature range is available. For other speeds, packages and powers contact your sales office
2. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyoursalesoffice.
LEADFINISH(SnPb)partsareinEOLprocess.ProductDiscontinuationNotice-PDN#SP-17-02
61.452
IDT709379/69L
High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Datasheet Document History
9/30/99:
11/10/99:
12/22/99:
1/12/01:
InitialPublicRelease
Replaced IDT log
Addednmissingdiamond
Changed information in Truth Table II
Increasedstoragetemperatureparameter
ClarifiedTA parameter
Page 1
Page 4
Page 5
DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed 200mVto0mVinnotes
RemovedPreliminarystatus
04/26/04:
Consolidatedmultipledevicesintoonedatasheet
RemovedI-tempfootnote
Page 2
Page 4
Addeddaterevisiontopinconfiguration
AddedJunctionTemperaturetoAbsoluteMaximumRatingsTable
AddedAmbientTemperaturefootnote
Page 5
Page 7
Page 15
AddedI-tempnumbersfor9nsspeedtotheDCElectricalCharacteristicsTable
Added 6ns speed DC timing numbers to the DC Electrical Characteristics Table
AddedI-tempfor9nsspeedtoACElectricalCharacteristicsTable
Added 6ns speed AC timing numbers to the AC Electrical Characteristics Table
Added 6ns speed grade and 9ns I-temp to ordering information
Added IDT Clock Solution Table
Page 1 & 16
Page 15
Page 1
Replaced old TM logo with new TM logo
Removed "IDT" from orderable part number
Addedgreenpartsavailabilitytofeatures
01/29/09:
07/26/10:
Page 15
Page 7
Addedgreenindicatortoorderinginformation
InordertocorrecttheheadernotesoftheACElectCharsTableandalignthemwiththeIndustrialtemprange
values located in the table, the commercial TA header note has been removed
Pages 8-11
Inordertocorrectthefootnotesoftimingdiagrams,CNTEN hasbeenremovedtoreconcilethefootnoteswith
the CNTEN logicdefinitionfoundinTruthTableII-AddressCounterControl
07/16/15:
Page 1
Updatedspeedofferingsbyremovingthe6.5nscommercialgradeinFeatures
Page 2
RemovedIDTinreferencetofabrication
Page 2 & 15
Page 5
Page 6
Page 7
Page 16
The package code PN100-1 changed to PN100 to match standard package codes
Removed X6 speed grade from the DC Elec Chars table
CorrectedtypointheTypicalOutputDeratingdrawing
Removed X6 speed grade from the AC Elec Chars table
Added Tape and Reel indicator to, removed X6 speed grade and updated the commercial offerings in
OrderingInformation
Page 15
RemovedtheIDTClockSolutiontable
02/08/18:
ProductDiscontinuationNotice-PDN#SP-17-02
Last time buy expires June 15, 2018
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
16
6.42
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