709359L6PFG [IDT]
HIGH-SPEED 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM;
| 型号： | 709359L6PFG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM 静态存储器 内存集成电路 |
| 文件： | 总15页 (文件大小：685K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 8/4K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT709359/49L
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial:6.5/7.5/9ns(max.)
– Industrial: 7.5ns (max.)
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
◆
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
◆
Low-power operation
– IDT709359/49L
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for 83 MHz
◆
Active:925mW(typ.)
Standby: 2.5mW (typ.)
◆
◆
◆
Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
◆
◆
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
◆
◆
Available in a 100-pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering informaiton
Functional Block Diagram
R/
WL
R/
W
R
R
UB
L
UB
CE0L
CE1L
CE0R
CE1R
1
0
1
0
0/1
0/1
LB
L
LB
OE
R
R
OEL
1b 0b
0a 1a
1a 0a
a
0b 1b
b
FT/PIPE
L
0/1
0/1
b
a
FT/PIPE
R
I/O9L-I/O17L
I/O0L-I/O8L
I/O9R-I/O17R
I/O0R-I/O8R
(1)
I/O
Control
I/O
Control
(1)
12L
A
A12R
Counter/
Address
Reg.
Counter/
Address
Reg.
MEMORY
ARRAY
A
C0LRK
R
R
A
0L
CLK
L
L
ADS
CNTEN
ADS
CNTEN
R
L
CNTRST
L
CNTRST
R
5633 drw 01
NOTE:
1. A12 is a NC for IDT709349.
MAY 2015
1
DSC-5633/4
©2015 Integrated Device Technology, Inc.
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
Withaninputdataregister,theIDT709359/49hasbeenoptimizedfor
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by CE0 and CE1, permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using CMOS high-performance technology, these
devicestypicallyoperateononly925mWofpower.
TheIDT709359/49isahigh-speed8/4Kx18bitsynchronousDual-
Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
PinConfigurations(1,2,3,4)
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
A
A
A
A
A
NC
NC
NC
LB
UB
CE0R
CE1R
8R
A
9L
75
74
2
9R
A10L
3
10R
A
12L
11L
(1)
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
4
11R
12R
A
(1)
5
NC
NC
NC
LB
UB
6
7
8
L
9
R
L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
R
CE0L
CE1L
CNTRST
R/W
OE
709359/49PF
(5)
PN100
L
100-Pin TQFP
CNTRST
R
L
(6)
Top View
L
R/W
GND
OE
FT/PIPE
I/O17R
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
R
VCC
FT/PIPE
L
R
R
I/O17L
I/O16L
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5633 drw 02
NOTES:
1. A12 is a NC for IDT709349.
2. All VCC pins must be connected to power supply.
3. All GND pins must be connected to ground.
4. Package body is approximately 14mm x 14mm x 1.4mm
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
2
6.42
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
CE0R, CE1R
R/W
OE
Names
Chip Enables(3)
CE0L, CE1L
R/W
OE
L
R
Read/Write Enable
Output Enable
Address
L
R
(1)
(1)
A
0L - A12L
A
0R - A12R
I/O0R - I/O17R
CLK
UB
LB
ADS
CNTEN
CNTRST
FT/PIPE
I/O0L - I/O17L
CLK
UB
LB
ADS
CNTEN
CNTRST
FT/PIPE
Data Input/Output
Clock
L
R
Upper Byte Select(2)
Lower Byte Select(2)
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power (5V)
L
R
L
R
NOTES:
L
R
1. A12 is a NC for IDT709349.
L
R
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CEo and CE1 are single buffered when FT/PIPE = VIL,
CEo and CE1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
L
R
L
R
V
CC
GND
Ground (0V)
5633 tbl 01
Truth Table I—Read/Write and Enable Control(1,2,3)
Upper Byte
I/O9-17
Lower Byte
I/O0-8
(5)
CLK
↑
CE
1
R/W
X
Mode
Deselected—Power Down
OE
X
X
X
X
X
X
L
CE (5)
0
UB(4)
LB(4)
H
X
L
L
L
L
L
L
L
L
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
L
X
X
X
Deselected—Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
↑
H
H
H
H
H
H
H
H
H
L
H
H
L
X
High-Z
↑
L
DATAIN
High-Z
High-Z
DATAIN
DATAIN
High-Z
DATAOUT
DATAOUT
High-Z
↑
H
L
L
↑
L
L
DATAIN
DATAOUT
High-Z
↑
L
H
L
H
H
H
X
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
↑
L
H
L
↑
L
L
DATAOUT
High-Z
↑
H
X
X
X
Outputs Disabled
5633 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signa
4. LB and UB are single buffered regardless of state of FT/PIPE.
5. CEo and CE1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.
6.342
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control(1,2)
Previous Internal
External
Address
Internal Address
MODE
Address
Used
An
CLK
↑
I/O(3)
I/O (n) External Address Used
I/O(n+1) Counter Enabled—Internal Address generation
I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
DI/O(0) Counter Reset to Address 0
ADS CNTEN CNTRST
An
X
X
An
L(4)
H
X
L(5)
H
H
D
An + 1
An + 1
D
↑
X
An + 1
X
H
H
H
D
↑
X
A
0
X
X
L(4)
↑
5633 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
Recommended Operating
Recommended DC Operating
Temperature and Supply Voltage(1) Conditions
Symbol
Parameter
Supply Voltage
Min.
4.5
Typ.
Max. Unit
Grade
Ambient
GND
Vcc
Temperature(1)
V
CC
5.0
5.5
V
V
V
Commercial
0OC to +70OC
-40OC to +85OC
0V
0V
5.0V
5.0V
+
+
10%
GND
Ground
0
0
0
Industrial
10%
____
V
IH
Input High Voltage
Input Low Voltage
2.2
-0.5(2)
6.0(1)
0.8
5633 tbl 04
____
NOTES:
V
IL
V
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
5633 tbl 05
NOTES:
1. VTERM must not exceed Vcc + 10%.
2. This is the parameter TA. This is the "instant on" case temperature.
2. VIL > -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings(1)
Capacitance(1)
(TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
CIN
V
9
pF
(3)
C
OUT
V
10
pF
Te m p e rature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
5633 tbl 07
T
BIAS
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
TSTG
Storage
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
Te m p e rature
3. COUT also references CI/O.
IOUT
DC Output
Current
mA
5633 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
4
6.42
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
709359/49L
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Test Conditions
CC = 5.5V, VIN = 0V to VCC
CE = VIH or CE = VIL, VOUT = 0V to VCC
OL = +4mA
OH = -4mA
Min.
Max.
Unit
µA
µA
V
___
___
___
|
V
5
5
|
Output Leakage Current
Output Low Voltage
Output High Voltage
0
1
V
OL
I
0.4
___
V
OH
I
2.4
V
5633 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VCC = 5V ± 10%)
709359/49L6
Com'l Only
709359/49L7
709359/49L9
Com'l Only
Com'l & Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
210 400
Typ.(4)
Max. Unit
mA
ICC
Dynamic Operating
Current
L
L
L
L
L
L
230
430
185
360
CEL and CER= VIL
Outputs (D1) isabled
f = fMAX
____
____
____
____
(Both Ports Active)
IND
210
40
440
105
120
220
mA
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
45
____
115
____
35
____
95
CE
L = CER = VIH
(1)
f = fMAX
____
40
mA
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
150
235
135
120
205
CE"A" = VIL and
(3)
CE"B" = VIH
Active Port Outp(u1)ts
Disabled, f=fMAX
____
_____
____
____
135
0.5
0.5
130
235
3.0
3.0
190
mA
ISB3
Full Standby Current
(Both Ports -
Both Ports CE
R
and
> VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(2)
COM'L
IND
L
L
0.5
3.0
0.5
3.0
CE
L
CMOS Level Inputs)
V
V
____
_____
____
____
mA
ISB4
Full Standby Current
(One Port -
COM'L
IND
L
L
160
210
110
170
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
CMOS Level Inputs)
V
V
IN > VCC - 0.2V or
____
_____
____
____
130
205
IN < 0.2V, Active Port
(1)
Outputs Disabled, f = fMAX
5633 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6.542
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
2ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1, 2 and 3
5633 tbl 10
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
30pF
347Ω
5pF*
347Ω
5633 drw 04
5633 drw 05
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
8
7
6
5
10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
tCD
tCD
(Typical, ns)
1
2
,
4
3
2
1
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
-1
5633 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6
6.42
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3) (VCC = 5V ± 10%)
709359/49L6
Com'l Only
709359/49L7
Com'l & Ind
709359/49L9
Com'l Only
Symbol
Parameter
Min.
Max.
____
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CYC1
CYC2
CH1
CL 1
CH2
CL 2
Clock Cycle Time (Flow-Through)(2)
Clock Cycle Time (Pipelined)(2)
Clock High Time (Flow-Through)(2)
Clock Low Time (Flow-Through)(2)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(2)
Clock Rise Time
19
10
6.5
6.5
4
22
12
7.5
7.5
5
25
15
12
12
6
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
t
t
t
t
4
____
5
____
6
____
tR
3
3
3
____
____
____
tF
Clock Fall Time
3
____
3
____
3
____
t
SA
HA
SC
HC
SB
HB
SW
HW
SD
HD
SAD
HA D
SCN
HCN
SRST
HRST
OE
OLZ
OHZ
CD1
CD2
DC
CKHZ
CKLZ
Address Setup Time
3.5
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
Address Hold Time
t
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
3.5
0
t
t
3.5
0
t
t
3.5
0
t
R/W Hold Time
t
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
3.5
0
t
t
3.5
0
t
ADS Hold Time
t
3.5
0
CNTEN Setup Time
t
CNTEN Hold Time
t
3.5
CNTRST Setup Time
t
0
____
0
____
1
____
CNTRST Hold Time
t
Output Enable to Data Valid
6.5
____
7.5
____
9
____
(1)
t
Output Enable to Output Low-Z
2
2
2
t
Output Enable to Output High-Z(1)
Clock to Data Valid (Flow-Through)(2)
Clock to Data Valid (Pipelined)(2)
Data Output Hold After Clock High
1
____
7
1
____
7
1
____
7
t
15
18
20
____
____
____
t
6.5
____
7.5
____
9
____
t
2
2
2
2
2
2
2
2
2
(1)
t
Clock High to Output High-Z
9
____
9
____
9
____
(1)
t
Clock High to Output Low-Z
Port-to-Port Delay
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
____
____
____
____
____
____
t
CWDD
24
9
28
10
35
15
ns
tCCS
ns
5633 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) to either the Left or Right ports when FT/PIPE = VIH. Flow-Through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for
that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER and FT/PIPEL.
6.742
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for
Flow-Through Output (FT/PIPE"X" = VIL)(3,7)
t
CYC1
tCH1
tCL1
CLK
CE
0
tSC
tHC
tSC
tHC
CE1
tSB
tHB
UB, LB
R/W
tHB
tSB
tHW
tSW
tSA
tHA
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
An + 3
(1)
tDC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2
(1)
(1)
tCKLZ
tDC
(1)
t
OHZ
t
OLZ
OE (2)
tOE
5633 drw 07
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE"X" = VIH)(3,7)
tCYC2
tCH2
tCL2
CLK
CE
0
tSC
tHC
tSC
tHC
(4)
CE1
t
SB
tHB
tSB
tHB
(6)
UB, LB
R/W
tHW
tSW
tSA
tHA
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
Qn + 1
Qn + 2 (6)
(1)
tCKLZ
(1)
(1)
t
OHZ
tOLZ
OE(2)
tOE
5633 drw 08
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
7. "X" here denotes Left or Right port. The diagram is with respect to that port.
8
6.42
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
t
CYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A6
A5
A4
A3
A
2
A
0
A1
tSC
tHC
t
SC
tHC
(3)
CKHZ
tCD2
tCD2
t
tCD2
Q
0
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
(3)
(3)
tDC
tCKLZ
t
DC
tCKHZ
tSA
tHA
A6
A5
A4
A3
A2
A
0
A1
t
SC
tHC
CE0(B2)
tSC
tHC
(3)
tCD2
tCKHZ
tCD2
DATAOUT(B2)
Q4
Q2
(3)
(3)
tCKLZ
tCKLZ
5633 drw 09
Timing Waveform of Write with Port-to-Port Flow-Through Read(4,5,7)
CLK "A"
tSW
tHW
R/W "A"
ADDRESS "A"
DATAIN "A"
CLK "B"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(6)
tCCS
tCD1
R/W "B"
tHW
t
SW
tHA
tSA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
(6)
t
CD1
tCWDD
VALID
VALID
tDC
tDC
5633 drw 10
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709359/49 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
6.942
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 3
An + 4
An
An +1
An + 2
An + 2
ADDRESS
tSA
tHA
tSD
t
HD
DATAIN
Dn + 2
(1)
(1)
tCKLZ
tCD2
tCD2
(2)
tCKHZ
Qn + 3
Qn
DATAOUT
READ
NOP(5)
WRITE
READ
5633 drw 11
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
(1)
CKLZ
tCD2
tCD2
t
(2)
Qn
Qn + 4
DATAOUT
(1)
t
OHZ
OE
READ
WRITE
READ
5633 drw 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
10
6.42
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
t
CYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 4
An
An + 3
An +1
An + 2
Qn + 1
An + 2
ADDRESS
tSA
tHA
t
SD
tHD
DATAIN
Dn + 2
tCD1
tCD1
tCD1
tCD1
(2)
Qn + 3
Qn
READ
DATAOUT
(1)
(1)
tDC
tDC
READ
tCKLZ
t
CKHZ
NOP(5)
WRITE
5633 drw 13
TimingWaveformof Flow-ThroughRead-to-Write-to-Read(OE Controlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 5
An
tHA
An +1
An + 2
An + 3
Dn + 3
An + 4
ADDRESS
tSA
t
SD tHD
DATAIN
Dn + 2
tOE
tDC
tCD1
tCD1
tCD1
(2)
Qn + 4
Qn
DATAOUT
(1)
CKLZ
(1)
t
tOHZ
tDC
OE
READ
WRITE
READ
5633 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
61.412
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
t
SAD tHAD
CNTEN
tSCN tHCN
tCD2
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 3
Qn + 1
Qn
DATAOUT
tDC
READ
READ
WITH
COUNTER
HOLD
READ WITH COUNTER
EXTERNAL
ADDRESS
COUNTER
5633 drw 15
TimingWaveformof Flow-ThroughReadwithAddressCounterAdvance(1)
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tCD1
Qn + 3(2)
Qn + 4
Qx(2)
Qn
Qn + 1
Qn + 2
DATAOUT
tDC
READ
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
WITH
COUNTER
5633 drw 16
NOTES:
1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output
remains constant for subsequent clocks.
12
6.42
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 2
An + 4
An + 1
An + 3
tSAD tHAD
ADS
CNTEN
t
SD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
5633 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
t
CYC2
tCH2
tCL2
CLK
t
SA tHA
ADDRESS(4)
An + 2
An
An + 1
INTERNAL(3)
ADDRESS
Ax(6)
0
An + 1
1
An
t
SW tHW
R/W
ADS
CNTEN
t
SRST
tHRST
CNTRST
t
SD
tHD
D0
DATAIN
(5)
Qn
Q1
Q0
DATAOUT
.
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS n
READ
ADDRESS n+1
READ
ADDRESS 1
5633 drw 18
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
CE0, UB, LB = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’ Address is written
to during this cycle.
61.432
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Depth and Width Expansion
AFunctionalDescription
The IDT709359/49 features dual chip enables (refer to Truth Table
I)inordertofacilitaterapidandsimpledepthexpansionwithnorequire-
mentsforexternallogic.Figure4illustrateshowtocontrolthevariouschip
enables in order to expand two devices in depth.
The IDT709359/49 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.
The IDT709359/49 can also be used in applications requiring ex-
pandedwidth,asindicatedinFigure4.Sincethebanksareallocatedat
thediscretionoftheuser,theexternalcontrollercanbesetuptodrivethe
input signals for the various devices as required to allow for 36-bit
or wider applications.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory appli-
cations.
CE0 = VIH or CE1 = VIL for one clock cycle will power down the
internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT709359/49's for depth
expansionconfigurations.WhenthePipelinedoutputmodeisenabled,two
cyclesarerequiredwithCE0=VIL andCE1=VIHtore-activatetheoutputs.
(1)
A13/A12
IDT709359/49
IDT709359/49
CE0
CE0
CE1
CE1
VCC
VCC
Control Inputs
Control Inputs
IDT709359/49
IDT709359/49
CE1
CE1
CE0
CE0
CNTRST
CLK
Control Inputs
Control Inputs
ADS
CNTEN
R/W
5633 drw 19
LB, UB
OE
Figure 4. Depth and Width Expansion with IDT709359/49
NOTE:
1. A13 is for IDT709359, A12 is for IDT709349.
14
6.42
IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
A
XXXXX
A
99
A
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Tube or Tray
Tape & Reel
Blank
8
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I(1)
G(2)
PF
Green
100-pin TQFP (PN100)
Commercial Only
Commercial & Industrial
Commercial Only
6
7
9
Speed in nanoseconds
Low Power
L
144K (8K x 18-Bit) Synchronous Dual-Port RAM
72K (4K x 18-Bit) Synchronous Dual-Port RAM
709359
709349
5633 drw 20
NOTE:
1. Contactyourlocalsalesofficeforindustrialtemprangeforotherspeeds,packagesandpowers.
2. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyour salesoffice.
DatasheetDocumentHistory
07/08/02:
08/18/03:
InitialPublicRelease
RemovedPreliminarystatus
Page 16 Added IDT Clock Solution Table
Page16 Removed "IDT" from orderable part number
Page 1 Added green availability to Features
10/21/08:
05/21/15:
Page 1 Removed 100-pin fine pitch Ball Grid Array fpBGA offering from Features
Page 2 Removed IDT in reference to fabrication
Page 3 The package code PN100-1 changed to PN100 to match standard package codes
Page 3 Removed the date for the PN100-pin TQFP configuration
Page4 Removedthe100-pinfinepitchBallGridArrayfpBGAconfigurationandcorrespondingfootnotes
Page5Correctedtypoinfootnotetext
Page7CorrectedtypointheTypicalOutputDeratingdrawing
Page 8 Removed the commercial temp range from the AC Elec Chars Read & Write Cycle Timing table title
Page15AddedTape&ReelandGreenindicatorswiththeirfootnoteannotationstotheOrderingInformation
Page 15 Removed the 100-pin TQFP fpBGA from the Ordering Information
Page 15 Removed IDT Clock table
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61.452
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