709169S12BF [IDT]
CABGA-100, Tray;型号: | 709169S12BF |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | CABGA-100, Tray 静态存储器 内存集成电路 |
文件: | 总16页 (文件大小:179K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HIGH-SPEED 16/8K x 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT709169/59L
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial:6.5/7.5/9ns(max.)
Industrial:7.5ns (max.)
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
◆
◆
Low-power operation
– IDT709169/59L
– 10ns cycle time,100MHzoperationinPipelinedoutputmode
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for 83MHz
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin fine pitch Ball Grid Array (fpBGA) packages.
◆
◆
Active:925mW(typ.)
Standby: 2.5mW (typ.)
◆
Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
◆
◆
◆
Functional Block Diagram
R/WR
R/W
L
OEL
OER
CE0R
CE1R
CE
CE10LL
1
0
0/1
1
0
0/1
0
0
1
1
0/1
0/1
FT/PIPE
L
FT/PIPE
R
I/O0R - I/O8R
I/O0L - I/O8L
I/O
Control
I/O
Control
(1)
(1)
13R
A13L
A
Counter/
Address
Reg.
Counter/
Address
Reg.
MEMORY
ARRAY
A
C0LRK
R
R
A
0L
CLK
L
L
ADS
CNTEN
CNTRST
ADS
CNTEN
CNTRST
R
L
R
L
5653 drw 01
NOTE:
1. A13 is a NC for IDT709159.
AUGUST 2003
1
DSC-5653/2
©2003IntegratedDeviceTechnology,Inc.
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
Withaninputdataregister,theIDT709169/59hasbeenoptimizedfor
applications having unidirectional or bidirectional data flow in bursts.
Anautomaticpowerdownfeature, controlledbyCE0andCE1, permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using IDT’s CMOS high-performance technology,
thesedevices typicallyoperateononly925mWofpower.
TheIDT709169/59isahigh-speed16/8Kx9bitsynchronousDual-
Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
PinConfigurations(1,2,3,4)
06/28/02
Index
100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
NC
NC
NC
NC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
A
A
A
7R
A7L
A8L
A9L
4
8R
9R
5
6
A10R
A11R
A12R
A13R
A
A
A
10L
7
11L
8
12L
(1)
(1)
9
A
13L
709169/59PF
PN100-1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
(5)
NC
NC
NC
GND
NC
NC
NC
NC
NC
NC
NC
100-Pin TQFP
V
CC
NC
NC
NC
(6)
Top View
NC
CE0L
CE1L
CE0R
CE1R
CNTRST
R
CNTRST
R/W
OE
FT/PIPE
L
R/W
R
L
OE
R
L
FT/PIPE
GND
NC
R
L
NC
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
.
5653 drw 02
NOTES:
1. A13 is a NC for IDT709159.
2. All VCC pins must be connected to power supply.
3. All GND pins must be connected to ground supply.
4. Package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
2
6.42
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations (con't.)(1,2,3,4)
709169/59BF
BF100(5)
100-Pin fpBGA
TopView(6)
06/28/02
A1
A2
A3
A6
A7
A8
A9
A4
A5
A10
A
6R
A9R
A
12R
GND
NC R/WR GND
NC GND
NC
B1
B2
B3
C3
B6
B7
B9
B4
B5
B8
B10
A
4R
A
5R
A
8R
NC
NC
NC
A
10R
NC
OE
R
I/O6R
C1
C5
C6
C2
C4
C7
C9
C10
C8
A
3R
NC CE0R
NC
NC
A7R
CE1R
I/O7R I/O3R
PL/FTR
D1
D2
D6
13R 1)
D9
D3
D5
D7
D8
D10
D4
E4
F4
(
A
0R CLK
R
R
I/O5R
I/O1R
A
A
1R
A
11R
CNTRST
R
I/O8R
A
2R
E5
E6
E7
E8
E9
E10
E1
E2
E3
ADS
L
GND I/O4R I/O2R I/O0R
VCC
GND ADS
CNTEN
R
A
1L
F7
F1
F2
F3
F5
F6
F9
F10
F8
V
CC
V
CC GND
G5
G6
I/O1L I/O0L
GND CLK
L
A0L
I/O2L
A
3L
G1
CNTEN
G2
G4
G8
G9
G3
G7
G10
L
NC
NC
A12L
R/W
L
I/O4L GND
I/O3L
A
5L
9L
NC
,
H7
H8
H9
H10
H3
H4
H5
J5
H6
H1
H2
A
13L(1)
NC I/O7L I/O6L I/O5L
A
NC CE1L
A
2L
A4L
J1
J2
J3
J4
J6
J7
J8
J9
J10
NC
A7L
A10L
NC
NC
NC
OEL
GND GND
I/O8L
K6
K8
CNTRST
K10
K2
K4
K5
K7
K9
K1
K3
V
CC
L
NC
L
V
CC
CE0L
PL/FT
A
8L
NC
A
6L
A
11L
5653 drw 03
NOTES:
1. A13 is a NC for IDT709159.
2. All VCC pins must be connected to power supply.
3. All GND pins must be connected to ground supply.
4. Package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.342
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
Chip Enables
CE0L, CE1L
R/W
OE
CE0R, CE1R
R/W
OE
L
R
Read/Write Enable
Output Enable
Address
L
R
(1)
(1)
A
0L - A13L
A0R - A13R
I/O0L - I/O8L
CLK
I/O0R - I/O8R
CLK
Data Input/Output
Clock
L
R
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power (5V)
ADS
CNTEN
CNTRST
FT/PIPE
L
ADS
CNTEN
CNTRST
FT/PIPE
R
L
R
L
R
L
R
V
CC
GND
Ground (0V)
5653 tbl 01
NOTE:
1. A13 is a NC for IDT709159.
Truth Table I—Read/Write and Enable Control(1,2,3)
CLK
↑
CE
1
R/W
X
I/O0-8
High-Z
High-Z
DATAIN
DATAOUT
High-Z
Mode
Deselected—Power Down
OE
X
X
X
L
CE0
H
X
L
L
L
X
L
X
Deselected—Power Down
↑
H
H
H
L
Write
↑
H
Read
↑
H
X
X
Outputs Disabled
5653 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
4
6.42
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control(1,2)
Previous
Internal
Address
Internal
Address
Used
External
Address
MODE
(3)
CLK
↑
I/O
I/O (n) External Address Used
I/O(n+1) Counter Enabled—Internal Address generation
I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
DI/O(0) Counter Reset to Address 0
ADS
CNTEN
CNTRST
(4)
An
X
X
An
An
L
X
H
H
H
D
(5)
An + 1
An + 1
H
H
X
L
D
↑
X
An + 1
X
H
X
D
↑
(4)
X
A0
L
↑
5653 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0 and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0 and CE1.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.
RecommendedOperating
Recommended DC Operating
TemperatureandSupplyVoltage
Conditions
Symbol
Parameter
Supply Voltage
GND Ground
Min.
4.5
Typ. Max. Unit
Grade
Ambient
GND
Vcc
Temperature(1)
VCC
5.0
5.5
0
V
V
V
Commercial
0OC to +70OC
0V
0V
5.0V
5.0V
+
+
10%
0
0
Industrial
-40OC to +85OC
10%
____
V
IH
Input High Voltage
Input Low Voltage
2.2
6.0(1)
0.8
5653 tbl 04
____
NOTES:
VIL
-0.5(2)
V
1. This is the parameter TA. This is the "instant on" case temperature.
5653 tbl 05
NOTES:
1. VTERM must not exceed Vcc + 10%.
2. VIL > -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings(1)
Capacitance(1)
(TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
CIN
V
9
pF
(3)
OUT
C
V
10
pF
5653 tbl 07
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
T
BIAS
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
Storage
Temperature
TSTG
3. COUT also references CI/O.
DC Output
Current
mA
IOUT
5653 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operationofthe device atthese oranyotherconditions above those indicatedinthe
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
6.542
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
709169/59L
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
Min.
Max.
5
Unit
µA
µA
V
___
___
___
|
|
Output Leakage Current
Output Low Voltage
Output High Voltage
5
CE
OL = +4mA
OH = -4mA
0
= VIH or CE
1
= VIL, VOUT = 0V to VCC
VOL
I
0.4
___
VOH
I
2.4
V
5653 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VCC = 5V ± 10%)
709169/59L6
Com'l Only
709169/59L7
Com'l & Ind
709169/59L9
Com'l Only
Symbol
Parameter
Test Condition
= VIL
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
210 400
Typ.(4)
185
Max.
360
Unit
mA
ICC
Dynamic Operating
Current
(Both Ports Active)
L
L
L
L
L
L
230
430
CE
L
and CE
R
Outputs Disabled
(1)
____
____
____
____
IND
210
40
440
105
120
220
f = fMAX
mA
mA
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
45
115
35
95
CEL
= CER = VIH
(1)
f = fMAX
____
____
____
____
40
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
150
235
135
120
205
CE"A" = VIL and
(3)
CE"B" = VIH
Active Port Outputs
Disabled, f=fMAX
____
_____
____
____
135
0.5
0.5
130
235
3.0
3.0
190
(1)
mA
mA
ISB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
CE > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(2)
R and
COM'L
IND
L
L
0.5
3.0
0.5
3.0
L
V
V
____
_____
____
____
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
IND
L
L
160
210
110
170
CE"A" < 0.2V and
(5)
CE"B" > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, Active Port
Outputs Disabled, f = fMAX
V
V
____
_____
____
____
130
205
(1)
5653 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6
6.42
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
2ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1, 2 and 3
5653 tbl 10
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
30pF
347Ω
5pF*
347Ω
5653 drw 04
5653 drw 05
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
Figure 1. AC Output Test load.
*Including scope and jig.
8
7
6
5
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
tCD
tCD
(Typical, ns)
1
2
,
4
3
2
1
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
-1
5653 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.742
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3) (VCC = 5V ± 10%, TA = 0°C to +70°C)
709169/59L6
Com'l Only
709169/59L7
Com'l & Ind
709169/59L9
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
____
____
____
____
____
____
____
____
t
CYC1
CYC2
CH1
CL1
CH2
CL2
Clock Cycle Time (Flow-Through)
19
10
6.5
6.5
4
22
12
7.5
7.5
5
25
15
12
12
6
(2)
____
____
____
____
____
____
____
____
____
____
t
Clock Cycle Time (Pipelined)
(2)
(2)
t
Clock High Time (Flow-Through)
t
Clock Low Time (Flow-Through)
(2)
t
Clock High Time (Pipelined)
(2)
t
Clock Low Time (Pipelined)
4
5
6
____
____
____
tR
Clock Rise Time
3
3
3
____
____
____
tF
Clock Fall Time
3
3
3
____
____
____
t
SA
HA
SC
HC
SB
HB
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRST
HRST
OE
OLZ
OHZ
CD1
CD2
DC
CKHZ
CKLZ
Address Setup Time
Address Hold Time
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
3.5
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
t
3.5
0
t
t
3.5
0
t
t
3.5
0
t
R/W Hold Time
t
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
3.5
0
t
t
3.5
0
t
ADS Hold Time
t
3.5
0
CNTEN Setup Time
CNTEN Hold Time
CNTRST Setup Time
CNTRST Hold Time
Output Enable to Data Valid
t
t
3.5
t
0
0
1
____
____
____
t
6.5
7.5
9
(1)
____
____
____
t
Output Enable to Output Low-Z
2
2
2
(1)
t
Output Enable to Output High-Z
1
7
1
7
1
7
(2)
____
____
____
t
Clock to Data Valid (Flow-Through)
15
18
20
(2)
____
____
____
t
Clock to Data Valid (Pipelined)
6.5
7.5
9
____
____
____
t
Data Output Hold After Clock High
2
2
2
2
2
2
2
2
2
(1)
t
Clock High to Output High-Z
9
9
9
(1)
____
____
____
t
Clock High to Output Low-Z
Port-to-Port Delay
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
____
____
____
____
____
____
t
CWDD
24
9
28
10
35
15
ns
tCCS
ns
5653 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) to either the Left or Right ports when FT/PIPE = VIH. Flow-Through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for
that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER and FT/PIPEL.
8
6.42
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Flow-Through Output
(FT/PIPE"X" = VIL)(3,6)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
t
SC
tHC
CE1
R/W
tHW
tSW
t
SA
tHA
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
An + 3
(1)
tDC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2
(1)
(1)
tCKLZ
tDC
(1)
t
OHZ
t
OLZ
OE(2)
tOE
5653 drw 07
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE"X" = VIH)(3,6)
tCYC2
tCH2
tCL2
CLK
CE
0
t
SC
(4)
tHC
tSC
t
HC
CE1
R/W
t
HW
tSW
tSA
tHA
ADDRESS(5)
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
Qn + 2 (6)
DATAOUT
Qn + 1
(1)
tCKLZ
(1)
(1)
t
OHZ
tOLZ
OE(2)
tOE
5653 drw 08
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. "X" here denotes Left or Right port. The diagram is with respect to that port.
6.942
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
t
CYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A6
A5
A4
A3
A
2
A
0
A1
tSC
tHC
t
SC
tHC
(3)
CKHZ
tCD2
tCD2
t
tCD2
Q
0
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
(3)
(3)
tDC
tCKLZ
t
DC
t
CKHZ
tSA
tHA
A6
A5
A4
A3
A2
A
0
A1
tSC
tHC
CE0(B2)
tSC
tHC
(3)
tCD2
tCKHZ
tCD2
DATAOUT(B2)
Q4
Q2
(3)
(3)
tCKLZ
tCKLZ
5653 drw 09
Timing Waveform of Write with Port-to-Port Flow-Through Read(4,5,7)
CLK "A"
tSW
tHW
R/W "A"
ADDRESS "A"
DATAIN "A"
CLK "B"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(6)
tCCS
tCD1
R/W "B"
tHW
tSW
t
HA
tSA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
(6)
t
CD1
tCWDD
VALID
VALID
tDC
t
DC
5653 drw 10
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709169/59 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
10
6.42
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An + 3
An + 4
An
An +1
An + 2
An + 2
ADDRESS
tSA
tHA
t
SD
t
HD
DATAIN
Dn + 2
(1)
(1)
tCKLZ
t
CD2
tCD2
(2)
tCKHZ
Qn + 3
Qn
DATAOUT
READ
NOP(5)
WRITE
READ
5653 drw 11
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
t
CYC2
tCH2
tCL2
CLK
CE0
t
SC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
SA
tHA
t
SD
t
HD
DATAIN
Dn + 2
(1)
CKLZ
t
CD2
t
CD2
t
(2)
Qn
Qn + 4
DATAOUT
(1)
t
OHZ
OE
READ
WRITE
READ
5653 drw 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
61.412
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
t
CYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
t
SW
t
HW
HA
(4)
An + 4
An
An + 3
An +1
An + 2
An + 2
ADDRESS
t
SA
t
tSD
tHD
DATAIN
Dn + 2
tCD1
t
CD1
t
CD1
tCD1
(2)
Qn
Qn + 3
Qn + 1
DATAOUT
(1)
CKLZ
(1)
tDC
tDC
t
t
CKHZ
NOP(5)
READ
READ
WRITE
5653 drw 13
TimingWaveformofFlow-ThroughRead-to-Write-to-Read(OEControlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An + 2
An + 4
An + 5
An + 3
Dn + 3
An
tHA
An +1
ADDRESS
tSA
t
SD
tHD
DATAIN
Dn + 2
t
OE
CD1
tDC
tCD1
tCD1
t
(2)
Qn
Qn + 4
DATAOUT
(1)
CKLZ
(1)
t
tOHZ
tDC
OE
READ
WRITE
READ
5653 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
12
6.42
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 3
Qn + 1
Qn
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
5653 drw 15
Timing Waveformof Flow-ThroughReadwithAddressCounterAdvance(1)
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
An
ADDRESS
t
SAD tHAD
ADS
t
SAD
tHAD
tSCN
tHCN
CNTEN
t
CD1
Qn + 3(2)
Qx(2)
Qn + 4
Qn + 1
Qn + 2
Qn
DATAOUT
t
DC
READ
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
WITH
COUNTER
5653 drw 16
NOTES:
1. CE0 and OE = VIL, CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output
remains constant for subsequent clocks.
61.432
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 4
An + 2
An + 1
An + 3
t
SAD tHAD
ADS
CNTEN
tSD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
5653 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
t
CYC2
tCH2
tCL2
CLK
tSA tHA
ADDRESS(4)
An + 2
An
An + 1
INTERNAL(3)
ADDRESS
Ax(6)
0
An + 1
1
An
tSW tHW
R/W
ADS
CNTEN
tSRST
tHRST
CNTRST
t
SD
tHD
D0
DATAIN
(5)
Qn
Q1
Q0
DATAOUT
.
COUNTER(6)
RESET
WRITE
READ
READ
READ
READ
ADDRESS 0
ADDRESS 0
ADDRESS n ADDRESS n+1
ADDRESS 1
5653 drw 18
NOTES:
1. CE0 and R/W = VIL; CE1 and CNTRST = VIH.
CE0 = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’ Address is written
to during this cycle.
14
6.42
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Depth and Width Expansion
AFunctionalDescription
The IDT709169/59features dualchipenables (refertoTruthTable
I)inordertofacilitaterapidandsimpledepthexpansionwithnorequire-
mentsforexternallogic.Figure4illustrateshowtocontrolthevariouschip
enables in order to expand two devices in depth.
The IDT709169/59 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.
The IDT709169/59 can also be used in applications requiring ex-
pandedwidth,asindicatedinFigure4.Sincethebanksareallocatedat
thediscretionoftheuser,theexternalcontrollercanbesetuptodrivethe
input signals for the various devices as required to allow for 18-bit
or wider applications.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory appli-
cations.
CE0 = VIH or CE1 = VIL for one clock cycle will power down the
internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT709169/59's for depth
expansionconfigurations.WhenthePipelinedoutputmodeisenabled,two
cycles are requiredtogetvaliddata onthe outputs.
(1)
A14/A13
IDT709169/59
IDT709169/59
CE0
CE0
CE1
CE1
VCC
VCC
Control Inputs
Control Inputs
IDT709169/59
IDT709169/59
CE1
CE1
CE0
CE0
CNTRST
CLK
Control Inputs
Control Inputs
ADS
CNTEN
R/W
5653 drw 19
Figure 4. Depth and Width Expansion with IDT709169/59
OE
NOTE:
1. A14 is for IDT709169, A13 is for IDT709159.
61.452
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
A
99
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
BF
100-pin TQFP (PN100-1)
100-pin fpBGA (BF100)
6
7
9
Commercial Only
Commercial & Industrial
Commercial Only
Speed in nanoseconds
L
Low Power
709169 144K (16K x 9-Bit) Synchronous Dual-Port RAM
709159 72K (8K x 9- Bit) Synchronous Dual-Port RAM
5653 drw 20
NOTE:
1. Contact your local sales office for Industrial temp range for other speeds, packages and powers.
IDT Clock Solution for IDT709169/59 Dual-Port
Dual-Port I/O Specitications
Clock Specifications
Input Duty
IDT
PLL
Clock Device
IDT
IDT Dual-Port
Part Number
Non-PLL Clock
Device
Input
Capacitance
Maximum
Jitter
Voltage
I/O
Cycle
Frequency Tolerance
Requirement
49FCT805T
49FCT806T
74FCT807T
709169/59
5
TTL
9pF
40%
100
150ps
FCT88915TT
5653 tbl 12
DatasheetDocumentHistory
07/08/02:
08/18/03:
InitialPublicRelease
RemovedPreliminarystatus
Page 16 Added IDT Clock Solution Table
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16
6.42
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