703517S233RM [IDT]
QDR SRAM, 256KX36, 0.45ns, PBGA576, 25 X 25 MM, 2.55 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-576;
| 型号： | 703517S233RM |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | QDR SRAM, 256KX36, 0.45ns, PBGA576, 25 X 25 MM, 2.55 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-576 静态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATASHET
IDT70P3537
512K/256K x36
SYNCHRONOUS
DUAL QDR-II
TM
IDT70P3517
®
Features
each port
◆
– Four word transfers each of Read & Write per clock cycle per
port (four word bursts on 2 ports)
Octal Data Rate
Port Enable pins (E0,E1) for depth expansion
Dual Echo Clock Output with DLL-based phase alignment
High Speed Transceiver Logic inputs
– scaled to receive signals from 1.4V to 1.9V
Scalable output drivers
18Mb Density (512K x 36)
– Also available 9Mb Density (256K x 36)
◆
◆
◆
◆
◆
◆
QDR-II x 36 Burst-of-2 Interface
– Commercial: 233MHz, 250MHz
Two independent ports
– True Dual-Port Access to common memory
Separate, Independent Read and Write Data Buses on each
Port
◆
◆
– Drives HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V
– Output impedance adjustable from 35 ohms to 70 ohms
1.8V Core Voltage (VDD)
576-ball Flip Chip BGA (25mm x 25mm, 1.0mm ball pitch)
JTAG Interface - IEEE 1149.1 Compliant
– Supports concurrent transactions
◆
◆
Two-Word Burst on all DPRAM accesses
DDR (Double Data Rate) Multiplexed Address Bus
– One Read and One Write request per clock cycle
DDR (Double Data Rate) Data Buses
◆
◆
◆
◆
– Four word burst data (Two Read and Two Write) per clock on
Functional Block Diagram
VREFL
VREFR
EP[1:0]
ER[1:0]
EL[1:0]
LEFT PORT
DATA
RIGHT PORT
DATA
REGISTER
AND LOGIC
REGISTER
AND LOGIC
D
0L- D35L
D
0R-
D35R
WRITE DRIVER
KR
KL
K
L
KL
KR
K
R
(1)
(1)
ZQ
L
ZQ
R
Q
0L-
Q
35L
Q
0R- Q35R
512/256K x 36
MEMORY
ARRAY
CQL, CQL
CQR, CQR
K
C
L
KR
CR
L
(2)
A
17R
(2)
A
R
W
0R-
A0L-
A
17L
C
R
, C
R
R
C
L
, C
L
L
R
OR K
R
, K
OR K
L
, K
R
L
L
LEFT PORT
ADDRESS
REGISTER
AND LOGIC
RIGHT PORT
ADDRESS
REGISTER
AND LOGIC
R
W
ADDRESS DECODE
BW0R- BW3R
BW0L- BW3L
KR
KL
K
R
K
L
TCK
TMS
TRST
TDI
5677 drw01
JTAG
VREFR
VREFL
TDO
NOTES:
1. Input pin to adjust the device outputs to the system data bus impedance.
2. Address A17 is a INC for IDT70P3517. Disabled input pin (Diode tied to VDD and VSS).
January 29, 2009
©2008 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice. NOT AN OFFER FOR SALE The information
presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale
DSC-5677/1
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
Pin Configuration
70P3537
70P3517
RM-576 Ball Flip Chip BGA
Top View
A1 BALL PAD CORNER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A
B
C
D
E
F
A
B
C
D
E
F
BW0R
BW3R
DOFFR
VSS
VSS
VSS
ZQR
VSS
VSS VDDQR A2R
EP0
A3R
RR
E0R
VDD
VREFR
A8R
A9R
A14R A15R
VDDQR
VSS
VSS
VSS
MRST
VSS
VSS
VSS
D17R
BW1R
A7R
VSS
BW2R
WR
VSS VDDQR DEPTH VSS
A4R
A1R
A5R
A6R
E1R
KR
VSS
KR
VDD
A12R A13R
INC
VSS
VDDQR D35R
CR
D16R D15R VDDQR Q17R
VSS VDDQR A0R
CR
A10R A11R A16R A17R VDDQR VDDQR Q35R
VSS D33R D34R
D14R D13R VSS
Q15R Q16R VSS VDDQR VSS
VDDQR
VSS
VDDQR
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDDQR VSS VDDQR
VSS
VDDQR
VSS
VSS
Q34R Q33R VDDQR D31R D32R
D12R D11R VDDQR Q13R Q14R VDDQR VSS VDDQR
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS VDDQR
VDDQR Q32R Q31R
VSS D29R D30R
VSS
D10R VSS
Q11R Q12R VSS VDDQR VSS
VDD
VDD
VDD
VSS
VDDQR
VSS
VSS
Q30R Q29R VDDQR D27R D28R
G
H
J
G
H
J
VREFR VSS VDDQR Q9R Q10R VDDQR VSS VDDQR
VSS
VDD
VSS
VSS VDDQR
VDDQR Q28R Q27R
D26R
VSS
VSS
VSS
VDD
VSS
VDD
CQR
D9R
D7R
D5R
D3R
D8R
VSS
Q8R
CQR VSS VDDQR VSS
Q7R VDDQR VSS VDDQR
VDD
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VSS
VDDQR
VSS
VDDQR
VSS
VSS
Q26R VDDQR VSS
VREFR
D6R VDDQR Q6R
VDDQR Q25R Q24R
VSS D24R D25R
K
L
K
L
Q23R
Q22R
Q20R
D22R D23R
D20R D21R
D4R
VSS
Q4R
Q5R
Q3R
Q1R
VSS VDDQR VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDDQR
VSS
VDDQR
VSS
D2R VDDQR Q2R
VSS VDDQR
VDDQR Q21R
VDDQR
VSS
VDDQR
VSS
VSS
M
N
P
R
T
M
N
P
R
T
D1R
D0R
Q0R
VDD
VSS
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
VDDQR
VSS
VSS
VDDQL
VSS
Q19R
Q34L
Q32L
Q18R VDDQR D18R D19R
VDDQR
VSS
VSS
VSS
VDD
VSS
Q35L
D35L D34L
D16L D17L VDDQL Q17L Q16L VDDQL VSS VDDQL
VSS VDDQL
VSS
D14L D15L
Q15L Q14L VSS VDDQL VSS
VDD
VSS
VSS
VDDQL
Q33L VDDQL D33L D32L
VSS
D12L D13L VDDQL Q13L Q12L VDDQL
VDDQL
VDD
VSS
VDDQL
VSS
VDDQL Q30L
Q31L
VSS D31L D30L
VSS
D10L D11L VSS
Q11L Q10L VSS VDDQL VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VSS
KL
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDDQL
VSS
VDDQL
VSS
VSS
VDDQL
VSS
Q28L
Q29L VDDQL D29L D28L
U
V
U
V
VREFL
VSS
VSS VDDQL
Q9L
Q8L
CQL VDDQL VSS VDDQL
Q27L
VSS D27L D26L
CQL
Q25L
Q23L
D9L
VSS
Q7L
Q5L
Q3L
VSS VDDQL VSS
VDDQL
Q26L VDDQL VSS
VREFL
VSS
W
W
D7L
D5L
D3L
D1L
D8L VDDQL Q6L
VDDQL
VSS
Q24L
D25L
VDDQL
VSS
VDD
VSS
A6L
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VDDQL
VSS
VSS
VDDQL
VSS
VSS
Y
Y
D6L
VSS
Q4L
VSS VDDQL
VSS
VSS
CL
VDDQL
Q21L
Q22L VDDQL D24L D23L
AA
AB
AC
AD
AA
AB
AC
AD
D4L VDDQL Q2L
Q1L VDDQL VSS VDDQL
VDDQL VDDQL
VDDQL VDDQL VSS
VDDQL
VSS
VDDQL Q19L
Q20L
VSS
D22L D21L
CL
D2L
Q0L
VSS
VDDQL VSS
A0L
A1L
A4L
A7L
A10L A11L
A16L A17L
VSS
VDDQL Q18L VDDQL D20L D19L
VSS
KL
BW1L
BW2L
WL
DOFFL
VSS
D0L VDDQL
TDI VDDQL EP1
A5L
E1L
VDD
VSS
A12L
A13L
INC
VDDQL
VSS
VDDQL
D18L
VSS
VSS
RL
BW0L
BW3L
TRST
VSS
VSS
ZQL
VSS
TMS
VSS
A2L
A3L
E0L
VREFL
VDD
A8L
A9L
A14L A15L
17 18
VSS
TCK
TDO
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
19
20
21
22
23
24
5677 drw
NOTE:
1. The package is 25mm x 25mm x 2.55mm with 1.0mm ball pitch; the customer will have to provide external airflow of 100LFM (0.5m/s) or higher at 250MHz.
2
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
and tuned with matching impedance and signal quality. The user
can use the echo clock for downstream clocking of the data. For
theuser,echoclockseliminatetheneedtoproducealternateclocks
with precise timing, positioning, and signal qualities to guarantee
data capture. Since the echo clocks are generated by the same
source that drives the data output, the relationship to the data is
NOT significantly affected by external parameters such as voltage,
temperature, and process as would be the case if the clock were
generated by an outside source.Thus the echo clocks are guaran-
teed to be synchronized with the data.
All interfaces of Dual QDR-II Static RAMs are HSTL, allow-
ing speeds beyond SRAM devices that use any form of TTL
interface. The interface can be scaled to higher voltages (up to
1.9V) to interface with 1.8V systems, if necessary. The device has
VDDQ pins and a separate Vref, allowing the user to designate the
interface operational voltage independent of the device core volt-
age of 1.8V VDD. Output impedance control pins allow the user to
adjust the drive strength to adapt to a wide range of loads and
transmission lines.
Functional Description
As a memory standard, the (Quad Data Rate) QDR-II SRAM
interface has become increasingly common in high performance
networkingsystems. WiththeQDR-IIinterface/configuration,memory
throughput is increased without increasing the clock rate via the use
of two unidirectional buses on each of providing 2 ports of QDR-II
makes this a Dual-QDRII Static Ramtwoports to transferdata without
the need for bus turnaround.
Dual QDR-II Static RAMs are high speed synchronous mem-
ories supporting two independent double-data-rate (DDR) read and
write data ports. This scheme allows simultaneous read and write
access for the maximum device throughput - two data items are
passed with each read or write. Four data word transfers occur per
clock cycle, providing quad-data-rate (QDR) performance on each
port. Comparing this with standard SRAM common I/O single data
rate (SDR) devices, a four to one increase in data access is achieved
atequivalentclockspeeds. IDT70P3537/70P3517DualQDR-IIStatic
RAM devices, are capable of sustaining full bandwidth on both the
input and output buses simultaneously. Using independent buses for
read and write data access simplifies design by eliminating the need
for bidirectional buses. And all data are in two word bursts, (with
addressing capability to the burst level).
Clocking
The IDT70P3537/3517 has two sets of input clocks for both
theinputandoutput,theK,KclocksandtheC,Cclocks.Inaddition,
theIDT70P3537/3517has anoutput“echo”clockpair,CQandCQ.
The K and K clocks are the primary device input clocks.
The K clock is used to clock in the control signals (R, W, E[1:0],
BW0-3), the read address, and the first word of the data burst
(D[35:0]) during a write operation. The K clock is used to clock in
the control signals (BW0-3, E[1:0]), write address and the second
word of the data burst during a write operation (D[35:0]). In the
event that the user disables the C and C clocks, the K and K clocks
will also be used to clock the data out of the output register and
generate the echo clocks. The K and K, C and C,CQ and CQ, pairs
are offset by half a clock cycle from each other.
The C and C clocks may be used to clock the data out of
the outputregisterduringreadoperations andtogenerate the echo
clocks. C and C must be presented to the memory within the timing
tolerances as shown in the AC Electrical Characteristics Table
(Page 12). The output data from the IDT70P3537/70P3517 will be
closely aligned to the C and C input, through the use of an internal
DLL. When C is presented to the IDT70P3537/70P3517 the DLL
will have already internally clocked the data to arrive at the device
output simultaneously with the arrival of the C clock. The C and
second data item of the burst will also correspond.
Devices withQDR-IIinterfaces includenetworkprocessorunits
(NPUs) and field programmable gate arrays (FPGAs).
IDT70P3537/70P3517 Dual QDR-II Static RAMs support uni-
directional 36-bit read and write interfaces. These data inputs and
outputs operate simultaneously, thus eliminating the need for high-
speed bus turnarounds (i.e. no dead cycles are present). Access to
each port is accomplished using a common 18-bit address bus (17
bits for IDT70P3517). Addresses for reads and writes are latched on
rising edges of the K and K input clocks, respectively.The K and K
clocks are offset by 90 degrees or half a clock cycle. Each address
locationisassociatedwithtwo36-bitdatawordsthatburstsequentially
into or out of the device. Since data can be transferred into and out
of the device on every rising edge of the K and K clocks, memory
bandwidth is maximized while simplifying overall design through the
elimination of bus turnaround(s). IDT70P3537/70P3517 Dual QDR-II
Static RAMs can support devices in a multi-drop configuration (i.e.
multiple devices connected to the same interface). Through this
capability, system designers can support compatible devices such as
NPUs and FPGAs on the same bus at the same time.
Using independent ports for read and write access simplifies
design by eliminating the need for bidirectional buses. All buses
associated with Dual QDR-II Static RAMs are unidirectional and can
be optimized for signal integrity at very high bus speeds. The Dual
QDR-II Static RAM has scalable output impedance on its data output
bus and echo clocks allowing the user to tune the bus for low noise
and high performance.
Single Clock Mode
The IDT70P3537/70P3517 may be operated with a single
clock pair. C and C may be disabled by tying both signals high,
forcing the outputs and echo clocks to be controlled instead by the
K and K clocks.
IDT70P3537/70P3517 Dual QDR-II Static RAMs have a single
DDR address bus per port with multiplexed read and write addresses.
All read addresses are received on the first half of the clock cycle and
all write addresses are received on the second half of the clock cycle.
The byte write signals are received on both halves of the clock cycle
simultaneouslywiththedatatheyarecontrollingonthedatainputbus.
The Dual QDR-II Static RAM device has echo clocks, which
provide the user with a clock that is precisely timed to the data output
DLL Operation
TheDLLintheoutputstructureoftheIDT70P3537/70P3517
can be used to closely align the incoming clocks C and C with the
output of the data, generating very tight tolerances between the
3
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
two. The user may disable the DLL by holding DOFF low. With the DLL
off, the C and C (or K and K, if C and C are not used) will directly clock
the output register of the IDT70P3537/70P3517. With the DLL off,
there will be a propagation delay from the time the clock enters the
device until the data appears at the output. QDR-II becomes QDRITM
with DLL off. First data out is referenced to C instead of C.
Normal QDR write cycles are initiated by holding the write port select
(W) low at K rising edge. Also, the Byte Write inputs (BW0-3), desig-
nating which bytes are to be written, need to be held low for both the
K and K clocks. On the rising edge of K the first word of the data must
alsobepresentonthedatainputbus D[35:0]observingthedesignated
set up times. Upon the rising edge of K the first word of the burst will
be latchedintothe inputregister. AfterKhas risen, andthe designated
hold times observed, the second half of the clock cycle is initiated by
presenting the write address to the address bus A[X:0], the BW0-3
inputs for the second data word of the burst, and the second data item
of the burst to the data bus D[35:0]. Upon the rising edge of K, the
second word of the burst will be latched, along with the designated
address. Both the first and second words of the burst will be written
into memory as designated by the address and byte write enables.
The addresses for the write cycles is provided at the K rising edge,
and data is expected at the rising edge of K and K, beginning at the
same K that initiated the cycle.
Echo Clock
The echo clocks, CQ and CQ, are generated by the C and C
clocks (or K, K if C, C are disabled). The rising edge of C generates
the rising edge of CQ, and the falling edge of CQ. The rising edge of
C generates the rising edge of CQ and the falling edge of CQ. This
scheme improves the correlation of the rising and falling edges of the
echo clock and will improve the duty cycle of the individual signals.
Theechoclockis verycloselyalignedwiththe data,guaranteeing
that the echo clock will remain closely correlated with the data, within
the tolerances designated.
Programmable Impedance
Normal QDR-II Read and Write Operations
An external resistor, RQ, must be connected between the
ZQ pin on the IDT70P3537/70P3517 and tied to VSS to allow the
IDT70P3537/70P3517toadjustits outputdrive impedance.The value
of RQ must be 5X the value of the intended drive impedance of the
IDT70P3537/70P3517. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 15% is 175 ohms to 350
ohms. The output impedance is adjusted every 1024 clock cycles to
correct for drifts in supply voltage and temperature. If the user wishes
to drive the output impedance of the IDT70P3537/70P3517 to its
lowest value, the ZQ pin may be tied to VDDQ.
TheIDT70P3537/70P3517DualQDR-IIStaticRAMsupports
QDR-II burst-of-two read/write operations. Read operations are initi-
ated by holding the read port select (R) low, and presenting the read
address to the address port during the rising edge of K which will latch
the address. Data is delivered after the next rising edge of the next K
(t + 1), using C and C as the output timing references; or K and K, if
C and C are tied high.
The write operation is a standard QDR-II burst-of-two write
operation, except the data is not available to be read until the next
clock cycle (this is one cycle later than standard QDR-II SRAM).
4
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
Pin Definitions
Symbol(1)
Pin Function
Description
D[35:0]
X
Input
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid write operations
Byte Write Selects active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks during write operations. Used to select which byte is
BW
0
X
, BW
1X,
Input
written into the device during the current portion of the write operations. Bytes not written remain unaltered. All byte writes are sampled on the same edge as the
BW
2X
, BW
3X
Synchronous data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device.
BW controls D[8:0], BW controls D[17:9], BW controls D[26:18], and BW controls D[35:27].
0
1
2
3
Input
Address Inputs. Read addresses are sampled on the rising edge of K clock during active read operations. Write addresses are sampled on the rising edge of K
A[17:0] (2)
X
Synchronous clock during active write operations. These address inputs are multiplxed, so that both a read and write operation can occur on the same clock cycle. These inputs
are ignored when the appropriate port is deselected.
Q[35:0]
X
Output
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during
Synchronous Read operations or K and K when operating in single clock mode. When the Read port is deselected, Q[35:0] are automatically tri-stated.
Input
Write Control Logic, active LOW. Sampled on the rising edge of the positive input clock (K). When asserted active, a write operation in initiated. Deasserting will
WX
Synchronous deselect the Write port. Deselecting the Write port will cause D[35:0] to be ignored.
Input Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the
Synchronous Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next
R
X
rising edge of the C clock. (DOFFX = 1). Each read access consists of a burst of two sequential transfers.
CX
Input Clock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of
various devices on the board back to the controller. See application example for further details.
Input Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times
C
X
of various devices on the board back to the controller. See application example for further details.
KX
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device. Drives out data through Q[35:0] when in single clock mode.
All accesses are initiated on the rising edge of K.
KX
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device. Drives out data through Q[35:0] when in single clock mode.
CQX
Output Clock Synchronous Echo clock output. The rising edge of CQ is tightly matched to the synchronous data outputs and can be used as a data valid indication. CQ is free
running and does not stop when the output data is tri-stated.
Synchronous Echo Clock output. The rising edge of CQ is tightly matched to the synchronous data outputs and can be used as a data valid indication. CQ is free
running and does not stop wehen the output data is tri-stated.
Output Clock
CQ
X
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[35:0] output impedance is set to 0.2 x RQ,
where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode.
ZQX
Input
This pin cannot be connected directly to GND or left unconnected.
EP[1:0] are used to program the Port Enable pins E[1:0]. EP[1:0] are programmed by tying the pins high or low on the board. If a customer does not want to use
Pins EP[1:0], then these pins should be tied low. Refer to Truth Table III for Port Enable pins.
EP[1:0]
Input
E
X
[1:0]
Input
Two Port Enable pins E[1:0] are provided to connect to the two MSB bits on the memory controller in order to cascade up to four IDT70P3537 devices. If a customer
Syncronous does not want to use Pins E[1:0], then these pins should be tied low. Refer to Truth Table III for Port Enable pins. Also refer to Figure 1 showing cascade/multi-drop
using port-enable (E[1:0]) pins. E[1:0] are sampled on the rising edge of K for read operations and again on rising edge of K for write operations.
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be different from those listed in this data sheet.
There will be an increased propagation delay from the incidence of C and C to Q, or K and K to Q as configured.
Input
DOFFX
Input
Asynchronous
Master Reset pin. When held low will reset the device.
MRST
DEPTH
TDO
Input
Output
Input
Connect to VDDQ for 9Mb. Connect to VSS for 18Mb.
TDO pin for JTAG.
TCK
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
Input
Asynchronous
Reset pin for JTAG.
TRST
INC
Should be tied to VCC or VSS only, or can be left as a floating pin.
V
REF
X
Input
Reference
Reference Voltage input. Static input used to set the reference level for HSTL inputs as well as AC measurement points.
V
DD
SS
DDQ
Power Supply Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
Ground Ground for the device. Should be connected to ground of the system.
Power Supply Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the desired output voltage.
V
V
X
5677 tbl 01
NOTE:
1. "X" = "L" for the Left Port pins and "X" = "R" for the Right Port pins.
2. A[16:0]x for IDT70P3517.
5
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
(1)
Truth Table I - Synchronous Port Control
(3,4)
(3,4)
D
Q
OPERATION
(2)
(2)
K
K
R
W
D(A+0)
D(A+1)
C
C
Q(A+0)
Q(A+1)
E
O
E1
Stopped
X
X
X
X
X
X
F
X
X
X
X
X
X
F
X
Stopped
Previous state
High - Z
Clock stopped
Stopped
X
X
X
X
X
Stopped
Previous state Clock stopped
No operation
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
H
X
X
L
H
X
X
X
L
X
X
X
X
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
High - Z
High - Z
High - Z
No operation
No operation
No operation
No operation
No operation
Read
High - Z
F
X
X
T
High - Z
F
T
DOUT at C (t+1)
X
X
T
X
X
T
DOUT at C (t+2) Read
X
D
IN at K(t)
X
Write
Write
D
IN at K(t)
X
5677 tbl 03
NOTES:
1. x = "Don’t Care", H = Logic High, L = Logic Low, Ç represents rising edge.
2. T (True) = E and EP have some polarity (device selected) on the rising edge of the appropriate clock. F (False) =E and EP have
opposite polarity (device de-selected) on the rising edge of the appropriate clock. See Truth Table III.
3. "A"represents address locationlatched bythe device when operation was initiated.A+0, A+1 represents the internal address sequence
in the burst.
4. "t" represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively
following clock cycle t.
(2,3)
Truth Table II - Write Port Enable Control
(1)
K
BW
0
BW1(1) BW2(1) BW3(1)
K
Mode
Input Input Input Input Input Input
Ç
Ç
Ç
Ç
Ç
Ç
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
Write function disabled all bytes
Write function disabled all bytes
Write data inputs to Byte 0 Only
Write data inputs to Byte 0 Only
Write data inputs to Byte 1 Only
Write data inputs to Byte 1 Only
Write data inputs to Byte 2 Only
Write data inputs to Byte 2 Only
Write data inputs to Byte 3 Only
Write data inputs to Byte 3 Only
Write data inputs to all Bytes
Ç
Ç
Ç
Ç
Ç
Ç
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
H
H
L
L
L
L
L
L
L
Write data inputs to all Bytes
5677 tbl 03a
NOTES:
1. BW0 controls D[8:0], BW1 controls D[17:9], BW2 controls D[26:18], BW3 controls D[35:27].
2. For this table: W is Low on the rising edge of K; E0 and E1 are true on the rising edge of K. See Truth Tables I and III.
Addresses for Writes are qualified on rising edge of K.
3. This table represents a subset of the potential write scenarios based upon BW0 - BW3 inputs and is meant to illustrate
basic device functionality.
6
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
Truth Table III - Port Enable Pins(1)
Normal Read and Writes
Device Selected
Bank 0
EP[0]
EP[1]
E[0]
L
E[1]
L
V
SS
DD
SS
DD
V
SS
SS
DD
DD
Bank 1
V
V
H
L
Bank 2
V
V
L
H
Bank 3
V
V
H
H
5677 tbl05
NOTES:
1. EP [1:0] - Port Enable Programming Polarity (see pin description for the entire device).
2. Ex[1:0] - Port Enable (see pin description assigned for each port).
Cascade/Multi-Drop using Port Enable (E0 & E1) Pins
As shown below in Figure 1 upto four devices can be cascaded using the Port Enable (E0,E1) pins scheme. The port enable pins
are subject to the same DC characteristics as the QDR interface. Refer to Pin Definitions table for pin descriptions. This diagram illustrates
one port of a QDR-II dual port
Figure 1. Multi-drop Cascading using the Chip Enable E[1:0] Pins
7
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
(1)
Absolute Maximum Ratings(1,2,3)
Capacitance (TA = +25°C, f = 1.0MHz)
Conditions(2)
IN = 0V
OUT = 0V
Symbol
Rating
Value
Unit
Symbol
Parameter
Input Capacitance
Output Capacitance
Max.
Unit
VDD
Supply Voltage on VDD with
Respect to GND
–0.5 to +2.2
V
C
IN
V
5
pF
CO
V
7
pF
V
DDQ
Supply Voltage on VDDQ with
Respect to GND
–0.5 to VDD
V
V
5677 tbl 08
NOTE:
VTERM
Voltage on Input, Output and I/O
terminals with respect to GND
–0.3 to VDD+0.3
1. Tested at characterization and retested after any design or process change that
may affect these parameters.
2. VDD = 1.8V, VDDQ = 1.5V
T
BIAS
Temperature Under Bias
Storage Temperature
–55 to +125
–65 to +150
+ 20
°C
°C
TSTG
IOUT
Continuous Current into Outputs
mA
5677 tbl 07
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.
Recommended DC Operating
and Temperature Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
3. VTerm(MAX) = minimum of VDD +0.3V and 2.2V.
Power Supply
Voltage
VDD
1.7
1.8
1.9
V
V
DDQ
I/O Supply Voltage
Ground
1.4
0
1.5
0
1.9
0
V
V
V
SS
Input Reference
Voltage
VREF
0.68
VDDQ/2
0.95
V
Thermal Resistance
V
IH
Input High Voltage
Input Low Voltage
V
REF+0.1
–
–
V
DDQ+0.3
V
V
Parameter
Symbol
Typ.
12.5
0.1
Unit
VIL
–0.3
VREF–0.1
θJA
Ambient
Junction to Ambient
Junction to Case
°C/W
o
c
TA
0
25
+70
Te mp e rature (1)
θJC
°C/W
5677 tbl 09
5677 tbl 10
NOTE:
1. Duringproductiontesting,thecase temperatureequals theambienttemperature.
NOTE:
1. Junction temperature is a function of on-chip power dissipation, package
thermal impedance, mounting site temperature and mounting site thermal
impedance. TJ = TA + PD x θJA.
Recommended Operating
Temperature and Supply Voltage
Ambient
Grade
Commercial
Industrial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
VDD
1.8V
1.8V
+
+
100mV
100mV
0V
5677 tbl06
8
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
DC Electrical Characteristics Over the Operating Temperature
and Supply Voltage (VDD = 1.8V ±100mV, VDDQ = 1.4V to 1.9V, TA = 0 to 70°C)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Note
µA
Input Leakage Current
Output Leakage Current
I
IL
V
DD = Max VIN = VSS to VDDQ
-10
-10
+10
+10
8
Output Disabled
µA
IOL
8
V
I
DD = Max,
OUT = 0mA (outputs open),
Cycle Time > tKHKH Min
250MH
Z
-
-
-
-
-
-
-
1636
1542
1432
1351
1212
1147
1007
Active Operating Current
2 Port Read
I
DD
mA
1
1
1
233MH
Z
V
DD = Max,
OUT = 0mA (outputs open),
Cycle Time > tKHKH Min
250MH
233MH
250MH
233MH
250MH
Z
IDD1
I
mA
mA
Z
VDD = Max,
Z
2 Port Write
IDD2
IOUT = 0mA (outputs open),
Z
Cycle Time > tKHKH Min
Device Deselected
Z
IOUT = 0mA (outputs open),
Standby Current
ISB
f=Max,
All Inputs < 0.2V or > VDDQ - 0.2V
mA
2
233MH
Z
-
956
WEN=REN=High
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Z
Q
= 250Ω, IOH = -(VDDQ/2)/(R
Q
/5)
V
DDQ/2 -0.12
DDQ/2 -0.12
DDQ -0.2
SS
V
DDQ/2 +0.12
V
V
V
V
3,7
4,7
5
V
OH1
OL1
OH2
OL2
Z
Q
= 250Ω, IOL = (VDDQ/2)/(R
OH = -0.1mA
OL = 0.1mA
Q/5)
V
VDDQ/2 +0.12
V
I
V
VDDQ
V
I
V
0.2
6
V
| IOH
| IOL
|
|
V
OUT = VDDQ/2
-(IOHo-15%)
(IOLo-15%)
-(IOHo+15%)
(IOLo+15%)
3
4
Output Impedance Control
V
VOUT = VDDQ/2
5677 tbl12
NOTES:
1. Operating Current is measured at 100% bus utilization on the active port.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOHO = (VDDQ/2)/(RQ/5) = @Vout = VDDQ/2 and is guaranteed by device characterization for 175Ω < ZQ < 350Ω. This parameter is tes
at ZQ = 250Ω, which gives a nominal 50Ω output impedance.
4. Outputs are impedance-controlled. IOLO = (VDDQ/2)/(RQ/5) = @Vout = VDDQ/2 and is guaranteed by device characterization for 175Ω < ZQ < 350Ω. This parameter is tes
at ZQ = 250Ω, which gives a nominal 50Ω output impedance.
5. This measurement is taken to ensure that the output has the capability of pullling to the VDDQ rail, and is not intended to be used as an impedance
measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to VSS, and is not intended to be used as an impedance measure point.
7. Programmable Impedance Mode.
8. 30µA for JTAG input pins.
Input Electrical Characteristics Over the Operating Temperature
and Supply Voltage (VDD = 1.8V ±100mV, VDDQ = 1.4V to 1.9V, TA = 0 to 70°C)
Parameter
Symbol
Min
Max
Unit
Notes
Input High Voltage, DC
VIH (DC)
VREF +0.1
VDDQ +0.3
V
1,2
Input Low Voltage, DC
Input High Voltage, AC
Input Low Voltage, AC
V
IL (DC
)
-0.3
V
REF -0.1
V
V
V
1,3
4,5
4,5
VIH (AC)
V
REF +0.2
-
VIL (AC)
-
VREF -0.2
5677 tbl 13
NOTES:
1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters.
2. VIH (Max) DC = VDDQ +0.3V, VIH (Max) AC = VDDQ +0.5V (pulse width < 20% tKHKH (min)).
3. VIL (MIN) DC = -0.3V, VIL (MIN) AC = -0.5V (pulse width < 20% tKHKH (min)).
4. This condition is for AC function test only, not for AC parameter test.
5. To maintain a valid level, the transitioning edge of the input must:
Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC)
Reach at least the target AC level
After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC)
9
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
Overshoot Timing
Undershoot Timing
VIL
VSS
VSS -0.25V
VSS -0.5V
20% tKHKH (MIN)
5677 drw 06
AC Test Loads
AC Test Conditions
V
REF
DDQ/2
V
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High Level
Symbol
VDD
Value
1.7-1.9
Unit
OUTPUT
V
V
V
V
V
ns
V
VDDQ
VIH
1.4-1.9
= 50
0
Ω
Z
Device
Under
Test
R = 50Ω
L
(VDDQ/2) +0.5
(VDDQ/2) -0.5
VDDQ/2
RQ = 250
Ω
Input Low Level
VIL
DDQ/2
V
ZQ
Input Reference Level
Input Rise/Fall Time
VREF
TR/TF
0.3/0.3
5677 drw 07
Output Timing Reference Level
VDDQ/2
5677 tbl 14
NOTE:
1. Parameters are tested with RQ=250Ω.
(VDDQ/2) +0.5V
(VDDQ/2) -0.5V
VDDQ/2
5677 drw08
10
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
AC Electrical Characteristics
(VDD = 1.8V ±100mV, VDDQ = 1.4V to 1.9V, TA(8) = 0 to 70°C)
Commercial
250MHz
233MHz
Min.
Max.
Min.
Max.
Symbol
Parameter
Unit
Notes
Clock Parameters
t
KHKH
KC var
KHKL
KLKH
KHKH
KHKH
KHCH
KC lock
KC reset
Average clock cycle time (K,K,C,C)
4.00
6.30
4.30
7.20
ns
ns
__
__
t
Clock Phase Jitter (K,K,C,C)
Clock High Time (K,K,C,C)
Clock LOW Time (K,K,C,C)
Clock to clock (K→K,C→C)
Clock to clock (K→K,C→C)
Clock to data clock (K→C,K→C)
DLL lock time (K, C)
0.20
0.20
1,5
9
__
__
t
1.60
1.60
1.80
1.80
0.00
1024
30
1.80
1.80
2.00
2.00
0.00
1024
30
ns
__
__
__
__
__
__
t
ns
9
t
ns
10
10
t
ns
t
1.80
2.00
ns
__
__
t
cycles
ns
2
__
__
t
K static to DLL reset
Output Parameters
__
__
t
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CHQZ
CHQX1
C,C HIGH to output valid
C,C HIGH to output hold
0.45
0.45
ns
ns
ns
ns
ns
ns
ns
ns
3
3
3
3
__
__
t
-0.45
-0.45
__
__
t
C,C HIGH to echo clock valid
C,C HIGH to echo clock hold
CQ,CQ HIGH to output valid
CQ,CQ HIGH to output hold
C HIGH to output High-Z
C HIGH to output Low-Z
0.45
0.45
__
__
t
-0.45
-0.45
__
__
t
0.30
0.32
__
__
t
-0.30
-0.32
__
__
t
0.45
0.45
3,4,5
3,4,5
__
__
t
-0.45
-0.45
Set-Up Times
__
__
__
__
__
__
t
AVKH
IVKH
DVKH
Address valid to K,K rising edge
Control inputs valid to K,K rising edge
Date-in valid to K, K rising edge
0.35
0.35
0.35
0.37
0.37
0.37
ns
ns
ns
6
7
t
t
Hold Times
__
__
__
__
__
__
t
KHAX
KHIX
KHDX
K,K rising edge to address hold
K,K rising edge to control inputs hold
K,K rising edge to data-in hold
0.35
0.35
0.35
0.37
0.37
0.37
ns
ns
ns
6
7
t
t
Port-to-Port Delay
Clock-to-Clock Offset
—
—
5677 tbl 15
tCO
4.00
4.30
ns
NOTES:
1. Cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No. 65 (EIA/JESD65)
page.
2. VDD slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once VDD, VDDQ and input clock are stable.
3. If C, C are tied High, K, K become the references for C, C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at 0°C and 1.9V tCHQZ, is a MAX parameter that is
worst case at 70°C and 1.7V.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. Control signals are R, W, BW0, BW1, BW2, BW3,E0, E1.
8. During production testing, the case temperature equals TA.
9. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60%of the cycle time (tKHKH).
10. Clock to Clock time (tKHKH) and Clock to Clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
11
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
Timing Waveform for Alternating Read and Write Operations(1,2)
Read
0
Write
1
Read
2
Write
3
Read
4
Write
5
Write
7
NOP
8
NOP
9
NOP
6
K
K
R
tKHKL
tKLKH
tKHKH
tKHKH
tKHKH
tIVKH
tKHIX
W
tAVKH
tIVKH
tKHAX
tKHIX
A4
A7
A5
A
A0
A2
A3
A1
tKHAX
tAVKH
tAVKH tKHAX
tIVKH
tKHIX
B11
B51
B10
D10
B30
B31
D31
B50
D50
B70
B71
D71
(3)
BWx
D30
D11
D51
Q01
D70
Q20
D
Q
tDVKH tKHDX
tDVKH tKHDX
(4)
Q00
Q40
Q21
Q41
tCHQX1
tCQHQV
tCHQX
tCHQX
tCHQZ
tCHQV
tCHQV
tKHKH
tKLKH
C
tKHKH
tKHKL
tKHKH
C
tCHCQV
tCQHQX
tCQHQV
tCHCQX
CQ
tCHCQV
tCQHQV
tCQHQX
tCHCQX
CQ
5677 drw 09
NOTES:
1. Device is selected per E[0] and E[1] as defined in Truth Table II, and MRST = VIH.
2. This waveform represents operation when DLL is ON.
3. To perform a valid write operation, both W and the appropriate BW0-3 must be low.
4. Q00 refers to the output from A0, and Q01 refers to the output from the next internal address following A0.
12
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
Timing Waveform of Back-to-Back Read-Write-Read to Same
Address(1,2)
NOTES:
1. Device is selected per E[0] and E[1] as defined in Truth Table II, and MRST = VIH.
2. This waveform represents operation when DLL is ON.
3. To perform a valid write operation, both W and the appropriate BW0-3 must be low.
4. ORIG Q00 represents the existing data in the memory. New Q00 represents the data written into the memory in the first cycle of the waveform.
13
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
Timing Waveform for Left Port Write to Right Port Read(1)
0
2
5
1
3
4
6
7
8
11
13
14
9
10
12
(2)
tCO
KL
tKHKH
K
L
L
L
W
A1
A0
Address_
DINL
D11
D00
D01
D10
KR
KR
R
R
Address_
R
A2
A0
QR
Q00
Q01
Q20
Q21
tCHQX1
CR
tCHQV
C
R
CQR
CQR
5677 drw 11
NOTES:
1. Device is selected per E[0] and E[1] as defined inTruth Table III. MRST = VIH. BW0L, BW1L, BW2L, and BW3L = VIL
2. If tco < specified minimum, data read from right port is not valid until the next KR cycle. If tco > specified minimum, data read from right port is available on the first KR cycle
as shown.
14
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
Timing Waveforms for DLL Operation (On/Off)(1,2)
Read
0
Write
1
Read
2
Write
3
Read
4
Write
5
Write
7
NOP
8
NOP
9
NOP
6
K
tKHKL
tKLKH
tKHKH
tKHKH
tKHKH
K
R
tIVKH
tKHIX
W
tAVKH
tIVKH
tKHAX
tKHIX
A0
A4
A5
B51
D51
A
A2
A3
A7
A1
tKHAX
tAVKH
tAVKH tKHAX
tIVKH
tKHIX
(3)
B31
B10
D10
B30
D30
B11
B50
D50
B70
D70
B71
BW
X
D11
D31
D
D71
tDVKH tKHDX
tDVKH tKHDX
tCHQZ
tCHQV
Case 1: Q
DLL OFF (QDRI)
(4
)
Q40
Q00
Q01
Q20
Q21
Q41
(5)
tCHQX1
tCHQX
tCHQV
tCHQX
Case 2: Q
DLL ON (QDRII)
(4
)
Q40
Q00
Q01
Q20
Q21
Q41
tCHQX1
tCHQX
tCHQX
tCHQV
tCHQZ
tKLKH
tCHQV
tKHKH
C
tKHKH
tKHKL
tKHKH
C
5677 drw 12
NOTES:
1. Device is selected per E[0] and E[1] as defined in Truth Table II, and MRST = VIH.
2. With DLL OFF (DOFFX < VIL) device behaves as a QDRI device. With DLL ON (DOFFX > VIH) device behaves as a QDR-II device.
3. To perform a valid write operation, both W and the appropriate BW0-3 must be low on the rising edge of K.
4. Q00 refers to the output from A0, and Q01 refers to the output from the next internal address following A0.
5. With DLL off (DOFF = VIL) the propagation delays will be increased and the AC timing parameters will be different values from those specified in this data sheet.
15
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
Master Reset Timing Waveform
K
(5ns)
MRST(1)
5677 drw13
NOTE:
1. MRST must be held LOW for a minimum of (5ns) after power supply is stable.
16
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
IEEE 1149.1 Test Access Port and Boundary SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial
Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. In conformance with
IEEE 1149.1, the QDR-II Dual-Port Static RAM contains a TAP controller, Instruction Register, Bypass Register and ID Register. The TAP
controller has a standard 16-state machine that resets internally upon power-up. It is possible to use this device without utilizing the TAP. To
disable the TAP controller without interfacing with normal operation of the QDR-II Dual-Port Static RAM TCK must be tied to VSS to preclude
a mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may
be left unconnected, but they may also be tied to Vdd through a resistor. TDO should be left unconnected.
JTAG Block Diagram
TAP Controller State Diagram
Test Logic Reset
1
0
Run Test Idle
1
1
1
Select DR
0
Select IR
0
0
1
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
0
1
Exit 1 DR
0
Exit 1 IR
0
Pause DR
1
Pause IR
1
0
0
0
Exit 2 DR
1
Exit 2 IR
1
1
0
Update DR
0
Update IR
1
5677 drw 15
17
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
0x0
Reserved for version number
0x355(1)
0x33
1
IDT Device ID (27:12)
Defines IDT part number (IDT70P3537)
IDT JEDEC ID (11:1)
Allows unique identification of device vendor as IDT
Indicates the presence of an ID register
ID Register Indicator Bit (Bit 0)
5677 tbl 16
NOTE:
1. Device ID for IDT70P3517 is 0x356.
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
1
Bypass (BYR)
Identification (IDR)
32
Boundary Scan (BSR)
Note 1
5677 tbl 17
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
on the IDT website (www.idt.com), or by contacting your local IDT sales represen-
tative.
System Interface Parameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
IDCODE
1111
Places the bypass register (BYR) between TDI and TDO.
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state except COLx & INTx outputs.
HIGHZ
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
0011
0001
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.
RESERVED
PRIVATE
0101, 0111, 1000, 1001,
1010, 1011, 1100
Several combinations are reserved. Do not use codes other than those
identified above.
0110,1110,1101
For internal use only.
5677 tbl 18
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
18
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
JTAG DC Operating Conditions
Parameter
Power Supply Voltage (I/P + O/P)
Input High Level
Symbol
Min
1.7
1.3
-0.3
Typ
Max
1.9
Unit
V
Note
V
DD
IH
IL
OH
OL
1.8
V
-
-
-
-
V
DD+0.3
V
Input Low Level
V
0.5
V
Output High Voltage (IOH = -1mA)
Output Low Voltage (IOL = 1mA)
V
V
DD - 0.2
VDD
V
V
VSS
0.2
V
5677 tbl 19
JTAG AC Test Conditions
Parameter
Symbol
IH/VIL
TR/TF
Value
1.8/0
Unit
V
Note
Input High/Low Level
V
Input Rise/Fall Time
1.0/1.0
DD/2
ns
Input and Output Timing Reference Level
V
V
1
5677 tbl 20
NOTE:
1. For outputs see AC test loads on page 10.
JTAG AC Characteristics
Parameter
Symbol
Min
100
40
40
10
10
10
10
10
10
0
Max
Unit
Note
TCK Cycle Time
t
CHCH
CHCL
CLCH
MVCH
CHMX
DVCH
CHDX
SVCH
CHSX
CLQV
JRST
JRSR
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
t
t
-
t
-
t
-
t
-
t
-
Input Setup Time
t
-
Input Hold Time
t
-
Clock Low to Output Valid
TRST Low to Reset JTAG
TRST High to TCK HIGH
t
20
-
t
50
50
t
-
5677 tbl 21
JTAG Timing Diagram
TCK
tCHCL
tCLCH
tCHCH
tCHMX
tMVCH
TMS
TDI
tDVCH
tCHDX
tCHSX
tSVCH
Outputs
tCLQV
TDO
tJRSR
tJRST
TRST
5677 drw 16
19
January 29, 2009
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-II
TM
Ordering Information
XXXXX
A
999
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
RM
Commercial (0°C to +70°C)
576–ball RoHS Compliant Flip Chip BGA
250
233
Commercial Only
Speed in Megahertz
Com’l & Ind’l
S
Standard Power
18Mbit (512K x 36) Dual QDR-IITM Static RAM
9Mbit (256K x 36) Dual QDR-IITM Static RAM
70P3537
70P3517
5677 drw17
Preliminary Datasheet: Description
"PRELIMINARY" datasheets contain descriptions for products that are in early release.
Datasheet Document History
7/11/2007: Initial release of Preliminary Datasheet
8/05/2008: Page 9 Corrected a typo in DC Chars table
01/19/09: Page 20 Removed "IDT" from orderable part number
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
®
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
20
January 29, 2009
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