5V41235PGG8 [IDT]
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER;
| 型号： | 5V41235PGG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER PC 输出元件 |
| 文件： | 总18页 (文件大小：317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
5V41235
Recommended Applications
Features/Benefits
2 Output synthesizer for PCIe Gen1/2/3 and Ethernet
• 16-pin TSSOP and QFN packages; small board footprint
• Spread-spectrum capable; reduces EMI
General Description
• Outputs can be terminated to LVDS; can drive a wider
variety of devices
The 5V41235 is a PCIe Gen2/3 compliant spread spectrum
capable clock generator. The device has 2 differential
HCSL outputs and can be used in communication or
embedded systems to substantially reduce
electro-magnetic interference (EMI). The spread amount
and output frequency are selectable via select pins. The
5V41235 can also supply 25 MHz, 125 MHz and 200 MHz
outputs for applications such as Ethernet.
• TSSOP package: 25MHz, 100MHz, 125MHz and
200MHz output frequencies.
• QFN package: 100MHz and 200MHz output frequencies.
• OE control pin; greater system power management
• Spread% and frequency pin selection; no software
required to configure device
• Industrial temperature range available; supports
demanding embedded applications
Output Features
• 2 - 0.7V current mode differential HCSL output pairs
Key Specifications
• Cycle-to-cycle jitter < 100 ps
• Output-to-output skew < 50 ps
• PCIe Gen2 phase jitter < 3.0ps RMS
• PCIe Gen3 phase jitter <1.0ps RMS
Block Diagram
VDD
2
SS1:SS0
2
CLK0
CLK0
Control
Logic
S1:S0
2
Phase Lock Loop
CLK1
CLK1
X1/ICLK
Clock
Buffer/
Crystal
Oscillator
25 MHz
crystal or clock
X2
2
Optional tuning crystal
capacitors
Rr(IREF)
GND
OE
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Pin Assignments
1
2
3
4
5
6
7
8
VDDXD
CLK0
16
15
14
13
12
11
10
9
S0
S1
16 15 14 13
SS0
X1/ICLK
X2
CLK0
S1 1
SS0 2
X1/CLK 3
X2 4
12 GNDODA
11 VDDODA
10 CLK1
GNDODA
VDDODA
CLK1
5V41235
OE
9 CLK1#
5
6
7
8
GNDXD
SS1
CLK1
IREF
16-pin (173 mil) TSSOP
16-pin QFN
Output Select Table 1 (MHz) - TSSOP Only
Output/Spread Select Table 3 - QFN Only
S1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SS1 SS0
Output
100MHz
200MHz
100MHz
Spread%
-0.5
S1
0
S0
0
CLK(1:0), CLK(1:0)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
25M
100M
125M
200M
-0.5
0
1
No spread
1
0
Reserved
1
1
100MHz
200MHz
-1
-1
Spread Selection Table 2 - TSSOP Only
Reserved
Reserved
SS1 SS0
Spread%
No Spread
Down -0.5
Down -0.75
No Spread
0
0
1
1
0
1
0
1
100MHz
200MHz
-1.5
-1.5
Reserved
Reserved
Reserved
200MHz
No spread
Reserved
Reserved
IDT® 2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
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Pin Descriptions
QFN Pin TSSOP
Pin
Name
Pin
Type
Pin Description
Number
Pin
Number
16
1
1
2
3
4
5
6
S0
S1
Input Select pin 0. See Table1. Internal pull-up resistor.
Input Select pin 1. See Table 1. Internal pull-up resistor.
2
SS0
X1/ICLK
X2
Input Spread Select pin 0. See Table 2. Internal pull-up resistor.
Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
Output Crystal connection. Leave unconnected for clock input.
3
4
5
OE
Input Output enable. Tri-states outputs and device is not shut down. Internal
pull-up resistor.
6
7
8
7
8
9
GNDXD
SS1
Power Connect to ground.
Input Spread Select pin 1. See Table 2. Internal pull-up resistor.
IREF
Output Precision resistor attached to this pin is connected to the internal current
reference.
9
10
11
12
13
14
15
16
CLK1
CLK1
Output HCSL complementary clock output 1.
Output HCSL true clock output 1.
10
11
12
13
14
15
VDDODA
GNDODA
CLK0
Power Connect to voltage supply +3.3 V for output driver and analog circuits
Power Connect to ground.
Output HCSL complementary clock output 0.
Output HCSL true clock output 0.
CLK0
VDDXD
Power Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.
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Applications Information
External Components
A minimum number of external components are required for
proper operation.
Output Structures
6*IREF
IREF
=2.3 mA
Decoupling Capacitors
Decoupling capacitors of 0.01F should be connected
between each VDD pin and the ground plane, as close to
the VDD pin as possible. Do not share ground vias between
components. Route power from power source through the
capacitor pad and then into ICS pin.
Crystal
See Output Termination
Sections - Pages 3 ~ 5
A 25 MHz fundamental mode parallel resonant crystal
should be used. This crystal must have less than 300 ppm
of error across temperature in order for the 5V41235 to meet
PCI Express specifications.
RR 475
General PCB Layout Recommendations
Crystal Capacitors
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Crystal capacitors are connected from pins X1 to ground
and X2 to ground to optimize the accuracy of the output
frequency.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
C = Crystal’s load capacitance in pF
L
Crystal Capacitors (pF) = (C - 7) * 2
L
2. No vias should be used between decoupling capacitor
and VDD pin.
For example, for a crystal with a 8pF load cap, each external
crystal cap would be 2pF [(8-7)*2=2].
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
Current Source (Iref) Reference Resistor - R
R
If board target trace impedance (Z) is 50, then R = 475
R
(1%), providing IREF of 2.32 mA. The output current (I ) is
equal to 6*IREF.
OH
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the 5V41235.This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Output Termination
The PCI-Express differential clock outputs of the 5V41235
are open source drivers and require an external series
resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the
PCI-Express Layout Guidelines section.
The 5V41235 can also be configured for LVDS compatible
voltage levels. See the LVDS Compatible Layout
Guidelines section.
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Layout Guidelines
SRC Reference Clock
Common Recommendations for Differential Routing
L1 length, route as non-coupled 50ohm trace
L2 length, route as non-coupled 50ohm trace
L3 length, route as non-coupled 50ohm trace
Dimension or Value
0.5 max
0.2 max
0.2 max
33
Unit Figure
inch
inch
inch
ohm
ohm
1
1
1
1
1
Rs
Rt
49.9
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
2 min to 16 max
1.8 min to 14.4 max
inch
inch
1
1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
0.25 to 14 max
0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
L2
L1
Rs
Rs
L4
L4'
L2'
L1'
Rt
Rt
HCSL Output Buffer
PCI Express
Down Device
REF_CLK Input
L3' L3
Figure 2: PCI Express Connector Routing
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
Rt
Rt
HCSL Output Buffer
PCI Express
Add-in Board
REF_CLK Input
L3' L3
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Alternative Termination for LVDS and other Common Differential Signals (figure 3)
Vdiff
0.45v
0.58
0.80
0.60
Vp-p
0.22v
0.28
0.40
0.3
Vcm
1.08
0.6
0.6
1.2
R1
33
33
33
33
R2
R3
R4
Note
150
78.7
78.7
174
100
137
none
140
100
100
100
100
ICS874003i-02 input compatible
Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Figure 3
L2
L1
R3
R4
R1a
R1b
L4
L4'
L2'
L1'
R2a
R2b
HCSL Output Buffer
Down Device
REF_CLK Input
L3'
L3
Cable Connected AC Coupled Application (figure 4)
Component
Value
Note
R5a, R5b
R6a, R6b
Cc
8.2K 5%
1K 5%
0.1 µF
Vcm
0.350 volts
Figure 4
3.3 Volts
R5a
R5b
Cc
L4
L4'
Cc
R6a
R6b
PCIe Device
REF_CLK Input
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Typical PCI-Express (HCSL) Waveform
700 mV
0
500 ps
500 ps
tOR
tOF
0.525 V
0.175 V
0.525 V
0.175 V
Typical LVDS Waveform
1325 mV
1000 mV
500 ps
500 ps
tOR
tOF
1250 mV
1150 mV
1250 mV
1150 mV
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 5V41235. These ratings are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product
reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDDXD, VDDODA
All Inputs and Outputs
Rating
4.6 V
-0.5 V to VDD+0.5 V
0 to +70C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
-40 to +85C
-65 to +150C
125C
Junction Temperature
Soldering Temperature
260C
ESD Protection (Input)
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±±%, Ambient Temperature -40 to +85C
Parameter
Symbol
Conditions
Min.
3.135
2.2
Typ.
3.3
Max.
3.465
Units
V
Supply Voltage
V
1
Input High Voltage
V
S0, S1, OE, ICLK, SS0, SS1
S0, S1, OE, ICLK, SS0, SS1
0 < Vin < VDD
VDD +0.3
V
IH
1
Input Low Voltage
V
VSS-0.3
-5
0.8
5
V
IL
2
Input Leakage Current
I
A
mA
mA
pF
pF
pF
nH
k
k
IL
Operating Supply Current
@100 MHz
I
R =33R =50, C =2 pF
63
42
85
50
7
DD
S
P
L
I
OE =Low
DDOE
Input Capacitance
Output Capacitance
X1, X2 Capacitance
Pin Inductance
C
Input pin capacitance
Output pin capacitance
IN
C
6
OUT
C
5
INX
PIN
L
5
Output Impedance
Pull-up Resistor
Z
CLK outputs
3.0
O
R
S0, S1, OE, SS0, SS1
100
PU
1. Single edge is monotonic when transitioning through region.
2. Inputs with pull-ups/-downs are not included.
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AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1
Unless stated otherwise, VDD=3.3 V ±±%, Ambient Temperature -40 to +85C
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ.
25
Max.
Units
MHz
MHz
MHz
mV
mV
mV
mV
ps
Output Frequency
HCSL termination
25
25
200
100
850
LVDS termination
HCSL
1,2
Output High Voltage
V
OH
1,2
Output Low Voltage
V
HCSL
-150
250
OL
1,2
Crossing Point Voltage
Crossing Point Voltage
Absolute
550
140
100
1,2,4
Variation over all edges
1,3
Jitter, Cycle-to-Cycle
Frequency Synthesis Error
Modulation Frequency
All outputs
0
ppm
kHz
ps
Spread spectrum
30
32.9
33
700
700
125
50
1,2
Rise Time
t
From 0.175 V to 0.525 V
From 0.525 V to 0.175 V
175
175
OR
1,2
Fall Time
t
ps
OF
1,2
Rise/Fall Time Variation
ps
Output to Output Skew
ps
1,3
Duty Cycle
45
7
55
%
5
Output Enable Time
All outputs
50
50
100
100
1.8
30
ns
5
Output Disable Time
All outputs
ns
Stabilization Time
t
From power-up VDD=3.3 V
ms
STABLE
Spread Spectrum Transition
Time
t
Stabilization time after spread
spectrum changes
ms
SPREAD
Note 1: Test setup is R =33R =50 with C =2 pF, Rr = 475 (1%).
S
P
L
Note 2: Measurement taken from a single-ended waveform.
Note 3: Measurement taken from a differential waveform.
Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.
Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.
Electrical Characteristics - Differential Phase Jitter Parameters
TA = Commercial and Industrial, Supply Voltage VDD = 3.3 V +/-5%
SPEC
Max
86
PARAMETER
Symbol
tjphaseG1
Conditions
PCIe Gen 1
Min
Typ
28
Units Notes
ps (p-p) 1,2,3
PCIe Gen 2
10kHz < f < 1.5MHz
PCIe Gen 2
ps
tjphaseG2Lo
tjphaseG2High
tjphaseG3
0.7
1.8
3
3.1
1
1,2,3
(RMS)
Jitter, Phase
ps
(RMS)
1,2,3
1.5MHz < f < Nyquist (50MHz)
ps
PCIe Gen 3
0.48
1,2,3
(RMS)
1Guaranteed by design and characterization, not 100% tested in production.
2See http://www.pcisig.com for complete specs
3Applies to 100MHz, spread off and 0.5% down spread only.
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Thermal Characteristics (16TSSOP)
Parameter
Thermal Resistance Junction to
Ambient
Symbol
Conditions
Min.
Min.
Typ. Max. Units
Still air
1 m/s air flow
3 m/s air flow
78
70
68
37
C/W
C/W
C/W
C/W
JA
JA
JA
JC
Thermal Resistance Junction to Case
Thermal Characteristics (16QFN)
Parameter
Symbol
Conditions
Typ. Max. Units
Thermal Resistance Junction to
Ambient
Still air
63.2
55.9
51.4
65.8
C/W
C/W
C/W
C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
IDT® 2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
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Marking Diagram (±V4123±PGG)
Marking Diagram (±V4123±PGGI)
16
16
9
9
IDT5V412
35PGG
YYWW$
IDT5V412
35PGGI
YYWW$
LOT
LOT
8
8
1
1
Notes:
1. Line 1 and 2: IDT part number.
2. Line 3: YYWW – Date code; $ – Assembly location.
3. “G” after the two-letter package code designates RoHS compliant package.
4. “I” at the end of part number indicates industrial temperature range.
5. Bottom marking: country of origin if not USA.
Marking Diagram (±V4123±NLGI)
Marking Diagram (±V4123±NLGI)
XXX
XXX
YWW$
235GI
YWW$
235G
Notes:
1. Line 1: Lot number.
2. Line 2: YWW – Date code; $ – Assembly location.
3. “G” designates RoHS compliant package.
4. “I” at the end of part number indicates industrial temperature range.
5. Bottom marking: country of origin if not USA.
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Ordering Information
Part / Order Number
5V41235PGG
Marking
See Page 10
Shipping Packaging
Tubes
Package
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin QFN
Temperature
0 to +70 C
5V41235PGG8
5V41235PGGI
5V41235PGGI8
5V41235NLG
Tape and Reel
Tubes
0 to +70 C
-40 to +85 C
-40 to +85 C
0 to +70 C
Tape and Reel
Tubes
See Page 10
5V41235NLG8
5V41235NLGI
Tape and Reel
Tubes
16-pin QFN
0 to +70 C
16-pin QFN
-40 to +85 C
-40 to +85 C
5V41235NLGI8
Tape and Reel
16-pin QFN
“G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
Revision History
Rev. Originator
Date
Description of Change
A
B
RDW
RDW
11/02/11 Initial release.
11/22/11 1. Changed title to “2 Output PCIe GEN1/2/3 Synthesizer”
2. Updated Differential Phase Jitter table.
C
RDW
06/06/12 1. Updated Features bullet(s) from: “• 25 MHz, 125 MHz and 200 MHz output frequencies; supports
Ethernet applications”, to: “• 25 MHz, 100MHz, 125 MHz and 200 MHz output frequencies;
TSSOP-only
• 100MHz output frequency; MLF package”.
2. Added table 3, Output/Spread Select table for MLF only
D
E
S. Sharma
IH
10/16/12 1. Updated and expanded Output Select table per char review.
2. Changed crystal capacitance load spec from 16pF to 8pF.
09/09/15 Corrected typo in Ordering information; NLG and NLGI shipping packaging changed from “Tray” to
“Tubes”.
F
IH
07/08/16 Updated marking diagrams for TSSOP devices.
G
RDW
10/11/16 1. Updated Features bullets for package output frequencies.
2. Changed all MLF references to QFN.
H
J
B.Shen
C.P.
01/12/17 Updated 16QFN POD drawing to latest showing chamfered epad.
05/05/17 Updated PGG16 package outline drawing to latest version.
IDT® 2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
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