5T9820NLI8 [IDT]
Clock Driver, PQCC68;
| 型号： | 5T9820NLI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver, PQCC68 |
| 文件： | 总36页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT5T9820
EEPROM PROGRAMMABLE
2.5V ZERO DELAY PLL
CLOCK DRIVER
FEATURES:
DESCRIPTION:
• 2.5VDD
The IDT5T9820 is a 2.5V PLL clock driver intended for high perfor-
mancecomputinganddata-communicationsapplications. TheIDT5T9820
hastenoutputsinfivebanksoftwo, plusadedicateddifferentialfeedback.
The redundant input capability allows for a smooth change over to a
secondary clock source when the primary clock source is absent.
TheclockdrivercanbeconfiguredthroughtheuseofJTAG/I2Cprogram-
ming. An internal EEPROM will allow the user to save and restore the
configurationofthedevice.
• 5 pairs of outputs
• Low skew: 100ps all outputs at same interface level, 250ps all
outputs at different interface levels
• Selectable positive or negative edge synchronization
• Tolerant of spread spectrum input clock
• Synchronous output enable
• Selectable inputs
• Input frequency: 4.17MHz to 250MHz
• Output frequency: 12.5MHz to 250MHz
• Internal non-volatile EEPROM
The feedback bank allows divide-by-functionality from 1 to 12 through
theuseofJTAGorI2Cprogramming. Thisprovidestheuserwithfrequency
multiplication1to12withoutusingdividedoutputsforfeedback. Eachoutput
bank also allows for a divide-by functionality of 2 or 4.
• JTAG or I2C bus serial interface for programming
• Hot insertable and over-voltage tolerant inputs
• Feedback divide selection with multiply ratios of (1-6, 8, 10, 12)
• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
interface
The IDT5T9820 features a user-selectable, single-ended or differential
inputtotensingle-endedoutputs. Theclockdriveralsoactsasatranslatorfrom
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended
1.8V/2.5VLVTTLinputtoHSTL,eHSTL,or1.8V/2.5VLVTTLoutputs. Each
output bank can be individually configured to be either HSTL, eHSTL, 2.5V
LVTTL,or1.8VLVTTL,includingthefeedbackbank. Also,eachclockinput
can be individually configured to accept 2.5V LVTTL, 1.8V LVTTL, or
differentialsignals. Theoutputscanbesynchronouslyenabled/disabled.
Furthermore, alltheoutputscanbesynchronizedwiththepositiveedge
of the REF clock input or the negative edge of REF.
• Selectable HSTL, eHSTL, or 1.8V/2.5V LVTTL output interface for
each output bank
• Selectable differential or single-ended inputs and ten single-
ended outputs
• PLL bypass for DC testing
• External differential feedback, internal loop filter
• Low Jitter: <75ps cycle-to-cycle, all outputs at same interface
level: <100ps cycle-to-cycle all outputs at different interface
levels
• Power-down mode
• Lock indicator
• Available in VFQFPN package
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
NOVEMBER 2004
1
c
2004 Integrated Device Technology, Inc.
DSC - 6503/21
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
FUNCTIONALBLOCKDIAGRAM
(TDO)
TDO/ADDR1
(ADDR1)
TMS/ADDR0
TCLK/SCLK
TDI/SDA
JTAG/I2C
PROGRAMMING
SELECTION
AND CONTROL
LOGIC
1sOE
VDDQ1
TRST/SEL
1Q0
Divide
Select
1Q1
2sOE
EEPROM
VDDQ2
2Q0
Divide
Select
2Q1
PD
3sOE
OMODE
VDDQ3
FB
3Q0
/N
Divide
Select
FB/VREF2
0
1
PLL
3Q1
REF0
0
1
REF0/VREF0
4sOE
VDDQ4
REF1
4Q0
REF1/VREF1
Divide
Select
4Q1
5sOE
VDDQ5
REF_SEL
PLL_EN
5Q0
Divide
Select
5Q1
LOCK(φ)
VDDQFB
QFB
Divide
Select
QFB
2
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
PINCONFIGURATION
TRST/SEL
OMODE
VDD
TDI/SDA
TCLK/SCLK
VDD
51
50
49
48
47
46
1
2
3sOE
3
VDDQ3
4
VDDQ3
REF_SEL
REF1
5
3Q0
6
45
3Q1
VDD
VDD
REF1/VREF1
REF0
7
44
43
42
8
REF0/VREF0
GND
9
FB
10
11
12
13
14
15
16
17
VDD
VDD
4Q1
FB/VREF2
41
40
39
VDD
VDD
4Q0
38
VDDQ4
NC
NC
NC
37
36
35
VDDQ4
4sOE
VDD
NC
VFQFPN
TOP VIEW
3
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Symbol
Description
Max
–0.5 to +3.6
–0.5 to +3.6
–0.5 to VDDQ +0.5
–0.5 to +3.6
150
Unit
V
Parameter Description
Min.
2.5
—
Typ.
3
Max.
3.5
7
Unit
pF
VDDQN, VDD Power Supply Voltage(2)
CIN
InputCapacitance
OutputCapacitance
VI
Input Voltage
V
COUT
6.3
pF
VO
Output Voltage
V
NOTE:
1. Capacitance applies to all inputs except JTAG/I2C signals, SEL, ADDR0, and ADDR1.
VREF
TJ
Reference Voltage(3)
Junction Temperature
Storage Temperature
V
°C
°C
TSTG
–65 to +165
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VDDQN and VDD internally operate independently. No power sequencing requirements
need to be met.
3. Not to exceed 3.6V.
RECOMMENDEDOPERATINGRANGE
Symbol
Description
Min.
–40
2.3
Typ.
+25
2.5
Max.
+85
2.7
Unit
°C
V
TA
AmbientOperatingTemperature
InternalPowerSupplyVoltage
(1)
VDD
HSTL Output Power Supply Voltage
Extended HSTL and 1.8V LVTTL Output Power Supply Voltage
1.4
1.65
1.5
1.8
1.6
1.95
V
V
(1)
VDDQN
2.5VLVTTLOutputPowerSupplyVoltage
TerminationVoltage
VDD
V
V
VT
VDDQN / 2
NOTE:
1. All power supplies should operate in tandem. If VDD or VDDQN is at maximum, then VDDQN or VDD (respectively) should be at maximum, and vice-versa.
PINDESCRIPTION
Symbol
I/O
Type
Description
REF[1:0]
I
I
Adjustable(1) Clockinput. REF[1:0] isthe"true"sideofthedifferentialclockinput. Ifoperatinginsingle-endedmode, REF[1:0] istheclockinput.
Adjustable(1)
REF[1:0]/
VREF[1:0]
Complementaryclockinput. REF[1:0]/VREF[1:0] isthe"complementary"sideofREF[1:0] iftheinputisindifferentialmode. Ifoperating
insingle-endedmode,REF[1:0]/VREF[1:0] isleftfloating. Forsingle-endedoperationindifferentialmode,REF[1:0]/VREF[1:0]shouldbeset
tothedesiredtogglevoltageforREF[1:0]:
2.5VLVTTL
1.8VLVTTL,eHSTL
HSTL
VREF =1250mV(SSTL2compatible)
VREF = 900mV
VREF = 750mV
LVEPECL
VREF = 1082mV
FB
I
I
Adjustable(1) Clockinput. FBisthe"true"sideofthedifferentialfeedbackclockinput. Ifoperatinginsingle-endedmode,FBisthefeedbackclockinput.
FB/VREF2
Adjustable(1) Complementaryfeedbackclockinput. FB/VREF2isthe"complementary"sideofFBiftheinputisindifferentialmode. Ifoperatinginsingle-
endedmode,FB/VREF2isleftfloating. Forsingle-endedoperationindifferentialmode, FB/VREF2shouldbesettothedesiredtogglevoltage
for FB:
2.5VLVTTL
1.8VLVTTL,eHSTL
HSTL
VREF =1250mV(SSTL2compatible)
VREF = 900mV
VREF = 750mV
LVEPECL
VREF = 1082mV
NOTE:
1. Inputs are capable of translating the following interface standards. User can select between:
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
4
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
PINDESCRIPTION,CONTINUED
Symbol
REF_SEL
nsOE
I/O
Type
LVTTL(1)
LVTTL(1)
Description
I
I
Reference clock select. When LOW, selects REF0 and REF0/VREF0. When HIGH, selects REF1 and REF1/VREF1.
Synchronousoutputenable/disable. Eachoutputs'senable/disablestatecanbecontrolledeitherwiththensOEpinorthroughJTAG
or I2C programming, corresponding bits 52 - 56. When the nsOE is HIGH or the corresponding Bit (52 - 56) is 1, the output will be
synchronouslydisabled.WhenthensOEisLOWandthecorrespondingBit(52-56)is0,theoutputwillbeenabled. (SeeJTAG/I2C
SerialConfigurationtable.)
QFB
QFB
O
O
O
I
Adjustable(2) Feedbackclockoutput
Adjustable(2) Complementaryfeedbackclockoutput
Adjustable(2) Fivebanksoftwooutputs
nQ[1:0]
PLL_EN
LVTTL(1)
PLL enable/disable control. The PLL's enable/disable state can be controlled either with the PLL_EN pin or through JTAG or I2C
programming,correspondingBit57. WhenPLL_ENisHIGHorthecorrespondingBit57is1,thePLLisdisabledandREF[1:0] goes
to all outputs. When PLL_EN is LOW and the corresponding Bit 57 is 0, the PLL will be active.
PD
I
LVTTL(1)
Power down control. When PD is LOW, the inputs are disabled and internal switching is stopped. The OMODE pin in conjunction
withthecorrespondingBit59selectswhethertheoutputsaregatedLOW/HIGHortri-stated. WhenOMODEisHIGHorBit59is1,
Bit58determinesthelevelatwhichtheoutputsstop. WhenBit58is0/1,thenQ[1:0] andQFBarestoppedinaHIGH/LOWstate,while
theQFBisstoppedinaLOW/HIGHstate. WhenOMODEisLOWandBit59is0,theoutputsaretri-stated. SetPDHIGHfornormal
operation. (SeeJTAG/I2CSerialConfigurationtable.)
LOCK
O
I
LVTTL
PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to
theinputs. Theoutputwillbe2.5VLVTTL. (FormoreinformationonapplicationspecificuseoftheLOCKpin, pleaseseeAN237.)
OMODE
LVTTL(1)
Outputdisablecontrol. UsedinconjunctionwithnsOEandPD. Theoutputs'disablestatecanbecontrolledeitherwiththeOMODE
pinorthroughJTAGorI2Cprogramming,correspondingBit59.WhenOMODEisHIGHorthecorrespondingBit59is1,theoutputs'
disable state will be gated and Bit 58 will determine the level at which the outputs stop. When Bit 58 is 0/1, the nQ[1:0] andQFBare
stopped in a HIGH/LOW state, while the QFB is stopped in a LOW/HIGH state. When OMODE is LOW and its corresponding bit
59is0,theoutputsdisablestatewillbethetri-state.(SeeJTAG/I2CSerialConfigurationtable.)
TRST/SEL
I/I
LVTTL/
TRST- Active LOW input to asynchronously reset the JTAG boundary-scan circuit.
LVTTL(4,5) SEL-Selectprogramminginterfacecontrolforthedual-functionpins. WhenHIGH,thedual-functionpinsaresetforJTAGprogramming.
WhenLOW,thedual-functionpinsaresetforI2CprogrammingandtheJTAGinterfaceisasynchronouslyplacedintheTestLogicReset
state.
TDO/ADDR1 O/I
TMS/ADDR0 I/I
LVTTL/
TDO-Serialdataoutputpinforinstructionsaswellastestandprogrammingdata. DataisshiftedinonthefallingedgeofTCLK. The
pinistri-statedifdataisnotbeingshiftedoutofthedevice.
ADDR1-UsedtodefineauniqueI2Caddressforthisdevice. OnlyforI2Cprogramming. (SeeJTAG/I2CSerialInterfaceDescription.)
3-Level(3,4,5)
LVTTL/
TMS-InputpinthatprovidesthecontrolsignaltodeterminethetransitionsoftheJTAGTAPcontrollerstatemachine. Transitionswithin
thestatemachineoccurattherisingedgeofTCLK. Therefore,TMSmustbesetupbeforetherisingedgeofTCLK. TMSisevaluated
ontherisingedgeTCLK.
3-Level(3,4,5)
ADDR0-UsedtodefineauniqueI2Caddressforthisdevice. OnlyforI2Cprogramming. (SeeJTAG/I2CSerialInterfaceDescription.)
TCLK/SCLK I/I
LVTTL/
TCLK - The clock input to the JTAG BST circuitry
LVTTL(4,5) SCLK - Serial clock for I2C programming
TDI/SDA
I/I
LVTTL/
TDI-Serialinputpinforinstructionsaswellastestandprogrammingdata. DataisshiftedinontherisingedgeofTCLK.
LVTTL(4,5) SDA - Serial data for I2C programming. (See JTAG/I2C Serial Description table.)
VDDQN
PWR
Power supply for each pair of outputs. When using 2.5V LVTTL, 1.8V LVTTL, HSTL, or eHSTL outputs, VDDQN should be set to its
correspondingoutputs(seeFrontBlockDiagram). Whenusing2.5VLVTTLoutputs,VDDQNshouldbeconnectedtoVDD.
VDD
PWR
PWR
Powersupplyforphaselockedloop,lockoutput,inputs,andotherinternalcircuitry
Ground
GND
NOTES:
1. Pins listed as LVTTL inputs can be configured to accept 1.8V or 2.5V signals through the use of the I2C/JTAG programming, bit 61. (See JTAG/I2C Serial Description.)
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQN voltage.
3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
4. The JTAG (TDO, TMS, TCLK, and TDI) and I2C (ADDR1, ADDR0, SCLK, and SDA) signals share the same pins (dual-function pins) for which the TRST/SEL pin will select between
the two programming interfaces.
5. JTAG and I2C pins accept 2.5V signals. The JTAG input pins (TMS, TCLK, TDI, TRST) will also accept 1.8V signals.
5
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
JTAG/ I2C SERIAL DESCRIPTION
Bit
Description
95:62 Reserved Bits. Set bits 95:62 to '0'.
61
Input Interface Selection for control pins (REF_SEL, PD, PLL_EN, OMODE, nsOE ). When bit 61 is ‘1’, the control pins are 2.5V LVTTL. When bit 61 is ‘0’,
thecontrolpinsare1.8VLVTTL.
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NOTE:
VCO Frequency Range. When ‘0’, range is 50MHz-125MHz. When ‘1’, range is 100MHz-250MHz.
Output’sDisableState. SeecorrespondingexternalpinOMODEinPinDescriptiontable.
Positive/NegativeEdgeControl. When‘0’/’1’, theoutputsaresynchronizedwiththenegative/positiveedgeofthereferenceclock.
PLL Enable/Disable. SeecorrespondingexternalpinPLL_ENinPinDescriptiontable.(1)
OutputEnable/Disablefor1Q[1:0] outputs. Seecorrespondingexternalpin1sOEinPinDescriptiontable.
OutputEnable/Disablefor2Q[1:0] outputs. Seecorrespondingexternalpin2sOEinPinDescriptiontable.
OutputEnable/Disablefor3Q[1:0] outputs. Seecorrespondingexternalpin3sOEinPinDescriptiontable.
OutputEnable/Disablefor4Q[1:0] outputs. Seecorrespondingexternalpin4sOEinPinDescriptiontable.
OutputEnable/Disablefor5Q[1:0] outputs. Seecorrespondingexternalpin5sOEinPinDescriptiontable.
FB Divide-by-N selection
FB Divide-by-N selection
FB Divide-by-N selection
FB Divide-by-N selection
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 1
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 1
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 2
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 2
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 3
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 3
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 4
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 4
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 5
Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 5
FB output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on FB bank
FB output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on FB bank
REF0Inputinterfaceselectionfor2.5VLVTTL,1.8VLVTTL,orDifferential
REF0Inputinterfaceselectionfor2.5VLVTTL,1.8VLVTTL,orDifferential
REF1inputinterfaceselectionfor2.5VLVTTL,1.8VLVTTL,orDifferential
REF1inputinterfaceselectionfor2.5VLVTTL,1.8VLVTTL,orDifferential
FBinputinterfaceselectionfor2.5VLVTTL,1.8VLVTTL,orDifferential
FBinputinterfaceselectionfor2.5VLVTTL,1.8VLVTTL,orDifferential
Divideselectionforbank1
Divideselectionforbank1
Divideselectionforbank1
Divideselectionforbank1
Divideselectionforbank1
Divideselectionforbank2
Divideselectionforbank2
Divideselectionforbank2
Divideselectionforbank2
1. Only for EEPROM operation; bit 57 must be set to 0 to enable the PLL for proper EEPROM operation. The EEPROM access times are based on the VCO frequency of the PLL
(refer to the EEPROM Operation section).
6
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
JTAG/ I2C SERIAL DESCRIPTION, CONT.
Bit
20
19
18
17
16
15
14
13
12
11
10
9
Description
Divideselectionforbank2
Divideselectionforbank3
Divideselectionforbank3
Divideselectionforbank3
Divideselectionforbank3
Divideselectionforbank3
Divideselectionforbank4
Divideselectionforbank4
Divideselectionforbank4
Divideselectionforbank4
Divideselectionforbank4
Divideselectionforbank5
Divideselectionforbank5
Divideselectionforbank5
Divideselectionforbank5
Divideselectionforbank5
Divide selection for FB bank
Divide selection for FB bank
Divide selection for FB bank
Divide selection for FB bank
Divide selection for FB bank
8
7
6
5
4
3
2
1
0
JTAG/ I2C SERIAL CONFIGURATIONS:
POWERDOWN
JTAG/ I2C SERIAL CONFIGURATIONS:
OUTPUTENABLE/DISABLE
PD
H
Bit 59 (OMODE)
X(X)
Output
NormalOperation
Tri-Sate
Bit 59 (OMODE)
X(X)
Bit 56-52 (nsOE)
0 and (L)
Output
NormalOperation
Tri-Sate
L
0 and (L)
1 or (H)
0 and (L)
1 or (H)
1 or (H)
L
Gated(1)
1 or (H)
Gated(1)
NOTE:
NOTE:
1. OMODE and its corresponding Bit 59 selects whether the outputs are gated LOW/
HIGH or tri-stated. When OMODE is HIGH or the corresponding Bit 59 is 1, the outputs'
disable state will be gated. Bit 58 determines the level at which the outputs stop.
When Bit 58 is 0/ 1, the nQ[1:0] and QFB are stopped in a HIGH/LOW state, while the
QFB is stopped in a LOW/HIGH state. When OMODE is LOW and its corresponding
Bit 59 is 0, the outputs' disable state will be the tri-state.
1. OMODE and its corresponding Bit 59 selects whether the outputs are gated LOW/
HIGH or tri-stated. When OMODE is HIGH or the corresponding Bit 59 is 1, the outputs'
disable state will be gated. Bit 58 determines the level at which the outputs stop.
When Bit 58 is 0/ 1, the nQ[1:0] and QFB are stopped in a HIGH/LOW state, while the
QFB is stopped in a LOW/HIGH state. When OMODE is LOW and its corresponding
Bit 59 is 0, the outputs' disable state will be the tri-state.
JTAG/ I2C SERIAL CONFIGURATIONS:
OUTPUTDRIVESTRENGTH
SELECTION(1)
JTAG/ I2C SERIAL CONFIGURATIONS:
CLOCKINPUTINTERFACESELEC-
TION(1)
Bit 37, 39, 41,
Bit 36, 38, 40,
Bit 31, 33, 35
Bit 30, 32, 34
Interface
Differential(2)
2.5VLVTTL
1.8VLVTTL
43, 45, 47
42, 44, 46
Interface
2.5VLVTTL
1.8VLVTTL
HSTL/eHSTL
0
0
1
0
1
1
0
0
1
0
1
0
NOTES:
1. All other states that are undefined in the table will be reserved.
2. Differential input interface for HSTL/eHSTL, LVEPECL (2.5V), and 2.5V/1.8V LVTTL.
NOTE:
1. All other states that are undefined in the table will be reserved.
7
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
JTAG/ I2C SERIAL CONFIGURATIONS: SKEW OR FREQUENCY SELECT(1)
Bit 4, 9, 14,
19, 24, 29
Bit 3, 8, 13,
18, 23, 28
Bit 2, 7, 12,
17, 22, 27
Bit 1, 6, 11,
16, 21, 26
Bit 0, 5, 10,
15, 20, 25
Output Skew
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
Zero Skew
Inverted
Divide-by-2
Divide-by-4
NOTE:
1. All other states that are undefined in the table will result in zero skew.
JTAG/ I2C SERIAL CONFIGURATIONS: FB DIVIDE-BY-N(1)
Bit51
Bit50
Bit49
Bit48
Divide-by-N
Permitted Output Divide-by-N connected to FB and FB/VREF2 (2)
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
2
1, 2, 4
1, 2
1
3
4
1, 2
1, 2
1, 2
1
5
6
8
10
12
1
1
NOTES:
1. All other states that are undefined in the table will be reserved.
2. Permissible output division ratios connected to FB and FB/VREF2. The frequencies of the REF[1:0] and REF [1:0]/VREF[1:0] inputs will be Fvco/N when the parts are
configured for frequency multiplication by using an undivided output for FB and FB/VREF2 and setting N (N = 1-6, 8, 10, 12).
INPUT/OUTPUTSELECTION(1)
EXTERNALDIFFERENTIALFEEDBACK
Input
Output(2)
By providing a dedicated external differential feedback, the IDT5T9820
gives users flexibility with regard to divide selection. The FB and FB/
VREF2 signals are compared with the input REF[1:0] and REF[1:0]/VREF[1:0]
signals at the phase detector in order to drive the VCO. Phase differ-
ences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
2.5VLVTTL,
1.8VLVTTL,
HSTL,
eHSTL
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
MASTERRESETFUNCTIONALITY
HSTL DIF
NOTES:
The IDT5T9820 performs a reset of the internal output divide circuitry
when all five output banks are disabled by toggling the nSOE pins
HIGH. When one or more banks of outputs are enabled by toggling the
nSOE LOW (if the corresponding nSOE programming bits are also set
LOW), the divide circuitry starts again from a known state. In the case
that the FB output is selected for divide-by-2 or divide-by-4, the FB
output will stop toggling while all five nSOE pins and bits are LOW, and
loss of lock will occur.
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations
of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require
the REF[1:0] /VREF[1:0] and FB/VREF2 pins to be left floating. Differential Single-Ended
(DSE) is for single-ended operation in differential mode, requiring VREF[1:0] and VREF2.
Differential (DIF) inputs are used only in differential mode.
2. For each output bank.
8
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
I2C BUS OPERATION
JTAG/ I2C SERIAL CONFIGURATIONS:
VCOFREQUENCYSELECT
TheIDT5T9820I2CinterfacesupportsStandard-Mode(100kHz)andFast-
Mode(400kHz)datatransferrates. Dataistransferredinbytesinsequential
orderfromthelowesttohighestbyte. AftergeneratingaSTARTcondition,the
bus master broadcasts a 7-bit slave address followed by a read/write bit.
Bit60
Min.
Max.
0
1
50Mhz
100MHz
125MHz
250Mhz
I2CADDRESS
A7
A6
A5
A4
A3
A2
A1
I2CSERIALINTERFACECONTROL
The I2C interface permits the configuration of the IDT5T9820. The
IDT5T9820isaread/writeslavedevicemeetingPhilipsI2Cbusspecifications.
The I2C bus is controlled by a master device that generates the serial clock
SCLK,controlsbusaccess,andgeneratestheSTARTandSTOPconditions
while the device works as a slave. Both master and slave can operate as a
transmitter and receiver but the master device determines which mode is
activated.
1
1
0
1
X
X
X
AddressA0istheread/writebitandissetto‘0’forwritesand‘1’forreads.
The ADDR0 and ADDR1 tri-level pins allow the last three bits of the 7-bit
address to be defined by the user.
ADDR1
LOW
LOW
LOW
MID
ADDR0
LOW
MID
A3
0
A2
0
A1
0
0
0
1
HIGH
LOW
MID
0
1
0
BUS CONDITIONS
0
1
1
Data transfer on the bus can only be initiated when the bus is not busy.
During data transfer, the data line (SDA) must remain stable whenever the
clockline(SCLK)ishigh. Changesinthedatalinewhiletheclocklineishigh
willbeinterpretedbythedeviceasaSTARTorSTOPcondition. Thefollowing
busconditionsaredefinedbytheI2Cbusprotocolandareillustratedinfigure
1.
MID
1
0
0
MID
HIGH
LOW
MID
1
0
1
HIGH
HIGH
HIGH
1
1
0
1
1
1
HIGH
1
1
0
NOT BUSY
WRITE OPERATION
Boththedata(SDA)andclock(SCLK)linesremainhightoindicatethebus
is not busy.
(see I2C Interface Definition for ProgWrite)
Toinitiateawriteoperation(ProgWrite),theread/writebitissetto‘0’. During
thewriteoperation,thefirsttwobytestransferredmustbetheDeviceAddress
followedbytheCommandCode. Theinternalprogrammingregistersofthe
deviceignorethesefirsttwobytes. ThesubsequentbytesaretheDataBytes,
whichtotaltwelve. AlltwelveDataBytesmustbewrittenintothedeviceduring
the write operation in order for the internal programming registers to be
updated. If a STOP condition is generated before the 12th Data Byte, the
internalprogrammingregisterswillremainunchangedtopreventaninvalid
PLLconfiguration. AnAcknowledgebythedevicebetweeneachbytemust
occurbeforethenextbyteissent. Afterthetransferofthe12th DataByte,an
Acknowledgesignalwillbesenttothebusmasterafterwhichitwillgenerate
a STOP condition. Once the STOP condition has occurred, the internal
programmingregistersofthedevicewillbeupdated.
STARTDATATRANSFER
AhightolowtransitionoftheSDAlinewhiletheSCLKinputishighindicates
aSTARTcondition. AllcommandstothedevicemustbeprecededbyaSTART
condition.
STOPDATATRANSFER
AlowtohightransitionoftheSDAlinewhileSCLKisheldhighindicatesa
STOP condition. All commands to the device must be followed by a STOP
condition.
DATAVALID
ThestateoftheSDAlinerepresentsvaliddataiftheSDAlineisstablefor
thedurationofthehighperiodoftheSCLKlineafteraSTARTconditionoccurs.
ThedataontheSDAlinemustbechangedonlyduringthelowperiodofthe
SCLKsignal. Thereisoneclockpulseperdatabit. Eachdatatransferisinitiated
by a START condition and terminated with a STOP condition.
READOPERATION
(see I2C Interface Definition for ProgRead)
Toinitiateareadoperation(ProgRead),theread/writebitissetto‘1’. During
thereadoperation,therewillbeatotaloffourteendatabytesreturnedfollowing
an Acknowledge of the device address. The first two data bytes are the ID
ByteandaReservedByte,inthatorder. Thesubsequentbytesarethesame
twelveDataBytesthatwerewrittenduringthewriteoperation. Thereadback
ACKNOWLEDGE
When addressed, the receiving device is required to generate an
Acknowledgeaftereachbyteisreceived. Themasterdevicemustgenerate
anextraclockpulsetocoincidewiththeAcknowledgebit. Theacknowledging
device must pull the SDA line low during the high period of the master
acknowledgeclockpulse. Setupandholdtimesmustbetakenintoaccount.
can be terminated at any time by issuing a STOP condition.
I2C ID BYTE
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0
0
0
0
0
1
0
0
9
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
EEPROMOPERATION
(see I2C Interface Definition for the EEPROM instructions)
TheIDT5T9820canalsostoreitsconfigurationininternalEEPROM. Thecontentsofthedevice’sinternalprogrammingregisterscanbesavedtotheEEPROM
by issuing a save instruction (ProgSave) and can be loaded back to the internal programming registers by issuing a restore instruction (ProgRestore). To
initiateasaveorrestore,onlytwobytesaretransferred. TheDeviceAddressisissuedwiththeread/writebitsetto‘0’followedbytheappropriateCommand
Code. ThesaveorrestoreinstructionexecutesaftertheSTOPconditionisreceived,duringwhichtimetheIDT5T9820willnotgenerateAcknowledgebits.
ThedeviceisreadytoacceptanewprogramminginstructiononceitAcknowledgesits7-bitaddress. Thetimeittakesforthesaveandrestoreinstructions
to complete depends on the PLL oscillator frequency, FVCO. The restore time, TRESTORE, and the save time, TSAVE, can be calculated as follows:
TRESTORE = 1.23X106/FVCO
(mS)
6
TSAVE
FVCO + 52
(mS)
= 3.09X10 /
Inorderforthesaveandrestoreinstructionstofunctionproperly,theIDT5T9820mustnotbeinpower-downmode(PDmustbeHIGH),andthePLLmust
be enabled (PLL_EN must be LOW and Bit 57 = 0).
Onpower-upoftheIDT5T9820,anautomaticrestoreisperformedtoloadtheEEPROMcontentsintotheinternalprogrammingregisters. Theauto-restore
will not function properly if the device is in power-down mode (PDmust be HIGH). The device’s auto-restore feature will function regardless of the state of
the PLL_EN pin or Bit 57. The IDT5T9820 will be ready to accept a programming instruction once it acknowledges its 7-bit I2C address. The time it takes
forthedevicetocompletetheauto-restoreisapproximately3ms.
PROGRAMMINGNOTES
OncetheIDT5T9820hasbeenprogrammedeitherwithaProgWriteorProgRestoreinstruction,thedevicewillattempttoachievephaselockusingthenew
PLLconfiguration. IfthereisavalidREFandFBinputclockconnectedtothedeviceanditdoesnotachievelock,theusershouldissueaProgReadinstruction
toconfirmthatthePLLconfigurationdataisvalid.
Onpower-upandbeforetheautomaticProgRestoreinstructionhascompleted,theinternalprogrammingregisterswillcontainthevalueof‘0’forallbits95:0.
ThePLLwillremainattheminimumfrequencyandwillnotachievephaselockuntilaftertheautomaticrestoreiscompleted. Iftheoutputsareenabledbythe
nSOEpins,theoutputswilltoggleattheminimumfrequency. IftheoutputsaredisabledbythenSOEpinsandtheOMODEpinissetHIGH,thenQ[1:0]and
QFB are stopped HIGH, while QFB is stopped LOW.
SCLK
tSU:START
tHD:START
tSU:STOP
SDA
Address or data
valid
Data can
change
START
STOP
tR
tF
tHIGH
tLOW
SCLK
tHD:START
tHD:DATA
tSU:DATA
tSU:START
tSU:STOP
SDA IN
tBUF
tOVD
tOVD
SDA OUT
Figure 1: I2C Timing Data
10
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
I2CINTERFACEDEFINITION
Device Address
Command Code
8'bxxxxxx00
Data
W
0
ProgWrite
S
7'b1101xxx
A
A
Data Byte 1 (Bits 95 - 88) A . . .
Data Byte 2
Data Byte 3
A
A
A
A
A
A
A
A
A
A
A
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
P
M
S
B
L
S
B
M
S
B
L
S
B
Data Byte 4
Data Byte 5
Data Byte 6
ID Byte:
ID
00000100
Data Byte 7
Part #
5T9820
Data Byte 8
Data Byte 9
Data Byte 10
Data Byte 11
Data Byte 12 (Bits 7 - 0)
Device Address
7'b1101xxx
R
1
ID Byte
A
ProgRead
S
8'b00000100
A
A
. . .
. . .
Reserved Byte
Data Byte 1 (Bits 95 - 88) A . . .
Data Byte 2
Data Byte 3
A
A
A
A
A
A
A
A
A
A
A
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
P
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Data Byte 8
Data Byte 9
Data Byte 10
Data Byte 11
Data Byte 12 (Bits 7 - 0)
Device Address
7'b1101xxx
W
0
Command Code
8'bxxxxxx01
ProgSave
S
S
A
A
A
P
Device Address
7'b1101xxx
W
0
Command Code
8'bxxxxxx10
ProgRestore
A
P
11
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
I2C BUS DC CHARACTERISTICS
Symbol
VIH
Parameter
Conditions
Min
Typ
Max
Unit
V
Input HIGH Level
InputLOWLevel
Hysteresis of Inputs
InputLeakageCurrent
OutputLOWVoltage
0.7 * VDD
VIL
0.3 * VDD
V
VHYS
IIN
0.05 * VDD
V
±1.0
0.4
µA
V
VOL
IOL = 3 mA
I2C BUS AC CHARACTERISTICS FOR STANDARD MODE
Symbol
FSCLK
tBUF
Parameter
Min
0
Typ
Max
Unit
KHz
µs
µs
µs
ns
Serial Clock Frequency (SCLK)
Bus free time between STOP and START
SetupTime,START
100
4.7
4.7
4
tSU:START
tHD:START
tSU:DATA
tHD:DATA
tOVD
HoldTime, START
SetupTime, datainput(SDA)
Hold Time, data input (SDA)(1)
Outputdatavalidfromclock
Capacitive Load for Each Bus Line
Rise Time, data and clock (SDA, SCLK)
Fall Time, data and clock (SDA, SCLK)
HIGH Time, clock (SCLK)
LOW Time, clock (SCLK)
SetupTime, STOP
250
0
µs
µs
pF
3.45
400
CB
tR
1000
300
ns
tF
ns
tHIGH
4
4.7
4
µs
µs
µs
tLOW
tSU:STOP
NOTE:
1. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge of
SCLK.
I2C BUS AC CHARACTERISTICS FOR FAST MODE
Symbol
FSCLK
tBUF
Parameter
Min
0
Typ
Max
Unit
KHz
µs
µs
µs
ns
Serial Clock Frequency (SCLK)
Bus free time between STOP and START
SetupTime,START
400
1.3
0.6
0.6
100
0
tSU:START
tHD:START
tSU:DATA
tHD:DATA
tOVD
HoldTime, START
SetupTime, datainput(SDA)
Hold Time, data input (SDA)(1)
Outputdatavalidfromclock
Capacitive Load for Each Bus Line
Rise Time, data and clock (SDA, SCLK)
Fall Time, data and clock (SDA, SCLK)
HIGH Time, clock (SCLK)
LOW Time, clock (SCLK)
SetupTime, STOP
µs
µs
pF
0.9
400
300
300
CB
tR
20 + 0.1 * CB
ns
tF
20 + 0.1 * CB
ns
tHIGH
0.6
1.3
0.6
µs
µs
µs
tLOW
tSU:STOP
NOTE:
1. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge of
SCLK.
12
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
JTAGINTERFACE
TheStandardJTAGinterfaceconsistsoffourbasicelements:
• Test Access Port (TAP)
• TAP controller
• Instruction Register (IR)
Five additional pins (TDI, TDO, TMS, TCLK and TRST) are provided to
supporttheJTAGboundaryscaninterface.TheIDT5T9820 incorporatesthe
necessarytapcontrollerandmodifiedpadcellstoimplementtheJTAGfacility.
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
• Data Register Port (DR)
The following sections provide a brief description of each element. For a
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
MUX
Device ID Reg.
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
TAP
TMS
clkDR, ShiftDR
TAP
Controller
UpdateDR
TCLK
TRST
Instruction Decode
clkLR, ShiftLR
UpdateLR
Instruction Register
Control Signals
Boundary Scan Architecture
TEST ACCESS PORT (TAP)
THETAPCONTROLLER
The Tap interface is a general-purpose port that provides access to the
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
internaloftheprocessor.Itconsistsoffourinputports(TCLK,TMS,TDI,TRST) TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
and one output port (TDO). and Data Registers for capture and update of data.
13
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
1
Test-Logic
Reset
0
1
0
1
1
Run-Test/
Idle
Select-
DR-Scan
Select-
IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
0
0
Shift-DR
Shift-IR
1
1
1
1
Exit1-DR
Exit1-IR
0
0
Pause-DR
Pause-IR
1
1
0
0
Exit2-DR
Exit2-IR
1
1
Update-DR
Update-IR
0
1
1
0
TAP Controller State Diagram
NOTES:
1. Five consecutive TCLK cycles with TMS = 1 will reset the TAP.
2. TAP controller must be reset before normal PLL operations can begin.
RefertotheIEEEStandardTestAccessPortSpecification(IEEEStd.1149.1)
forthefullstatediagram
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction
Register parallel loads a pattern of fixed values on the rising edge of TCLK.
All state transitions within the TAP controller occur at the rising edge of The last two significant bits are always required to be “01”.
theTCLKpulse.TheTMSsignallevel(0or1)determinesthestateprogression Shift-IR In this controller state, the instruction register gets connected
thatoccursoneachTCLKrisingedge.TheTAPcontrollertakesprecedence betweenTDIandTDO, andthecapturedpatterngetsshiftedoneachrising
over the PLL and must be reset after power up of the device. See TRST edgeofTCLK.TheinstructionavailableontheTDIpinisalsoshiftedintothe
descriptionformoredetailsonTAPcontrollerreset.
instructionregister.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenabling
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
thenormaloperationoftheIC.TheTAPcontrollerstatemachineisdesigned IRstateorUpdate-IRstateismade.
insuchawaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-
Pause-IRThisstateisprovidedinordertoallowtheshiftingofinstruction
Logic-ResetstatecanbeenteredbyholdingTMSathighandpulsingTCLK registertobetemporarilyhalted.
five times. This is the reason why the Test Reset (TRST) pin is optional.
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-
Run-Test-IdleInthiscontrollerstate, thetestlogicintheICisactiveonly IRstateorUpdate-IRstateismade.
ifcertaininstructionsarepresent.Forexample,ifaninstructionactivatesthe
Update-IRInthiscontrollerstate,theinstructionintheinstructionregister
selftest,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetest islatchedintothelatchbankoftheInstructionRegisteroneveryfallingedge
logic in the IC is idles otherwise.
Select-DR-ScanThisisacontrollerstatewherethedecisiontoenterthe
DataPathortheSelect-IR-Scanstateismade.
ofTCLK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata
registers selected by the current instruction on the rising edge of TCLK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade. TheControllercanreturntotheTest-Logic-Reset controllerstatesaresimilartotheShift-IR,Exit1-IR,Pause-IR,Exit2-IRand
stateotherwise. Update-IRstatesintheInstructionpath.
14
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
THE INSTRUCTION REGISTER
path. Whenthebypassregisterisselectedbyaninstruction,theshiftregister
stageissettoalogiczeroontherisingedgeofTCLKwhentheTAPcontroller
isintheCapture-DRstate.
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
The Instruction is used to select the test to be performed, or the test data
register to be accessed, or both. The instruction shifted into the register is
latchedatthecompletionoftheshiftingprocesswhentheTAPcontrollerisat
Update-IRstate.
THE BOUNDARY-SCAN REGISTER
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata.Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports.TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
TESTDATAREGISTER
THE DEVICE IDENTIFICATION REGISTER
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
The following sections provide a brief description of each element. For a
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDTJEDECIDnumberis0xB3. Thistranslatesto0x33whentheparityis
dropped in the 11-bit Manufacturer ID field.
For the IDT5T9820, the Part Number field is 0x3A6.
TEST BYPASS REGISTER
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO.Itcontainsasinglestageshiftregisterforaminimumlengthinserial
JTAGDEVICEIDENTIFICATION
REGISTER
31 (MSB)
28 27
Partnumber
(16-bit)
12 11
ManufacturerID
(11-bit)0X33
1 0(LSB)
Version(4bits)
0X0
1
JTAGINSTRUCTIONREGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate.Theinstructionisdecodedto
performthefollowing:
•Selecttestdataregistersthatmayoperatewhiletheinstructioniscurrent.
Theothertestdataregistersshouldnotinterferewithchipoperationandthe
selecteddataregister.
•Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
TDI and TDO during data register scanning.
The Instruction Register is a 4-bit field (i.e.IR3, IR2, IR1, IR0) to decode
sixteendifferentpossibleinstructions.Instructionsaredecodedasfollows.
JTAGINSTRUCTIONREGISTERDECODING
IR (3)
IR (2)
IR (1)
IR (0)
Instruction
Function
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
X
0
1
0
1
0
1
0
1
0
1
X
X
EXTEST
Selectboundaryscanregister
Selectboundaryscanregister
SAMPLE/PRELOAD
IDCODE
Selectchipidentificationdataregister
Reserved
PROGWRITE
PROGREAD
PROGSAVE
PROGRESTORE
CLAMP
Writingtothevolatileprogrammingregisters
Readingfromthevolatileprogrammingregisters
SavingthecontentsofthevolatileprogrammingregisterstotheEEPROM
LoadingtheEEPROMcontentsintothevolatileprogrammingregisters
JTAG
HIGHZ
JTAG
BYPASS
Selectbypassregister
Selectbypassregister
BYPASS
15
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
Thefollowingsectionsprovideabriefdescriptionofeachinstruction.Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
ThePROGRESTOREinstructionisforloadingtheIDT5T9820configuration
datafromtheEEPROMtothedevice’svolatileprogrammingregisters. This
instructionselectstheBYPASSregisterpathforshiftingdatafromTDItoTDO
duringdataregisterscanning.
EXTEST
TherequiredEXTESTinstructionplacestheICintoanexternalboundary-
testmodeandselectstheboundary-scanregistertobeconnectedbetween
TDIandTDO. Duringthisinstruction,theboundary-scanregisterisaccessed
todrivetestdataoff-chipthroughtheboundaryoutputs,andrecievetestdata
off-chipthroughtheboundaryinputs. Assuch,theEXTESTinstructionisthe
workhorseofIEEE.Std1149.1,providingforprobe-lesstestingofsolder-joint
opens/shortsandoflogicclusterfunction.
DuringtheexecutionofaPROGSAVEorPROGRESTOREinstruction,the
IDT5T9820willnotacceptanewprogramminginstruction(read,write,save,
orrestore). Allnon-programmingJTAGinstructionswillfunctionproperly,but
theusershouldwaituntilthesaveorrestoreiscompletebeforeissuinganew
programminginstruction. Thetimeittakesforthesaveandrestoreinstructions
tocompletedependsonthePLLoscillatorfrequency,FVCO. Therestoretime,
TRESTORE, andthesavetime, TSAVE, canbecalculatedasfollows:
TRESTORE = 1.23X106/FVCO
(mS)
SAMPLE/PRELOAD
6
TherequiredSAMPLE/PRELOADinstructionallowstheICtoremainina
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan
beaccessedviaadatascanoperation,totakeasampleofthefunctionaldata
entering and leaving the IC.
TSAVE
FVCO + 52
(mS)
= 3.09X10 /
If a new programming instruction is issued before the save or restore
completes, the new instruction is ignored, and the BYPASS register path
remainsineffectforshiftingdatafromTDItoTDOduringdataregisterscanning.
IDCODE
InorderfortheProgSaveandProgRestoreinstructionstofunctionproperly,
the IDT5T9820 must not be in power-down mode (PD must be HIGH), and
the PLL must be enabled (PLL_EN = LOW and Bit 57 = 0).
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDI and TDO. The device identification register is a 32-bit shift register
containing information regarding the IC manufacturer, device type, and
versioncode. Accessingthedeviceidentificationregisterdoesnotinterfere
withtheoperationoftheIC.Also,accesstothedeviceidentificationregister
shouldbeimmediatelyavailable,viaaTAPdata-scanoperation,afterpower-
up of the IC or after the TAP has been reset using the optional TRST pin or
byotherwisemovingtotheTest-Logic-Resetstate.
Onpower-upoftheIDT5T9820,anautomaticrestoreisperformedtoload
the EEPROM contents into the internal programming registers. The auto-
restorewillnotfunctionproperlyifthedeviceisinpower-downmode(PDmust
beHIGH). Thedevice'sauto-restorefeaturewillfunctionregardlessofthestate
of the PLL_EN pin or Bit 57. The time it takes for the device to complete the
auto-restoreisapproximately3ms.
PROGWRITE
CLAMP
The PROGWRITE instruction is for writing the IDT5T9820 configuration
datatothedevice’svolatileprogrammingregisters. Thisinstructionselectsthe
programmingregisterpathforshiftingdatafromTDItoTDOduringdataregister
scanning. The programming register path has 112 registers (14 bytes)
between TDI and TDO. The 12 configuration data bytes are scanned in
throughTDIfirst,startingwithBit0. Afterscanninginthelastconfigurationbit,
Bit95,sixteenadditionalbitsmustbescannedintoplacetheconfigurationdata
intheproperlocation. Thelastsixteenregistersintheprogrammingpathare
reserved, read-only registers.
TheoptionalCLAMPinstructionloadsthecontentsfromtheboundary-scan
registerontotheoutputsoftheIC,andselectstheone-bitbypassregisterto
be connected between TDI and TDO. During this instruction, data can be
shifted through the bypass register from TDI to TDO without affecting the
conditionoftheICoutputs.
HIGH-IMPEDANCE
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand
selectstheone-bitbypassregistertobeconnectedbetweenTDIandTDO.
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI
toTDOwithoutaffectingtheconditionoftheICoutputs.
PROGREAD
ThePROGREADinstructionisforreadingouttheIDT5T9820configuration
datafromthedevice’svolatileprogrammingregisters. Thisinstructionselects
theprogrammingregisterpathforshiftingdatafromTDItoTDOduringdata
registerscanning. Theprogrammingregisterpathhas112registersbetween
TDI and TDO, and the first bit scanned out through TDO will be Bit 0 of the
configurationdata.
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
functional mode and selects the one-bit bypass register to be connected
between TDI and TDO. The BYPASS instruction allows serial data to be
transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof
theIC.
PROGSAVEandPROGRESTORE(EEPROMOPERATION)
The PROGSAVE instruction is for copying the IDT5T9820 configuration
datafromthedevice’svolatileprogrammingregisterstotheEEPROM. This
instructionselectstheBYPASSregisterpathforshiftingdatafromTDItoTDO
duringdataregisterscanning.
16
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
PROGRAMMINGNOTES
OncetheIDT5T9820hasbeenprogrammedeitherwithaProgWriteorProgRestoreinstruction,thedevicewillattempttoachievephaselockusingthenew
PLLconfiguration. IfthereisavalifREFandFBinputclockconnectedtothedevice,anditdoesnotachievelock,theusershouldissueaProgReadinstruction
toconfirmthatthePLLconfigurationdataisvalid.
Onpower-upandbeforetheautomaticProgRestoreinstructionhascompleted,theinternalprogrammingregisterswillcontainthevalueof'0'forallbits95:0.
ThePLLwillremainattheminimumfrequencyandwillnotachievephaselockuntilaftertheautomaticrestoreiscompleted. Iftheoutputsareenabledbythe
nSOEpins,theoutputswilltoggleattheminimumfrequency. IftheoutputsaredisabledbythenSOEpins,andtheOMODEpinissethigh,thenQ[1:0]and
QFB are stopped HIGH, while QFB is stopped LOW.
tTCLK
t4
t2
t1
TCLK
t3
TDI/TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
t5
Standard JTAG Timing
NOTE:
t1 = tTCLKLOW
t2 = tTCLKHIGH
t3 = tTCLKFALL
t4 = tTCLKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
JTAG
ACELECTRICALCHARACTERISTICS
SYSTEMINTERFACEPARAMETERS
Symbol
Parameter
Min.
100
40
Max.
Units
Symbol
Parameter
DataOutput(1)
Min.
Max.
Units
tTCLK
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
—
ns
tDO
—
20
ns
tDOH
tDS
DataOutputHold(1)
DataInput, tRISE =3ns
DataInput, tFALL =3ns
0
—
ns
tTCLKHIGH
tTCLKLOW
tTCLKRISE
tTCLKFALL
tRST
—
ns
40
—
ns
10
—
ns
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAGReset
—
5(1)
5(1)
—
ns
tDH
10
—
ns
—
ns
NOTE:
1. 50pF loading on external output signals.
50
ns
tRSR
JTAG Reset Recovery
50
—
ns
NOTE:
1. Guaranteed by design.
17
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
Symbol
VIHH
Parameter
Test Conditions
Min.
Max
Unit
V
Input HIGH Voltage Level(1)
Input MID Voltage Level(1)
InputLOWVoltageLevel(1)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
VIN = VDD
VDD – 0.4
—
VIMM
VDD/2 – 0.2 VDD/2 + 0.2
V
VILL
—
—
0.4
200
+50
—
V
HIGH Level
MID Level
LOW Level
I3
3-LevelInputDCCurrent
(ADDR0, ADDR1)
VIN = VDD/2
–50
–200
–100
µA
µA
VIN = GND
IPU
InputPull-UpCurrent
VDD = Max., VIN = GND
—
NOTE:
1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched dynamically after powerup,
the function and timing of the outputs may be glitched, and the PLL may require additional tLOCK time before all datasheet limits are achieved.
18
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFORHSTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(7)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current
VDD = 2.7V
VDD = 2.7V
VI = VDDQN/GND
VI = GND/VDDQN
—
—
—
±5
±5
µA
InputLOWCurrent
—
—
VIK
ClampDiodeVoltage
VDD = 2.3V, IIN = -18mA
- 0.7
- 1.2
+3.6
—
V
VIN
VDIF
VCM
VIH
VIL
DCInputVoltage
- 0.3
0.2
V
DCDifferentialVoltage(2,8)
DC Common Mode Input Voltage(3,8)
DC Input HIGH(4,5,8)
DC Input LOW(4,6,8)
Single-EndedReferenceVoltage(4,8)
V
680
750
750
900
mV
mV
mV
mV
VREF + 100
—
—
VREF - 100
—
VREF
—
OutputCharacteristics
VOH
VOL
VOX
Output HIGH Voltage
IOH = -8mA
IOH = -100µA
IOL = 8mA
VDDQN - 0.4
—
—
V
V
VDDQN - 0.1
OutputLOWVoltage
—
—
0.4
0.1
IOL = 100µA
FB/FB Output Crossing Point
VDDQN/2 - 150 VDDQN/2 VDDQN/2 + 150
mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQN = 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
POWERSUPPLYCHARACTERISTICSFORHSTLOUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current(3)
VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, Outputs enabled, All outputs unloaded
VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, Outputs enabled, All outputs unloaded
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH
VDD = Max., VDDQN = Max., CL = 0pF
112
150
mA
IDDQQ
Quiescent VDDQN Power Supply Current(3)
3
75
µA
IDDPD
Power Down Current
0.7
22
3
mA
IDDD
Dynamic VDD Power Supply
CurrentperOutput
30
µA/MHz
IDDDQ
ITOT
Dynamic VDDQN Power Supply
CurrentperOutput
Total Power VDD Supply Current(4,5)
VDD = Max., VDDQN = Max., CL = 0pF
18
30
µA/MHz
mA
VDDQN = 1.5V, FVCO = 100MHz, CL = 15pF
VDDQN = 1.5V, FVCO = 250MHz, CL = 15pF
VDDQN = 1.5V, FVCO = 100MHz, CL = 15pF
VDDQN = 1.5V, FVCO = 250MHz, CL = 15pF
280
320
130
225
400
450
200
330
ITOTQ
Total Power VDDQN Supply Current(4,5)
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. Bit 60 = 1.
5. All outputs are at the same interface level.
19
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL
Symbol
VDIF
Parameter
Value
Units
V
InputSignalSwing(1)
1
VX
DifferentialInputSignalCrossingPoint(2)
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
750
mV
V
VTHI
CrossingPoint
1
tR, tF
V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOReHSTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(7)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current
VDD = 2.7V
VDD = 2.7V
VI = VDDQN/GND
VI = GND/VDDQN
—
—
—
±5
±5
µA
InputLOWCurrent
—
—
VIK
ClampDiodeVoltage
VDD = 2.3V, IIN = -18mA
- 0.7
- 1.2
+3.6
—
V
VIN
VDIF
VCM
VIH
VIL
DCInputVoltage
- 0.3
0.2
V
DCDifferentialVoltage(2,8)
DC Common Mode Input Voltage(3,8)
DC Input HIGH(4,5,8)
DC Input LOW(4,6,8)
Single-EndedReferenceVoltage(4,8)
V
800
900
900
1000
—
mV
mV
mV
mV
VREF + 100
—
VREF - 100
—
VREF
—
OutputCharacteristics
VOH
VOL
VOX
Output HIGH Voltage
IOH = -8mA
IOH = -100µA
IOL = 8mA
VDDQN - 0.4
—
—
V
V
VDDQN - 0.1
OutputLOWVoltage
—
—
0.4
0.1
V
IOL = 100µA
V
FB/FB Output Crossing Point
VDDQN/2 - 150 VDDQN/2 VDDQN/2 + 150
mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in a differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQN = 1.8V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
20
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
POWERSUPPLYCHARACTERISTICSFOReHSTLOUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current(3)
VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, Outputs enabled, All outputs unloaded
VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, Outputs enabled, All outputs unloaded
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH
VDD = Max., VDDQN = Max., CL = 0pF
112
150
mA
IDDQQ
Quiescent VDDQN Power Supply Current(3)
3
75
µA
IDDPD
Power Down Current
0.7
22
3
mA
IDDD
Dynamic VDD Power Supply
CurrentperOutput
30
µA/MHz
IDDDQ
ITOT
Dynamic VDDQN Power Supply
VDD = Max., VDDQN = Max., CL = 0pF
22
30
µA/MHz
mA
CurrentperOutput
Total Power VDD Supply Current(4,5)
VDDQN = 1.8V, FVCO = 100MHz, CL = 15pF
VDDQN = 1.8V, FVCO = 250MHz, CL = 15pF
VDDQN = 1.8V, FVCO = 100MHz, CL = 15pF
VDDQN = 1.8V, FVCO = 250MHz, CL = 15pF
280
320
160
280
400
450
250
400
ITOTQ
Total Power VDDQN Supply Current(4,5)
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. Bit 60 = 1.
5. All outputs are at the same interface level.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL
Symbol
VDIF
Parameter
Value
Units
InputSignalSwing(1)
1
V
mV
V
VX
DifferentialInputSignalCrossingPoint(2)
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
900
VTHI
CrossingPoint
1
tR, tF
V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
21
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR
LVEPECL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(2)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current
VDD = 2.7V
VDD = 2.7V
VDD = 2.3V, IIN = -18mA
VI = VDDQN/GND
—
—
—
—
±5
±5
µA
InputLOWCurrent
VI = GND/VDDQN
VIK
ClampDiodeVoltage
—
- 0.7
—
- 1.2
3.6
V
VIN
VCM
VREF
VIH
VIL
DCInputVoltage
- 0.3
915
—
V
DC Common Mode Input Voltage(3,5)
Single-EndedReferenceVoltage(4,5)
DC Input HIGH
1082
1082
—
1248
—
mV
mV
mV
mV
1275
555
1620
875
DC Input LOW
—
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, +25°C ambient.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation while in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
DIFFERENTIALINPUTACTESTCONDITIONSFORLVEPECL
Symbol
VDIF
Parameter
Value
Units
mV
mV
V
InputSignalSwing(1)
732
VX
DifferentialInputSignalCrossingPoint(2)
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
1082
CrossingPoint
1
VTHI
tR, tF
V/ns
NOTES:
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
22
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR2.5V
LVTTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(8)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current
InputLOWCurrent
ClampDiodeVoltage
DCInputVoltage
VDD = 2.7V
VDD = 2.7V
VI = VDDQN/GND
VI = GND/VDDQN
—
—
—
—
±5
±5
µA
VIK
VIN
VDD = 2.3V, IIN = -18mA
—
- 0.7
- 1.2
+3.6
V
V
- 0.3
Single-Ended Inputs(2)
VIH
DC Input HIGH
DC Input LOW
1.7
—
—
V
V
VIL
0.7
DifferentialInputs
VDIF
VCM
VIH
DCDifferentialVoltage(3,9)
DC Common Mode Input Voltage(4,9)
DC Input HIGH(5,6,9)
DC Input LOW(5,7,9)
Single-EndedReferenceVoltage(5,9)
0.2
1150
—
1350
V
1250
1250
mV
mV
mV
mV
VREF + 100
—
—
VIL
VREF - 100
—
VREF
—
OutputCharacteristics
VOH
VOL
Output HIGH Voltage
IOH = -12mA
IOH = -100µA
IOL = 12mA
IOL = 100µA
VDDQN - 0.4
—
—
V
V
V
V
VDDQN - 0.1
OutputLOWVoltage
—
—
0.4
0.1
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 2.5V LVTTL single-ended operation, Bits 35/34, 33/32, 31/30 = 0/1 or 1/0, and REF[1:0]/VREF[1:0] is left floating. If Bits 47 - 36 = 0, FB/VREF2 should be left floating.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQN = VDD, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
23
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICSFOR2.5VLVTTLOUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current(3)
VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, Outputs enabled, All outputs unloaded
VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, Outputs enabled, All outputs unloaded
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH
VDD = Max., VDDQN = Max., CL = 0pF
112
150
mA
IDDQQ
Quiescent VDDQN Power Supply Current(3)
20
75
µA
IDDPD
Power Down Current
0.7
19
3
mA
IDDD
Dynamic VDD Power Supply
CurrentperOutput
30
µA/MHz
IDDDQ
ITOT
Dynamic VDDQN Power Supply
CurrentperOutput
Total Power VDD Supply Current(4,5)
VDD = Max., VDDQN = Max., CL = 0pF
32
40
µA/MHz
mA
VDDQN = 2.5V., FVCO = 100MHz, CL = 15pF
VDDQN = 2.5V., FVCO = 250MHz, CL = 15pF
VDDQN = 2.5V., FVCO = 100MHz, CL = 15pF
VDDQN = 2.5V., FVCO = 250MHz, CL = 15pF
275
315
215
355
400
450
320
530
ITOTQ
Total Power VDDQN Supply Current(4,5)
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. Bit 60 = 1.
5. All outputs are at the same interface level.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 2.5V LVTTL
Symbol
VDIF
Parameter
Value
VDD
Units
InputSignalSwing(1)
V
V
VX
DifferentialInputSignalCrossingPoint(2)
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
VDD/2
VTHI
CrossingPoint
2.5
V
tR, tF
V/ns
NOTES:
1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF
(AC) specification under actual use conditions.
2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2.5V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 2.5V LVTTL
Symbol
VIH
Parameter
Value
VDD
0
Units
V
Input HIGH Voltage
VIL
InputLOWVoltage
V
VTHI
InputTimingMeasurementReferenceLevel(1)
InputSignalEdgeRate(2)
VDD/2
2
V
tR, tF
V/ns
NOTES:
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
24
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR1.8V
LVTTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(8)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current
InputLOWCurrent
ClampDiodeVoltage
DCInputVoltage
VDD = 2.7V
VDD = 2.7V
VI = VDDQN/GND
VI = GND/VDDQN
—
—
—
—
±5
±5
µA
VIK
VIN
VDD = 2.3V, IIN = -18mA
—
- 0.7
- 1.2
V
V
- 0.3
VDDQN + 0.3
Single-Ended Inputs(2)
VIH
DC Input HIGH
DC Input LOW
1.073(10)
—
—
0.683(11)
V
V
VIL
DifferentialInputs
VDIF
VCM
VIH
DCDifferentialVoltage(3,9)
DC Common Mode Input Voltage(4,9)
DC Input HIGH(5,6,9)
DC Input LOW(5,7,9)
Single-EndedReferenceVoltage(5,9)
0.2
825
—
975
V
900
900
mV
mV
mV
mV
VREF + 100
—
—
VIL
VREF - 100
—
VREF
—
OutputCharacteristics
VOH
VOL
Output HIGH Voltage
IOH = -6mA
IOH = -100µA
IOL = 6mA
VDDQN - 0.4
—
—
V
V
V
V
VDDQN - 0.1
OutputLOWVoltage
—
—
0.4
0.1
IOL = 100µA
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 1.8V LVTTL single-ended operation, Bits 35 - 30 = 0 and REF[1:0]/VREF[1:0] is left floating. If Bits 47/46, 45/44, 43/42, 41/40, 39/38, 37/36 = 0/1, FB/VREF2 should be left floating.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. The input is guaranteed to toggle within ±200mV of VREF[1:0] when VREF[1:0]
is constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the REF[1:0] input. To guarantee switching in voltage range
specified in the JEDEC 1.8V LVTTL interface specification, VREF[1:0] must be maintained at 900mV with appropriate tolerances.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQN = 1.8V, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 * VDD where VDD is 1.8V ± 0.15V.
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated
worst case value ( VIH = 0.65 * [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply.
11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 * VDD where VDD is 1.8V ± 0.15V.
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated
worst case value ( VIL = 0.35 * [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply.
25
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICSFOR1.8VLVTTLOUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current(3)
VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, Outputs enabled, All outputs unloaded
VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW,
PLL_EN = HIGH, Outputs enabled, All outputs unloaded
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH
VDD = Max., VDDQN = Max., CL = 0pF
112
150
mA
IDDQQ
Quiescent VDDQN Power Supply Current(3)
3
75
µA
IDDPD
Power Down Current
0.7
18
3
mA
IDDD
Dynamic VDD Power Supply
CurrentperOutput
30
µA/MHz
IDDDQ
ITOT
Dynamic VDDQN Power Supply
VDD = Max., VDDQN = Max., CL = 0pF
19
30
µA/MHz
mA
CurrentperOutput
Total Power VDD Supply Current(4,5)
VDDQN = 1.8V., FVCO = 100MHz, CL = 15pF
VDDQN = 1.8V., FVCO = 250MHz, CL = 15pF
VDDQN = 1.8V., FVCO = 100MHz, CL = 15pF
VDDQN = 1.8V., FVCO = 250MHz, CL = 15pF
275
310
135
200
400
450
200
300
ITOTQ
Total Power VDDQN Supply Current(4,5)
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. Bit 60 = 1.
5. All outputs are at the same interface level.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol
VDIF
Parameter
Value
VDDI
Units
InputSignalSwing(1)
V
mV
V
VX
DifferentialInputSignalCrossingPoint(2)
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
VDDI/2
VTHI
CrossingPoint
1.8
tR, tF
V/ns
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable
results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions.
2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1.8V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol
VIH
Parameter
Value
VDDI
0
Units
V
Input HIGH Voltage(1)
VIL
InputLOWVoltage
V
VTHI
InputTimingMeasurementReferenceLevel(2)
InputSignalEdgeRate(3)
VDDI/2
2
mV
V/ns
tR, tF
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input.
2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
3. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
26
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
ACELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
Alloutputsatthesameinterfacelevel
Symbol
FNOM
tRPW
Parameter
Min.
Typ.
Max
Unit
VCO Frequency Range
see JTAG/I2C Serial Configurations: VCO Frequency Range table
Reference Clock Pulse Width HIGH or LOW
Feedback Input Pulse Width HIGH or LOW
Output Matched Pair Skew(1,2,4)
OutputSkew(Rise-Rise,Fall-Fall,Nominal)(1,3)
MultipleFrequencySkew(Rise-Rise,Fall-Fall,Nominal-Divided,Divided-Divided)(1,3,4)
MultipleFrequencySkew(Rise-Fall,Nominal-Divided,Divided-Divided)(1,3,4)
InvertingSkew(Nominal-Inverted)(1,3)
InvertingSkew(Rise-Rise,Fall-Fall,Rise-Fall,Inverted-Divided)(1,3,4)
Process Skew(1,3.5)
REF Input to FB Static Phase Offset(6)
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
—
—
—
—
—
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
tFPW
tSK(B)
—
—
—
—
—
—
—
-100
-375
-275
—
—
—
—
—
—
—
—
—
—
—
—
—
50
tSK(O)
100
100
400
400
400
300
100
375
275
1.2
1
tSK1(ω)
tSK2(ω)
tSK1(INV)
tSK2(INV)
tSK(PR)
t(φ)
tODCV
Output Duty Cycle Variation from 50%(7)
HSTL / eHSTL / 1.8V LVTTL
2.5VLVTTL
tORISE
tOFALL
OutputRiseTime(8)
HSTL / eHSTL / 1.8V LVTTL
2.5VLVTTL
ns
ns
OutputFallTime(8)
HSTL / eHSTL / 1.8V LVTTL
2.5VLVTTL
1.2
1
tL
Power-upPLLLockTime(9)
PLLLockTimeAfterInputFrequencyChange(9)
PLL Lock Time After Change in REF_SEL (9,11)
PLLLockTimeAfterChangeinREF_SEL(REF1 andREF0aredifferentfrequency)(9)
PLL Lock Time After Asserting PD Pin(9)
Cycle-to-CycleOutputJitter(peak-to-peak)(10)
PeriodJitter(peak-to-peak)(10)
4
ms
ms
µs
ms
ms
ps
tL(ω)
1
tL(REFSEL1)
tL(REFSEL2)
tL(PD)
100
1
1
tJIT(CC)
tJIT(PER)
75
75
ps
tJIT(HP)
tJIT(DUTY)
VOX
Half Period Jitter (peak-to-peak, QFB/QFB only)(10, 12)
DutyCycleJitter(peak-to-peak)(10)
125
100
ps
ps
HSTLandeHSTLDifferentialTrueandComplementaryOutputCrossingVoltageLevel
QFB/QFB only(12)
VDDQN/2 - 150 VDDQN/2 VDDQN/2 + 150 mV
NOTES:
1. Skew is the time between the earliest and latest output transition among all outputs when all outputs are loaded with the specified load.
2. tSK(B) is the skew between a pair of outputs (nQ0 and nQ1) when all outputs are selected as the same class.
3. The measurement is made at VDDQN/2.
4. There are three classes of outputs: nominal (zero delay), inverted, and divided (divide-by-2 or divide-by-4 mode).
5. tSK(PR) is the output to corresponding output skew between any two devices operating under the same conditions (VDD and VDDQN, ambient temperature, air flow, etc.).
6. t(φ) is measured with REF and FB the same type of input, the same rise and fall times. For 1.8V / 2.5V LVTTL input and output, the measurement is taken from VTHI on REF
to VTHI on FB. For HSTL / eHSTL input and output, the measurement is taken from the crosspoint of REF/REF to the crosspoint of FB/FB. All outputs are set to zero delay,
FB input divider set to divide-by-one, and Bit 60 = 1.
7. tODCV is measured with all outputs selected for zero delay.
8. Output rise and fall times are measured between 20% to 80% of the actual output voltage swing.
9. tL, tL(ω), tL(REFSEL1), tL(REFSEL2), and tL(PD) are the times that are required before the synchronization is achieved. These specifications are valid only after VDD/VDDQN is stable and
within the normal operating limits. These parameters are measured from the application of a new signal at REF or FB, or after PD is (re)asserted until t(φ) is within specified
limits.
10. The jitter parameters are measured with all outputs selected for zero delay, FB input divider is set to divide-by-one, and Bit 60 = 1.
11. Both REF inputs must be the same frequency, but up to ±180° out of phase.
12. For HSTL/eHSTL outputs only.
27
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
Alloutputsatthedifferentinterfacelevels
Symbol
FNOM
tRPW
Parameter
Min.
Typ.
Max
Unit
VCO Frequency Range
see JTAG/I2C Serial Configurations: VCO Frequency Range table
Reference Clock Pulse Width HIGH or LOW
Feedback Input Pulse Width HIGH or LOW
Output Matched Pair Skew(1,2,4)
OutputSkew(Rise-Rise,Fall-Fall,Nominal)(1,3)
MultipleFrequencySkew(Rise-Rise,Fall-Fall,Nominal-Divided,Divided-Divided)(1,3,4)
MultipleFrequencySkew(Rise-Fall,Nominal-Divided,Divided-Divided)(1,3,4)
InvertingSkew(Nominal-Inverted)(1,3)
InvertingSkew(Rise-Rise,Fall-Fall,Rise-Fall,Inverted-Divided)(1,3,4)
Process Skew(1,3.5)
REF Input to FB Static Phase Offset(6)
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
tFPW
tSK(B)
—
—
—
—
—
—
—
-200
-475
-375
—
—
—
—
—
—
—
—
—
—
—
—
—
200
250
500
500
500
500
400
200
475
375
1.2
1
tSK(O)
tSK1(ω)
tSK2(ω)
tSK1(INV)
tSK2(INV)
tSK(PR)
t(φ)
tODCV
Output Duty Cycle Variation from 50%(7)
OutputRiseTime(8)
HSTL / eHSTL / 1.8V LVTTL
2.5VLVTTL
tORISE
tOFALL
HSTL / eHSTL / 1.8V LVTTL
2.5VLVTTL
ns
ns
OutputFallTime(8)
HSTL / eHSTL / 1.8V LVTTL
2.5VLVTTL
1.2
1
tL
Power-upPLLLockTime(9)
PLLLockTimeAfterInputFrequencyChange(9)
PLL Lock Time After Change in REF_SEL (9,11)
PLLLockTimeAfterChangeinREF_SEL(REF1 andREF0aredifferentfrequency)(9)
PLL Lock Time After Asserting PD Pin(9)
Cycle-to-CycleOutputJitter(peak-to-peak)(10)
PeriodJitter(peak-to-peak)(10)
4
ms
ms
µs
ms
ms
ps
tL(ω)
1
tL(REFSEL1)
tL(REFSEL2)
tL(PD)
100
1
1
tJIT(CC)
tJIT(PER)
100
150
200
150
ps
tJIT(HP)
tJIT(DUTY)
VOX
Half Period Jitter (peak-to-peak, QFB/QFB only)(10, 12)
DutyCycleJitter(peak-to-peak)(10)
ps
ps
HSTLandeHSTLDifferentialTrueandComplementaryOutputCrossingVoltageLevel
QFB/QFB only(12)
VDDQN/2 - 150 VDDQN/2 VDDQN/2 + 150 mV
NOTES:
1. Skew is the time between the earliest and latest output transition among all outputs when all outputs are loaded with the specified load.
2. tSK(B) is the skew between a pair of outputs (nQ0 and nQ1) when all outputs are selected as the same class.
3. The measurement is made at VDDQN/2.
4. There are three classes of outputs: nominal (zero delay), inverted, and divided (divide-by-2 or divide-by-4 mode).
5. tSK(PR) is the output to corresponding output skew between any two devices operating under the same conditions (VDD and VDDQN, ambient temperature, air flow, etc.).
6. t(φ) is measured with REF and FB the same type of input, the same rise and fall times. For 1.8V / 2.5V LVTTL input and output, the measurement is taken from VTHI on REF
to VTHI on FB. For HSTL / eHSTL input and output, the measurement is taken from the crosspoint of REF/REF to the crosspoint of FB/FB. All outputs are set to zero delay,
FB input divider set to divide-by-one, and Bit 60 = 1.
7. tODCV is measured with all outputs selected for zero delay.
8. Output rise and fall times are measured between 20% to 80% of the actual output voltage swing.
9. tL, tL(ω), tL(REFSEL1), tL(REFSEL2), and tL(PD) are the times that are required before the synchronization is achieved. These specifications are valid only after VDD/VDDQN is stable and
within the normal operating limits. These parameters are measured from the application of a new signal at REF or FB, or after PD is (re)asserted until t(φ) is within specified
limits.
10. The jitter parameters are measured with all outputs selected for zero delay, FB input divider is set to divide-by-one, and Bit 60 = 1.
11. Both REF inputs must be the same frequency, but up to ±180° out of phase.
12. For HSTL/eHSTL outputs only.
28
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
ACDIFFERENTIALINPUTSPECIFICATIONS(1)
Symbol
Parameter
Min.
Typ.
—
Max
—
Unit
t W
Reference/FeedbackInputClockPulseWidthHIGHorLOW(HSTL/eHSTLoutputs)(2)
Reference/Feedback Input Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL outputs)(2)
1
1
ns
—
—
HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL
VDIF
VIH
ACDifferentialVoltage(3)
AC Input HIGH(4,5)
AC Input LOW(4,6)
400
Vx + 200
—
—
—
—
—
—
mV
mV
mV
VIL
Vx - 200
LVEPECL
VDIF
ACDifferentialVoltage(3)
AC Input HIGH(4)
AC Input LOW(4)
400
1275
—
—
—
—
—
—
mV
mV
mV
VIH
VIL
875
NOTES:
1. For differential input mode, Bits 35 - 30 = 1.
2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the voltage range defined
by VDIF has been met or exceeded.
3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level.
The AC differential voltage must be achieved to guarantee switching to a new state.
4. For single-ended operation, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. Refer to each input interface's DC specification for the correct VREF[1:0] range.
5. Voltage required to switch to a logic HIGH, single-ended operation only.
6. Voltage required to switch to a logic LOW, single-ended operation only.
29
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
AC TIMING DIAGRAM(1)
tRPWL
tRPWH
REF
REF
tFPWH
tFPWL
tODCV
tODCV
FB
FB
tODCV
tODCV
Q
tSK(O),
tSK(B)
tSK(O),
tSK(B)
OTHER Q
tSK1(INV)
tSK1(INV)
INVERTED Q
Q DIVIDED BY 2
Q DIVIDED BY 4
tSK2(ω),
tSK2(INV)
tSK2(INV)
tSK2(ω)
tSK1(ω)
tSK1(ω),
tSK2(INV)
NOTE:
1. The AC TIMING DIAGRAM applies to Bit 58 = 1. For Bit 58 = 0, the negative edge of FB aligns with the negative edge of REF[1:0], divided outputs change on the negative
edge of REF[1:0], and the positive edges of the divide-by-2 and divide-by-4 signals align.
30
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
JITTERANDOFFSETTIMINGWAVEFORMS
QFB
nQ[1:0], QFB
tcycle n + 1
tcycle n
=
tjit(cc) tcycle n
tcycle n+1
Cycle-to-Cycle jitter
REF[1:0]
REF[1:0]
FB
FB
t(Ø)n + 1
t(Ø)n
n = N
∑
1
t(Ø)n
=
t(Ø)
(N is a large number of samples)
N
Static Phase Offset
NOTE:
1. Diagram for Bit 58 = 1 and HSTL / eHSTL input and output.
QFB
nQ[1:0], QFB
tW(MIN)
tW(MAX)
tJIT(DUTY) = tW(MAX) - tW(MIN)
Duty-Cycle Jitter
31
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
QFB
nQ[1:0], QFB
tcycle n
QFB
nQ[1:0], QFB
1
f
o
1
=
tjit(per) tcycle n
f
o
Period jitter
NOTE:
1. 1/fo = average period.
QFB
QFB
thalf period n + 1
thalf period n
QFB
QFB
1
f
o
1
2*f
=
tjit(hper) thalf period n
o
Half-Period jitter
NOTE:
1. 1/fo = average period.
32
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
TESTCIRCUITSANDCONDITIONS
VDDI
R1
R2
3 inch, ~50Ω
Transmission Line
VIN
VDDQN
VDD
VDDI
REF[1:0]
D.U.T.
Pulse
Generator
R1
R2
REF[1:0]
3 inch, ~50Ω
Transmission Line
VIN
Test Circuit for Differential Input(1)
DIFFERENTIALINPUTTESTCONDITIONS
Symbol
VDD = 2.5V ± 0.2V
Unit
R1
100
100
Ω
Ω
R2
VDDI
VCM*2
V
HSTL: Crossing of REF[1:0] and REF[1:0]
eHSTL: Crossing of REF[1:0] and REF[1:0]
LVEPECL: Crossing of REF[1:0] and REF[1:0]
1.8V LVTTL: VDDI/2
VTHI
V
2.5V LVTTL: VDD/2
NOTE:
1. This input configuration is used for all input interfaces. For single-ended testing,
the REF[1:0] must be left floating. For testing single-ended in differential input
mode, the VIN should be floating.
33
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
VDDQN
VDDQN
R1
VDDQN
VDD
VDDQN
VDD
R1
R2
REF[1:0]
R2
CL
REF[1:0]
nQ[1:0]
VDDQN
QFB
D.U.T.
D.U.T.
FB
FB
QFB
R1
CL
QFB
FB
FB
QFB
R2
CL
SW1
SW1
Test Circuit for Outputs
Test Circuit for Differential Feedback
DIFFERENTIALFEEDBACKTEST
CONDITIONS
OUTPUTTESTCONDITIONS
Symbol
VDD = 2.5V ± 0.2V
VDDQN = Interface Specified
15
Unit
Symbol
VDD = 2.5V ± 0.2V
Unit
VDDQN = Interface Specified
CL
R1
pF
Ω
Ω
V
CL
R1
15
100
pF
Ω
Ω
100
R2
100
R2
100
VOX
HSTL: Crossing of QFB and QFB
eHSTL: Crossing of QFB and QFB
1.8V LVTTL: VDDQN/2
2.5V LVTTL: VDDQN/2
1.8V/2.5V LVTTL
HSTL/eHSTL
VTHO
SW1
VDDQN/2
V
1.8V/2.5V LVTTL
HSTL/eHSTL
Open
Closed
VTHO
V
SW1
Open
Closed
34
IDT5T9820
INDUSTRIALTEMPERATURERANGE
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
RECOMMENDEDLANDINGPATTERN
NL 68 pin
NOTE: All dimensions are in millimeters.
35
IDT5T9820
EEPROMPROGRAMMABLE2.5VZERODELAYPLLCLOCKDRIVER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
X
XXXXX
XX
IDT
Package Package
Device Type
I
-40°C to +85°C (Industrial)
Thermally Enhanced Plastic Very Fine
Pitch Quad Flat No Lead Package
NL
5T9820
EEPROM Programmable 2.5V Zero Delay
PLL Clock Driver
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
for Tech Support:
logichelp@idt.com
(408) 654-6459
36
相关型号：
5T9890NLGI
Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), PQCC68, GREEN, PLASTIC, VFQFPN-68
IDT
5T9890NLGI8
Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), PQCC68, GREEN, PLASTIC, VFQFPN-68
IDT
5T9890NLI
Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), PQCC68, PLASTIC, VFQFPN-68
IDT
5T9890NLI8
Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), PQCC68, PLASTIC, VFQFPN-68
IDT
5T9891NLGI8
Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), PQCC68, GREEN, PLASTIC, VFQFN-68
IDT
5T9891NLI
Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), PQCC68, PLASTIC, VFQFN-68
IDT
5T9891NLI8
Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), PQCC68, PLASTIC, VFQFN-68
IDT
5T9950PFI
PLL Based Clock Driver, 5T Series, 8 True Output(s), 0 Inverted Output(s), PQFP32, TQFP-32
IDT
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