5PB1104CMGI/W [IDT]
1.8V to 3.3V LVCMOS High Performance Clock Buffer Family;
| 型号： | 5PB1104CMGI/W |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 1.8V to 3.3V LVCMOS High Performance Clock Buffer Family |
| 文件： | 总19页 (文件大小：504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.8V to 3.3V LVCMOS High Performance
Clock Buffer Family
5PB11xx
DATASHEET
Description
Features
The 5PB11xx is a high-performance LVCMOS Clock Buffer
Family. It has best-in-class Additive Phase Jitter of 50fsec
RMS.
• High performance 1:2, 1:4, 1:6, 1:8, 1:10 LVCMOS clock
buffer
• Very low pin-to-pin skew <50 ps
• Very low additive jitter <50 fs
• Supply voltage: 1.8V to 3.3V
• fMAX = 200MHz
• Integrated serial termination for 50ohm channel
• Packaged in 8-, 14-, 16-, 20-pin TSSOP and small DFN
and QFN packages
There are five different fan-out variations, 1:2 to 1:10,
available.
The IDT5PB11xx also supports a synchronous glitch-free
Output Enable function to eliminate any potential intermediate
incorrect output clock cycles when enabling or disabling
outputs. It comes in various packages and can operate from a
1.8V to 3.3V supply.
• Extended (-40°C to +105°C) temperature range
Block Diagram
LVCMOS
LVCMOS
CLKIN
Y0
LVCMOS
Y1
LVCMOS
Y2
LVCMOS
Y3
LVCMOS
Yn
1G
5PB11xx MAY 13, 2016
1
©2016 Integrated Device Technology, Inc.
5PB11xx DATASHEET
Pin Assignments for TSSOP Packages
Y1
CLKIN
1G
1
2
3
4
8
7
6
5
Y1
Y3
CLKIN
1G
1
2
3
4
5
6
7
14
13
Y1
Y3
CLKIN
1G
1
2
20
19
NC
5PB1102PGGI
Y0
VDD
NC
Y0
12 VDD
Y0
3
18 VDD
GND
Y2
11
GND
VDD
Y4
5PB1106PGGI
Y2
17
GND
VDD
Y4
4
10 GND
16 GND
5
5PB1110PGGI
9
6
Y5
15
14
13
12
11
Y5
Y1
CLKIN
1G
1
2
3
4
8
7
6
5
GND
VDD
8
GND
Y6
VDD
Y7
7
Y3
5PB1104PGGI
8
Y0
VDD
Y2
Y8
9
VDD
Y9
GND
Y1
Y3
CLKIN
1G
1
2
3
4
5
6
7
8
16
15
GND
10
Y0
14 VDD
Y2
13
GND
VDD
Y4
5PB1108PGGI
12 GND
11
10
9
Y5
GND
Y6
VDD
Y7
Pin Descriptions for TSSOP Packages
LVCMOS
Clock Input
Clock Output
Enable
LVCMOS Clock Output
Supply Voltage
Ground
Device Number
CLKIN
1G
2
Y0, Y1, . . . Y9
3, 8
VDD
6
GND
4
5PB1102PGGI
5PB1104PGGI
5PB1106PGGI
5PB1108PGGI
5PB1110PGGI
1
1
1
1
1
2
3, 8, 5, 7
6
4
2
3, 14, 11, 13, 6, 9
3, 16, 13, 15, 6, 11, 8, 9
3, 20, 17, 19, 6, 15, 8, 13, 12, 10
5, 8, 12
5, 10, 14
5, 9, 14, 18
4, 7, 10
4, 7, 12
4, 7, 11, 16
2
2
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
2
MAY 13, 2016
5PB11xx DATASHEET
Pin Assignments for DFN/QFN Packages
Y1
CLKIN
1G
1
2
3
4
8
7
6
5
NC
VDD
NC
5PB1102CMGI
Y0
20 19 18 17 16
13
14
16 15
GND
1
2
3
4
5
15
14
13
12
11
Y0
GND
VDD
Y4
Y2
12
11
10
9
Y0
1
2
3
4
VDD
Y2
GND
Y5
GND
5PB1106CMGI
5PB1110NDGI
GND
Y5
Y1
VDD
Y4
CLKIN
1G
1
2
3
4
8
7
6
5
VDD
Y7
Y3
5PB1104CMGI
6
7 8
5
GND
Y0
VDD
Y2
6
7 8 9 10
GND
13
14
16 15
12
11
10
9
Y0
GND
VDD
Y4
1
2
3
4
VDD
Y2
5PB1108CMGI
GND
Y5
6
7 8
5
Pin Descriptions for DFN/QFN Packages
LVCMOS
Clock Input
Clock Output
Enable
LVCMOS Clock Output
Supply Voltage
Ground
Device Number
CLKIN
1G
2
Y0, Y1, . . . Y9
3, 8
VDD
6
GND
4
5PB1102CMGI
5PB1104CMGI
5PB1106CMGI
5PB1108CMGI
5PB1110NDGI
1
1
2
3, 5, 7, 8
6
4
15
15
19
16
16
20
1, 4, 9, 11, 13, 14
1, 4, 6, 7, 9, 11, 13, 14
1, 4, 6, 8, 10, 11, 13, 15, 17, 18
3, 8, 12
3, 8, 12
3, 7, 12, 16
2, 5, 10
2, 5, 10
2, 5, 9, 14
Output Logic Table
Inputs
Output
CLKIN
1G
Yn
L
X
L
L
H
H
L
H
H
After at least three cycles of input clock toggling. Output Enable function is asynchronous to eliminate any intermediate incorrect output clock cycles during transition which may cause
frequency peaking to the downstream device.
MAY 13, 2016
3
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
5PB11xx DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 5PB11xx. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
Item
Rating
Supply Voltage, VDD
Output Enable and All Outputs
CLKIN
3.465V
-0.4 V to VDD+0.5 V
-0.4 V to 3.465V
-40 to +105C
-65 to +150C
125C
Ambient Operating Temperature (extended)
Storage Temperature
Junction Temperature
Soldering Temperature
260C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+105
Units
C
Ambient Operating Temperature (extended)
Power Supply Voltage (measured in respect to GND)
-40
+1.71
+3.465
V
DC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD=1.8V ±5% , Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Symbol
VDD
VIH
Conditions
Min.
1.71
Typ.
Max.
1.89
Units
V
V
Input High Voltage, CLKIN
Input Low Voltage, CLKIN
Input High Voltage, 1G
Input Low Voltage, 1G
Output High Voltage
Output Low Voltage
Nominal Output Impedance
Input Capacitance
Operating Supply Current
5PB1102
Note 1
Note 1
0.7xVDD
VDD
VIL
0.3xVDD
VDD
V
VIH
1.6
1.4
V
VIL
0.6
V
VOH
VOL
ZO
IOH = -5 mA
IOL = 5 mA
V
0.4
V
50
5
pF
CIN
CLKIN, 1G pin
100MHz, No load, 25°C
100MHz, No load, 25°C
100MHz, No load, 25°C
100MHz, No load, 25°C
100MHz, No load, 25°C
8
5PB1104
12
16
21
25
5PB1106
IDD
mA
5PB1108
5PB1110
Notes: 1. Nominal switching threshold is VDD/2
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
4
MAY 13, 2016
5PB11xx DATASHEET
VDD=2.5 V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Symbol
VDD
VIH
Conditions
Min.
2.375
Typ.
Max.
Units
2.625
VDD
V
V
Input High Voltage, CLKIN
Input Low Voltage, CLKIN
Input High Voltage, 1G
Input Low Voltage, 1G
Output High Voltage
Output Low Voltage
Nominal Output Impedance
Input Capacitance
Operating Supply Current
5PB1102
Note 1
Note 1
0.7xVDD
VIL
0.3xVDD
VDD
V
VIH
1.8
1.9
V
VIL
0.7
V
VOH
VOL
ZO
IOH = -8 mA
IOL = 8 mA
V
0.5
V
50
5
pF
CIN
CLKIN, 1G pin
100MHz, No load, 25°C
100MHz, No load, 25°C
100MHz, No load, 25°C
100MHz, No load, 25°C
100MHz, No load, 25°C
10
15
22
28
33
5PB1104
5PB1106
IDD
mA
5PB1108
5PB1110
VDD=3.3 V ±5% , Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Symbol
VDD
VIH
Conditions
Min.
3.135
Typ.
Max.
3.465
VDD
Units
V
V
Input High Voltage, CLKIN
Input Low Voltage, CLKIN
Input High Voltage, 1G
Input Low Voltage, 1G
Output High Voltage
Output Low Voltage
Nominal Output Impedance
Input Capacitance
Operating Supply Current
5PB1102
Note 1
Note 1
0.7xVDD
VIL
0.3xVDD
VDD
V
VIH
2
V
VIL
0.8
V
VOH
VOL
ZO
IOH = -12 mA
IOL = 12 mA
2.4
V
0.7
V
50
5
pF
CIN
CLKIN, 1G pin
100MHz, No load, 25°C
100MHz, No load, 25°C
100MHz, No load, 25°C
100MHz, No load, 25°C
100MHz, No load, 25°C
12
20
25
35
40
5PB1104
5PB1106
IDD
mA
5PB1108
5PB1110
MAY 13, 2016
5
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
5PB11xx DATASHEET
AC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Input Frequency
Symbol
Conditions
Min. Typ. Max. Units
0
200
0.75
0.75
1.0
1.0
3
MHz
ns
Output Rise Time (2 pF load)
Output Fall Time (2 pF load)
Output Rise Time (5 pF load)
Output Fall Time (5 pF load)
Start-up Time
tOR
tOF
tOR
tOF
0.36V to 1.44V, CL=2 pF
0.5
0.5
0.8
0.8
1.44V to 0.36V, CL=2 pF
0.36V to 1.44V, CL=5 pF
1.44V to 0.36V, CL=5 pF
ns
ns
ns
tSTART-UP Part start-up time for valid outputs after VDD ramp-up
Note 1
ms
ns
Propagation Delay
1.9
2.2
0.05
50
Buffer Additive Phase Jitter, RMS
Output to Output Skew (5PB1102/04/06)
Output to Output Skew (5PB1108/10)
Device to Device Skew
156.25MHz, Integration Range: 12kHz-20MHz
Rising edges at VDD/2, Note 2
Rising edges at VDD/2, Note 2
Rising edges at VDD/2
ps
35
45
ps
65
ps
200
3
ps
Output Enable Time
tEN
CL < 5 pF
CL < 5 pF
cycles
cycles
Output Disable Time
tDIS
3
VDD = 2.5 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Input Frequency
Symbol
Conditions
Min. Typ. Max. Units
0
200
0.7
0.7
1.0
1.0
3
MHz
ns
Output Rise Time (2 pF load)
Output Fall Time (2 pF load)
Output Rise Time (5 pF load)
Output Fall Time (5 pF load)
Start-up Time
tOR
tOF
tOR
tOF
0.5V to 2.0V, CL=2 pF
0.4
0.4
2.0V to 0.5V, CL=2 pF
0.5V to 2.0V, CL=5 pF
2.0V to 0.5V, CL=5 pF
ns
0.75
0.75
ns
ns
tSTART-UP Part start-up time for valid outputs after VDD ramp-up
Note 1
ms
ns
Propagation Delay
2.4
2.9
0.05
50
Buffer Additive Phase Jitter, RMS
Output to Output Skew (5PB1102/04/06)
Output to Output Skew (5PB1108/10)
Device to Device Skew
156.25MHz, Integration Range: 12kHz-20MHz
Rising edges at VDD/2, Note 2
Rising edges at VDD/2, Note 2
Rising edges at VDD/2
ps
35
45
ps
65
ps
200
3
ps
Output Enable Time
tEN
CL < 5 pF
CL < 5 pF
cycles
cycles
Output Disable Time
tDIS
3
VDD = 3.3 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Input Frequency
Symbol
Conditions
Min. Typ. Max. Units
0
200
0.6
0.6
1.0
1.0
3
MHz
ns
Output Rise Time (2 pF load)
Output Fall Time (2 pF load)
Output Rise Time (5 pF load)
Output Fall Time (5 pF load)
Start-up Time
tOR
tOF
tOR
tOF
0.66V to 2.64V, CL=2 pF
0.45
0.45
0.7
2.64V to 0.66V, CL=2 pF
0.66V to 2.64V, CL= 5pF
2.64V to 0.66V, CL=5 pF
ns
ns
0.7
ns
tSTART-UP Part start-up time for valid outputs after VDD ramp-up
Note 1
ms
ns
Propagation Delay
2
2.4
0.05
50
Buffer Additive Phase Jitter, RMS
Output to Output Skew (5PB1102/04/06)
156.25MHz, Integration Range: 12kHz-20MHz
Rising edges at VDD/2, Note 2
ps
35
ps
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
6
MAY 13, 2016
5PB11xx DATASHEET
Parameter
Output to Output Skew (5PB1108/10)
Device to Device Skew
Symbol
Conditions
Rising edges at VDD/2, Note 2
Rising edges at VDD/2
CL < 5 pF
Min. Typ. Max. Units
45
65
200
3
ps
ps
Output Enable Time
tEN
cycles
cycles
Output Disable Time
tDIS
CL < 5 pF
3
Notes:
1. With rail to rail input clock
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.
Phase Noise Plots
Figure 2. 5PB11xx Output Phase Noise 70.9fs
(12kHz to 20MHz)
Figure 1. 5PB11xx Reference Phase Noise 58.9fs
(12kHz to 20MHz)
The phase noise plots above show the low Additive Jitter of the 5PB11xx high-performance buffer. With an integration range of
12kHz to 20MHz, the reference input has about 58.9fs of RMS phase jitter while the output of 5PB11xx has about 70.9fs of RMS
phase jitter. This results in a low Additive Phase Jitter of only 39fs.
Test Load and Circuit
50ohms
5 inche
s
CL = 5pF
MAY 13, 2016
7
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
5PB11xx DATASHEET
Marking Diagrams
IDT5PB11
08PGGI
YYWW$
IDT5PB11
06PGGI
YYWW$
YWW$
B11AAI
14-pin TSSOP
16-pin TSSOP
8-pin TSSOP
IDT5PB11
10PGGI
YYWW$
20-pin TSSOP
11AA
YW**
XXX
YWW$
110I
1106
Y**
1108
Y**
8-pin DFN
16-pin QFN
16-pin QFN
20-pin QFN
Notes:
1. “AA” denotes the last two digits of the part number for 8-pin TSSOP and DFN (e.g. 02, 04).
2. “**” is the lot sequence.
3. “XXX” denotes the last three characters of the Asm lot (20-pin QFN only).
4. “YYWW”, “YWW”, “YW”, or “Y” is the last digit(s) of the year and week that the part was assembled.
5. “$” denotes the mark code.
6. “G” after the two-letter package code denotes RoHS compliant package.
7. “I” denotes extended temperature range device.
8. Bottom marking: country of origin (TSSOP only).
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
8
MAY 13, 2016
5PB11xx DATASHEET
Package Outline and Package Dimensions (8-pin DFN, 2mm x 2mm Body, 0.5mm pitch)
MAY 13, 2016
9
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
5PB11xx DATASHEET
Package Outline and Package Dimensions, cont. (8-pin DFN, 2mm x 2mm Body, 0.5mm pitch)
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
10
MAY 13, 2016
5PB11xx DATASHEET
Package Outline and Package Dimensions (16-pin QFN, 2.5mm x 2.5mm Body, 0.4mm pitch)
MAY 13, 2016
11
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
5PB11xx DATASHEET
Package Outline and Package Dimensions, cont. (16-pin QFN, 2.5mm x 2.5mm Body, 0.4mm pitch)
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
12
MAY 13, 2016
5PB11xx DATASHEET
Package Outline and Package Dimensions (20-pin QFN, 3mm x 3mm Body, 0.4mm pitch)
MAY 13, 2016
13
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
5PB11xx DATASHEET
Package Outline and Package Dimensions, cont. (20-pin QFN, 3mm x 3mm Body, 0.4mm pitch)
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
14
MAY 13, 2016
5PB11xx DATASHEET
Package Outline and Package Dimensions (8-, 14-, 16-, 20-pin TSSOP)
MAY 13, 2016
15
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
5PB11xx DATASHEET
Package Outline and Package Dimensions, cont. (8-, 14-, 16-, 20-pin TSSOP)
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
16
MAY 13, 2016
5PB11xx DATASHEET
Package Outline and Package Dimensions, cont. (8-, 14-, 16-, 20-pin TSSOP)
MAY 13, 2016
17
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
5PB11xx DATASHEET
Ordering Information
Part / Order Number
5PB1102PGGI
5PB1102PGGI8
5PB1104PGGI
5PB1104PGGI8
5PB1106PGGI
5PB1106PGGI8
5PB1108PGGI
5PB1108PGGI8
5PB1110PGGI
5PB1110PGGI8
5PB1102CMGI
5PB1102CMGI8
5PB1104CMGI
5PB1104CMGI8
5PB1104CMGI/W
5PB1106CMGI
5PB1106CMGI8
5PB1108CMGI
5PB1108CMGI8
5PB1110NDGI
5PB1110NDGI8
Marking
Shipping Packaging
Tubes
Package
8-pin TSSOP
8-pin TSSOP
8-pin TSSOP
8-pin TSSOP
14-pin TSSOP
14-pin TSSOP
16-pin TSSOP
16-pin TSSOP
20-pin TSSOP
20-pin TSSOP
8-pin DFN
Temperature
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
-40 to +105 C
see page 8
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Cut Tape
Tape and Reel
Cut Tape
8-pin DFN
8-pin DFN
Tape and Reel
Tape and Reel
Cut Tape
8-pin DFN
8-pin DFN
16-pin QFN
16-pin QFN
16-pin QFN
16-pin QFN
20-pin QFN
20-pin QFN
Tape and Reel
Cut Tape
Tape and Reel
Tubes
Tape and Reel
“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
Revision History
Rev. Date
Originator
Description of Change
A
B
03/20/15
B. Chandhoke Initial release.
05/19/15
B. Chandhoke 1. Expanded Output Enable function text in General Description, and within the note
under "Output Logic Table".
2. Updated all "Buffer Additive Phase Jitter, RMS" conditions from 125MHz to 156.25MHz.
C
06/09/15
B. Chandhoke 1. Corrected typos in part numbers in DC Electrical Tables.
2. Updated existing Output Rise/Fall Time specs for 5pF load.
3. Added additional Output Rise/Fall specs for 2 pF load.
D
E
06/15/15
06/22/15
B. Chandhoke Fixed typos in Output Rise/Fall Time 5pF specs for CL conditions; should be 5pF; not 2pF.
B. Chandhoke Changed 3.3V Operating Voltage spec from 3.15 min to 3.135 min; 3.45 max to 3.465
max.
F
08/24/15
05/13/16
B. Chandhoke 1. Added 5PB1104CMGIW orderable part.
2. Updated Abs Max Ratings table for “Output Enable and All outputs” and “CLKIN”;
changed -0.5 V to -0.4 and added -0.4 to... respectively.
G
H.G.
Replace NDG20 POD drawing with latest version.
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
18
MAY 13, 2016
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Sales
Tech Support
email: clocks@idt.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
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