59920A-2SOC [IDT]
Clock Driver;
| 型号： | 59920A-2SOC |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver |
| 文件： | 总6页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW
IDT59920A
PLL CLOCK DRIVER
TURBOCLOCK™ JR.
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
Eightzerodelayoutputs
Selectablepositiveornegativeedge synchronization
Synchronousoutputenable
Outputfrequency:15MHzto100MHz
CMOSoutputs
3 skew grades:
IDT59920A-2:tSKEW0<250ps
IDT59920A-5:tSKEW0<500ps
IDT59920A-7:tSKEW0<750ps
3-level input for PLL range control
PLLbypass forDCtesting
Externalfeedback,internalloopfilter
46mAIOL highdriveoutputs
LowJitter:<200pspeak-to-peak
Outputsdrive50Ωterminatedlines
PincompatiblewithCypressCY7B9920
AvailableinSOICPackage
The IDT59920A is a high fanout phase lock loop clock driver in-
tended for high performance computing and data-communications appli-
cations. The IDT59920A has CMOS outputs.
The IDT59920A maintains Cypress CY7B9920 compatibility while
providing two additional features: Synchronous Output Enable (GND/
sOE), and Positive/Negative Edge Synchronization (VDDQ/PE). When
the GND/sOE pin is held low, all outputs are synchronously enabled
(CY7B9920 compatibility). However, if GND/sOE is held high, all out-
puts except Q2 and Q3 are synchronously disabled.
•
•
•
•
•
•
•
•
Furthermore, when the VDDQ/PE is held high, all outputs are synchro-
nized with the positive edge of the REF clock input (CY7B9920 compat-
ibility). When VDDQ/PE is held low, all outputs are synchronized with the
negative edge of REF.
The FB signal is compared with the input REF signal at the phase
detector in order to drive the VCO. Phase differences cause the VCO of
the PLL to adjust upwards or downwards accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
FUNCTIONALBLOCKDIAGRAM
VDDQ/PE
GND/sOE
Q
0
Q1
Q2
Q
Q
Q
Q
3
4
5
6
FB
PLL
REF
FS
Q7
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AUGUST 2000
1
c
1999 Integrated Device Technology, Inc.
DSC - 5846
IDT59920A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
LOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.
ABSOLUTE MAXIMUM RATINGS (1)
PINCONFIGURATION
Symbol
Rating
Max.
Unit
Supply Voltage to Ground
–0.5 to +7
V
VI
DC Input Voltage
–0.5 to +7
530
V
1
2
3
GND
TEST
NC
REF
24
23
22
21
20
19
18
17
16
15
14
13
Maximum Power Dissipation (TA = 85°C)
Storage Temperature Range
mW
°C
V
DDQ
FS
TSTG
–65 to +150
GND/sOE
VDDN
Q7
4
5
NOTE:
NC
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
VDDQ/PE
SO24-2
6
VDDN
Q0
7
Q6
8
GND
Q5
Q1
9
GND
Q2
CAPACITANCE (T = 25 C, f = 1MHz, V = 0V)
Parameter
°
A
IN
10
11
12
Q4
VDDN
FB
Q3
Description
Input Capacitance
Typ. Max. Unit
CIN
5
7
pF
VDDN
NOTE:
1. Capacitance applies to all inputs except TEST and FS. It is
characterized but not production tested.
SOIC
TOP VIEW
PIN DESCRIPTION
Pin Name
Type
Description
REF
IN
Reference Clock Input
Feedback Input
FB
IN
TEST (1)
GND/ sOE (1)
IN
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation.
IN
Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as
the feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation.
VDDQ/PE
FS (2)
IN
IN
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.
Frequency range select. 3 level input.
FS = GND: 15 to 35MHz.
FS = MID (or open): 25 to 60MHz
FS = VDD: 40 to 85MHz
8 clock output
Q0 - Q7
VDDN
OUT
PWR
PWR
PWR
Power supply for output buffers
VDDQ
Power supply for phase locked loop and other internal circuitry
Ground
GND
NOTES:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active.
2. This input is wired to VDD, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL
may require an additional lock time before all data sheet limits are achieved.
2
IDT59920A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
LOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.
RECOMMENDED OPERATING RANGE
IDT59920A-5, -7
(Industrial)
IDT59920A-2
(Commercial)
Symbol
Description
Power Supply Voltage
Ambient Operating Temperature
Min.
Max.
Min.
Max.
Unit
VDD
4.5
5.5
4.75
5.25
V
TA
-40
+85
0
+70
°C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Input HIGH Voltage
Conditions
Min.
Max.
Unit
VIH
Guaranteed Logic HIGH (REF, FB Inputs Only)
VDD−1.35
—
V
V
VIL
Input LOW Voltage
Input HIGH Voltage (1)
Input MID Voltage (1)
Input LOW Voltage (1)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
—
VDD−1
VDD/2−0.5
—
1.35
VIHH
VIMM
VILL
IIN
—
V
3-Level Inputs Only
VDD/2+0.5
V
3-Level Inputs Only
1
V
Input Leakage Current
(REF, FB Inputs Only)
VIN = VDD or GND
VDD = Max.
—
±5
µA
VIN = VDD
HIGH Level
MID Level
LOW Level
—
—
±200
±50
±200
±100
±100
—
I3
3-Level Input DC Current (TEST, FS)
VIN = VDD/2
µA
VIN = GND
—
IPU
Input Pull-Up Current (VDDQ/PE)
Input Pull-Down Current (GND/sOE)
Output HIGH Voltage
VDD = Max., VIN = GND
VDD = Max., VIN = VDD
VDD = Min., IOH = −16mA
VDD = Min., IOH = −40mA
VDD = Min., IOL = 46mA
VDD = Max., VO = GND
—
µA
µA
V
IPD
—
VOH
—
VDD−0.75
—
—
V
VOL
IOS
Output LOW Voltage
0.45
N/A
V
Output Short Circuit Current (2)
—
mA
NOTES:
1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are
switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are
achieved.
2. Outputs are not to be shorted.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
Typ.
Max.
Unit
IDDQ
Quiescent Power Supply Current
VDD = Max., TEST = MID, REF = LOW,
GND/sOE = LOW, All outputs unloaded
10
40
mA
∆IDD
IDDD
ITOT
Power Supply Current per Input HIGH
Dynamic Power Supply Current per Output
Total Power Supply Current
V
DD = Max., V = 3.4V
0.4
100
53
1.5
160
—
mA
µA/MHz
mA
IN
VDD = Max., CL = 0pF
VDD = 5V, FREF = 25MHz, CL = 240pF (1)
VDD = 5V, FREF = 33MHz, CL = 240pF (1)
VDD = 5V, FREF = 66MHz, CL = 240pF (1)
63
—
mA
117
—
mA
NOTE:
1. For eight outputs, each loaded with 30pF.
3
IDT59920A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
LOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.
INPUT TIMING REQUIREMENTS
Symbol
Description (1)
Min.
Max.
Unit
tR, tF
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
Input duty cycle
—
10
ns/V
tPWC
DH
3
—
90
ns
%
10
15
REF
Reference Clock Input
100
MHz
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT59920A-2
Typ. Max.
IDT59920A-5
IDT59920A-7
Symbol
Parameter
REF Frequency Range
Min.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
FREF
FS = LOW
FS = MID
FS = HIGH
15
—
—
—
—
—
0.1
—
0
35
60
15
—
35
15
—
35
MHz
25
40
25
40
—
—
—
—
0.25
—
0
60
100
—
25
40
—
—
—
—
0.3
—
0
60
100
—
100
—
tRPWH
tRPWL
tSKEW0
tDEV
REF Pulse Width HIGH (1,8)
REF Pulse Width LOW (1,8)
3
3
3
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
3
—
3
—
3
—
Zero Output Skew (All Outputs) (1,3,4)
Device-to-Device Skew (1,2,5)
REF Input to FB Propagation Delay (1,7)
Output Duty Cycle Variation from 50% (1)
Output Rise Time (1)
—
0.25
0.75
0.25
1.2
2.5
2.5
0.5
25
—
—
−0.5
−1.2
0.5
0.5
—
—
—
0.5
1.25
0.5
1.2
3.5
3.5
0.5
25
—
—
−0.7
−1.5
0.5
0.5
—
—
—
0.75
1.65
0.7
1.5
5
—
tPD
−0.25
−1.2
0.5
0.5
—
tODCV
tORISE
tOFALL
tLOCK
tJR
0
0
0
2
2
3
Output Fall Time (1)
2
2
3
5
PLL Lock Time (1,6)
—
—
—
—
—
—
—
—
—
0.5
25
Cycle-to-Cycle Output Jitter (1) RMS
—
Peak-to-Peak
—
200
200
200
NOTES:
1. All timing and jitter tolerances apply for FNOM ≥25MHz. Guaranteed by design and characterization, not subject to production testing.
2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.
3. tSKEW is the skew between all outputs. See AC Test Loads.
4. For IDT59920A-2, tSKEW0 is measured with CL = 0pF; for CL = 30pF, tSKEW0 = 0.45ns max.
5. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow, etc.)
6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating
limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
7. tPD is measured with REF input rise and fall times (from 0.2VDD to 0.8VDD) of 1.5ns.
8. Refer to Input Timing Requirements for more detail.
4
IDT59920A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
LOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.
AC TEST LOADS AND WAVEFORMS
≤ 1.5ns
≤ 1.5ns
VDD
DD
V
80%
DD
Vth = 0.5V
100Ω
20%
0V
Output
100Ω
CMOS INPUT TEST WAVEFORM
CL
CL = 50pF (CL = 30pF for -2 and -5 devices)
TESTLOAD
tOFALL
tORISE
DD
0.8 V
0.2 V
DD
CMOSOUTPUTWAVEFORM
AC TIMING DIAGRAM
tREF
tRPWL
tRPW H
REF
tPD
tODCV
tODCV
FB
tJR
Q
tSKEW
tSKEW
OTHER Q
NOTES:
Skew: The time between the earliest and the latest output transition among all outputs when all are loaded with 50pF (30pF for -2 and -5)
and terminated with VDD/2.
tSKEW: The skew between all outputs.
tDEV:
The output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow,
etc.)
tODCV: The deviation of the output from a 50% duty cycle.
tORISE and tOFALL are measured between 0.2VDD and 0.8VDD.
tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal
operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within
specified limits.
5
IDT59920A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
LOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.
ORDERINGINFORMATION
XXXXX
XX
X
IDT
Package Process
Device Type
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
C
I
SO
Small Outline IC (300-mil) (SO24-2)
Low Skew PLL Clock Driver TurboClock Jr.
59920A-2
59920A-5
59920A-7
CORPORATE HEADQUARTERS
for SALES:
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800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Turboclock is a registered trademark of Integrated Device Technology, Inc.
6
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