552-02SPGGI8 [IDT]
Low Skew 2-input MUX and 1 to 8 Clock Buffer;
| 型号： | 552-02SPGGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew 2-input MUX and 1 to 8 Clock Buffer |
| 文件： | 总12页 (文件大小：377K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew 2-input MUX and 1 to 8 Clock Buffer
552-02S
DATASHEET
Description
Features
The 552-02S is a low skew, single-input to eight- output clock
buffer. The device offers a dual input with pin select for
switching between two clock sources. It has best in class
Additive Phase Jitter of sub 50fsec
• Low RMS Additive Phase Jitter: 50fs
• Low output skew: 50ps
• Operating Voltages of 1.8V to 3.3V
• Packaged in 16-pin TSSOP and 16-pin VFQFN, Pb-free
• Input clock multiplexer simplifies clock selection
• Output Enable pin tri-states outputs
• Input/Output clock frequency up to 200 MHz
• Low power CMOS technology
IDT makes many non-PLL and PLL based low skew output
devices as well as Zero Delay Buffers to synchronize clocks.
Contact us for all of your clocking needs.
• 3.3V tolerant inputs
• Extended temperature (-40°C to +105°C)
Block Diagram
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
INA
INB
1
0
SELA
OE
552-02S APRIL 18, 2017
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©2017 Integrated Device Technology, Inc.
552-02S DATASHEET
Pin Assignments
OE
VDD
Q0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SELA
VDD
Q7
16 15 14 13
OE
VDD
Q0
1
2
Q5
12
11
Q1
Q6
Q4
Q2
Q5
GND
INA
3
4
10
9
Q3
Q4
Q1
5
6
7
8
GND
INB
GND
INA
16 Pin TSSOP
16-pin VFQFN
Input Source Select
SELA
Input
INB
0
1
INA
Pin Descriptions
Pin
Pin
Pin
Pin Description
Number
Name
Type
1
2
OE
VDD
Q0
Input
Output Enable. Tri-states outputs when low. Internal pull-up resistor.
Connect to +1.8V, +2.5V or +3.3V. Must be the same as pin 15.
Power
3
Output Clock Output 0.
Output Clock Output 1.
Output Clock Output 2.
Output Clock Output 3.
4
Q1
5
Q2
6
Q3
7
GND
INB
INA
GND
Q4
Power
Input
Connect to ground.
8
Clock Input B. 3.3V tolerant.
Clock Input A. 3.3V tolerant.
Connect to ground.
9
Input
10
11
12
13
14
15
16
Power
Output Clock Output 4.
Output Clock Output 5.
Output Clock Output 6.
Output Clock Output 7.
Q5
Q6
Q7
VDD
SELA
Power
Input
Connect to +1.8V, +2.5V or +3.3V. Must be the same as pin 2.
Selects either INA or INB. Internal pull-up resistor.
External Components
A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01F should be
connected between VDD on pin 2 and GND on pin 7, and between VDD on pin 15 and GND on pin 10, as close to the device
as possible. A 33 series terminating resistor should be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skews that the 552-02S is capable of, careful attention must be paid to board layout. Essentially, all 8
outputs must have identical terminations, identical loads, and identical trace geometries. If they do not, the output skew will be
degraded. For example, using a 30series termination on one output (with 33 on the others) will cause at least 15ps of skew.
LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER
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APRIL 18, 2017
552-02S DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 552-02S. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
3.465V
-0.5 V to 3.465V
-40 to +105°C
-65 to +150 C
175 C
Ambient Operating Temperature, Extended
Storage Temperature
Junction Temperature
Soldering Temperature
260 C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
Units
C
Ambient Operating Temperature, Extended
Power Supply Voltage (measured in respect to GND)
-40
–
+105
+1.71
+3.465
V
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LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER
552-02S DATASHEET
DC Electrical Characteristics
VDD=1.8 V ±5%, Ambient temperature -40°C to +105°C, unless stated otherwise
Parameter
Operating Voltage
Symbol
VDD
VIH
Conditions
Min.
1.71
Typ.
Max.
1.89
Units
V
V
Input High Voltage, INA, INB
Input Low Voltage, INA, INB
Input High Voltage, OE, SELA
Input Low Voltage, OE, SELA
Output High Voltage
Note 1
0.7xVDD
1.89
VIL
Note 1
0.3xVDD
VDD
V
VIH
0.7xVDD
1.3
V
VIL
0.3xVDD
V
VOH
VOL
IDD
IOH = -10 mA
V
Output Low Voltage
IOL = 10 mA
0.35
V
Operating Supply Current
No load, 135 MHz
32
mA
VDD=2.5 V ±5%, Ambient temperature -40°C to +105°C, unless stated otherwise
Parameter
Operating Voltage
Symbol
VDD
VIH
Conditions
Min.
2.375
Typ.
Max.
2.625
Units
V
V
Input High Voltage, INA, INB
Input Low Voltage, INA, INB
Input High Voltage, OE, SELA
Input Low Voltage, OE, SELA
Output High Voltage
Note 1
0.7xVDD
2.625
VIL
Note 1
0.3xVDD
VDD
V
VIH
0.7xVDD
1.8
V
VIL
0.3xVDD
V
VOH
VOL
IDD
IOH = -16 mA
V
Output Low Voltage
IOL = 16 mA
0.5
V
Operating Supply Current
No load, 135 MHz
43
mA
VDD=3.3 V ±5%, Ambient temperature -40°C to +105°C, unless stated otherwise
Parameter
Operating Voltage
Symbol
VDD
VIH
Conditions
Min.
3.135
Typ.
Max.
3.465
Units
V
V
Input High Voltage, INA, INB
Input Low Voltage, INA, INB
Input High Voltage, OE, SELA
Input Low Voltage, OE, SELA
Output High Voltage
Note 1
0.7xVDD
3.465
VIL
Note 1
0.3xVDD
VDD
V
VIH
0.7xVDD
2.2
V
VIL
0.3xVDD
V
VOH
VOL
IDD
IOH = -25 mA
V
Output Low Voltage
IOH = 25 mA
0.7
V
Operating Supply Current
No load, 135 MHz
55
mA
LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER
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APRIL 18, 2017
552-02S DATASHEET
AC Electrical Characteristics
VDD = 1.8V ±5%, Ambient Temperature -40°C to +105°C, unless stated otherwise
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ.
Max.
200
1.5
1.5
2
Units
MHz
ns
0
Output Rise Time
Output Fall Time
Start-up Time
tOR
tOF
0.36 to 1.44 V, CL=5 pF
1.44 to 0.36 V, CL=5 pF
1
1
ns
tSTART-UP Part start-up time for valid outputs after VDD
ramp-up
ms
Propagation Delay
Note 1
135MHz
2
2.5
50
0
3
ns
ps
ps
ps
Buffer Additive Phase Jitter, RMS
Output to output skew
125MHz, Integration Range: 12KHz-20MHz
Rising edges at VDD/2
65
65
50
Note 2
Note 3
Input A to Input B skew
0
VDD = 2.5V ±5%, Ambient Temperature -40°C to +105°C, unless stated otherwise
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ.
Max.
200
1.0
1.0
2
Units
MHz
ns
0
Output Rise Time
Output Fall Time
Start-up Time
tOR
tOF
0.5 to 2.0 V, CL=5 pF
2.0 to 0.5 V, CL=5 pF
0.6
0.6
ns
tSTART-UP Part start-up time for valid outputs after VDD
ramp-up
ms
Propagation Delay
Note 1
135MHz
2
2.7
50
0
3.5
65
65
50
ns
ps
ps
ps
Buffer Additive Phase Jitter, RMS
Output to output skew
125MHz, Integration Range: 12KHz-20MHz
Rising edges at VDD/2
Note 2
Note 3
Input A to Input B skew
0
VDD = 3.3V ±5%, Ambient Temperature -40°C to +105°C, unless stated otherwise
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ.
Max.
200
1.0
1.0
2
Units
MHz
ns
0
Output Rise Time
Output Fall Time
Start-up Time
tOR
tOF
0.66 to 2.64 V, CL=5 pF
2.64 to 0.66 V, CL=5 pF
0.6
0.6
ns
tSTART-UP Part start-up time for valid outputs after VDD
ramp-up
ms
Propagation Delay
Note 1
135MHz
2
2.5
50
0
3
ns
ps
ps
ps
Buffer Additive Phase Jitter, RMS
Output to output skew
125MHz, Integration Range: 12KHz-20MHz
Rising edges at VDD/2
65
65
50
Note 2
Note 3
Input A to Input B skew
0
Notes:
1. With rail-to-rail input clock.
2. Between any two outputs with equal loading.
3. Propagation delay matching through the part.
4. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.
APRIL 18, 2017
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LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER
552-02S DATASHEET
Package Outline and Dimensions (16-pin VFQFN)
LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER
6
APRIL 18, 2017
552-02S DATASHEET
Package Outline and Dimensions, cont. (16-pin VFQFN)
APRIL 18, 2017
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LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER
552-02S DATASHEET
Package Outline and Dimensions (16-pin TSSOP)
LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER
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APRIL 18, 2017
552-02S DATASHEET
Package Outline and Dimensions (16-pin TSSOP), cont.
APRIL 18, 2017
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LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER
552-02S DATASHEET
Package Outline and Dimensions (16-pin TSSOP), cont.
LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER
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APRIL 18, 2017
552-02S DATASHEET
Ordering Information
Part / Order Number
552-02SPGGI
Marking
Shipping Packaging
Tubes
Package
Temperature
16-pin TSSOP
16-pin TSSOP
16-pin VFQFN
16-pin VFQFN
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
Tape and Reel
Tubes
552-02SPGGI8
552-02SCMGI
TBD
Tape and Reel
552-02SCMGI8
“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
Marking Diagrams
IDT552-0
2SPGGI
02SI
YYWW$
Y**
LOT
16-pin TSSOP
16-pin QFN
Notes:
1. “**” is the lot sequence.
2. “YYWW” or “Y” is the last digit(s) of the year and week that the part was assembled.
3. “$” denotes the mark code.
4. “LOT” denotes lot number.
5. “G” after the two-letter package code denotes RoHS compliant package.
6. “I” denotes extended temperature range device.
7. Bottom marking: country of origin (TSSOP only).
Revision History
Rev.
Date
Originator Description of Change
B
04/18/17
C.P.
1. Replaced package outline drawings with latest CMG16 and PGG16 versions.
2. Updated legal disclaimer.
A
07/11/16
H.G.
Release to final.
APRIL 18, 2017
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LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
Sales
Tech Support
www.idt.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when
installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products
for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under
intellectual property rights of IDT or any third parties.
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Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.
552-02S APRIL 18, 2017
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©2017 Integrated Device Technology, Inc.
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