332M-49LFT [IDT]
Clock Generator, 133MHz, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8;
| 型号： | 332M-49LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 133MHz, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8 光电二极管 |
| 文件： | 总6页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS332-49
Dual Output Clock Synthesizer
Description
Features
The ICS332-49 is a low-cost frequency generator that
is factory programmable. Using analog/digital
Phase-Locked-Loop (PLL) techniques, the device
accepts a 16.384 MHz clock input to produce output
clocks of 45 MHz and 133 MHz. In one selection the 45
MHz clock has center spread spectrum of 1.0%.
• 8 pin SOIC package – Pb-free, RoHS compliant
• Input clock frequency of 16.384 MHz
• Two output clocks of 45 MHz and 133 MHz
• Spread spectrum enabled at +1.0% (center)
• Duty cycle of 45/55
• Operating voltage of 3.3 V
• Advanced, low power CMOS process
The device also has a power down feature that
tri-states the clock outputs and turns off the PLLs when
the PDTS pin is taken low.
Block Diagram
OTP
PLL
ROM
with PLL
Divider
Values
SEL
45M
Clock
Synthesis
and
Control
Circuitry
16.384 MHz Crystal
X1
133M
Crystal
Oscillator
X2
Optional crystal capacitors
PDTS (both outputs and PLL)
MDS 332-49 E
1
Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
ICS332-49
Pin Assignment
Output Clock Selection Table
X1
VDD
8
7
6
5
1
2
3
4
X2
SEL CLK1 (MHz)
CLK2 (MHz)
Spread on
PDTS
SEL
CLK1
0
1
45
45
133
133
-
GND
CLK1
1.0%
CLK2
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
Connect this pin to a 16.384 MHz crystal input.
1
2
3
4
X1
XI
VDD
GND
CLK1
Power Connect to +3.3 V.
Power Connect to ground.
Output 45 MHz clock output with selectable 1.0% spread spectrum. Weak
internal pull-down when tri-state.
5
6
7
CLK2
SEL
Output 133 MHz clock output. Weak internal pull-down when tri-state.
Input
Input
Select pin for frequency selection on CLK1 and CLK2. Internal pull-up.
PDTS
Powers down entire chip. Tri-states CLK outputs when low. Internal
pull-up.
8
X2
XO
Connect this pin to a 16.384 MHz crystal input.
External Components
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ωresistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS332-49 must be isolated from system power supply
noise to perform optimally.
●
ICS332-49
Dual Output Clock Synthesizer
must be connected from each of the pins X1 and X2 to
ground.
bead and bulk decoupling from the device is less
critical.
The value (in pF) of these crystal caps should equal
(CL -6 pF)*2. In this equation, CL= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2 = 20].
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33Ωseries termination resistor
(if needed) should be placed close to the clock output.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS332-49. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS332-49. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
125°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
MDS 332-49 E
3
Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
ICS332-49
Dual Output Clock Synthesizer
Recommended Operation Conditions
Parameter
Min.
0
Typ.
Max.
+70
Units
° C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
+3.15
+3.3
+3.45
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±±%, Ambient Temperature 0 to +70°C
Parameter
Symbol
VDD
Conditions
Min.
Typ.
3.3
35
Max. Units
Operating Voltage
3.15
3.45
V
mA
µA
V
Supply Current
IDD
No load, PDTS=1
No load, PDTS=0
21
Input High Voltage, PDTS
Input Low Voltage, PDTS
Input High Voltage, SEL
Input Low Voltage, SEL
Input High Voltage, ICLK
Input Low Voltage, ICLK
VIH
VIL
VDD-0.5
2
0.4
0.4
V
VIH
VIL
V
V
VDD/2+1
VIH
VIL
V
VDD/2-1
V
Output High Voltage (CMOS
High)
VOH
IOH = -8 mA
VDD-0.4
2.4
V
Output High Voltage
VOH
VOL
IOS
IOH = -12 mA
IOL = 12 mA
V
V
Output Low Voltage
0.4
Short Circuit Current
Internal Pull-up Resistor
Internal Pull-down Resistor
70
360
510
mA
kΩ
kΩ
RPU
RPD
MDS 332-49 E
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Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
ICS332-49
Dual Output Clock Synthesizer
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±±%, Ambient Temperature 0 to +70° C
Parameter
Symbol
fIN
Conditions
Min.
Typ.
16.384
1.3
Max. Units
Input Frequency
MHz
ns
Output Rise Time
Output Fall Time
tOR
0.8 to 2.0 V, Note 1
2.0 to 0.8 V, Note 1
tOF
0.9
ns
Duty Cycle
40
50
60
%
Cycle Jitter (short term jitter)
tja
Peak to peak, 52M no
spread and 120M CLKs
150
ps
Output Frequency Synthesis
Error
45M clock
-2
-4
ppm
ppm
Output Frequency Synthesis
Error
133M clock
Output Enable Time
Output Disable Time
tOE
tOD
PDTS high to output on
PDTS low to tri-state
250
200
µs
µs
Notes:
1. Measured with a 15 pF load.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
Still air
150
140
120
40
° C/W
° C/W
° C/W
° C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
θ
MDS 332-49 E
5
Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
ICS332-49
Dual Output Clock Synthesizer
Package Outline and Package Dimensions (8-pin SOIC, 1±0 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
8
Symbol
Min
1.35
0.10
0.33
0.19
4.80
3.80
Max
1.75
0.25
0.51
0.25
5.00
4.00
Min
Max
A
A1
B
C
D
E
e
.0532
.0040
.013
.0688
.0098
.020
E
H
.0075
.1890
.1497
.0098
.1968
.1574
INDEX
AREA
1.27 BASIC
0.050 BASIC
1
2
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
.2284
.010
.016
0°
.2440
.020
.050
8°
D
L
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
332M-49LF
Marking
332M49L
332M49L
Shipping Packaging
Tubes
Package
8-pin SOIC
8-pin SOIC
Temperature
0 to +70° C
0 to +70° C
332M-49LFT
Tape and Reel
“LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or
critical medical instruments.
MDS 332-49 E
6
Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
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