307M-02I [IDT]
Clock Generator, 200MHz, PDSO16, 0.150 INCH, SOIC-16;
| 型号： | 307M-02I |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 200MHz, PDSO16, 0.150 INCH, SOIC-16 光电二极管 |
| 文件： | 总10页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
SERIALLY PROGRAMMABLE CLOCK SOURCE
ICS307-01/-02
Description
Features
The ICS307-01 and ICS307-02 are versatile serially
programmable clock sources which take up very little
board space. They can generate any frequency from 6
to 200 MHz and have a second configurable output.
The outputs can be reprogrammed on the fly and will
lock to a new frequency in 10 ms or less. Smooth
transitions (in which the clock duty cycle remains near
50%) are guaranteed if the output divider is not
changed.
• Packaged in 16-pin (150 mil wide) SOIC
• ICS307M-02 and -02I available in Pb (lead) free
package
• Highly accurate frequency generation
• Serially programmable: user determines the output
frequency via a 3 wire interface
• Eliminates need for custom quartz
• Input crystal frequency of 5 - 27 MHz
• Output clock frequencies up to 200 MHz
• Power down tri-state mode
The devices includes a PDTS pin which tri-states the
output clocks and powers down the entire chip.
The ICS307-02 features a default clock output at
start-up and is recommended for all new designs.
• Very low jitter
• Operating voltage of 3.3 V or 5 V
• 25 mA drive capability at TTL levels
• Industrial temperature version available
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
For applications which require defined input to output
skew, use the ICS527-01.
Block Diagram
VDD
TTL
V8:V0
9
2
3
2
SCLK
DATA
C1:C0
S2:S0
F1:F0
Shift
Register
STROBE
VCO
Divider
7
R6:R7
CLK1
X1/ICLK
Phase Comparator,
Charge Pump, and
Loop Filter
Crystal
Oscillator
Reference
Divider
Output
Divider
VCO
PDTS
CLK2
Crystal or
clock input
Function
Select
X2
3
3
Optional crystal capacitors
S2:S0
F1:F0
GND
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
1
ICS307-01/-02 REV H 090209
ICS307-01/-02
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Pin Assignment
X1/ICLK
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
NC
VDD
NC
NC
PDTS
DATA
CLK1
NC
GND
CLK2
NC
SCLK
STROBE
16 pin (150 mil) SOIC
Pin Descriptions
Pin
Pin
Pin
Pin Description
Number
Name
Type
Crystal connection (REF frequency). Connect to a parallel resonant crystal or an
input clock.
1
2
X1/ICLK
NC
XI
-
No connect. Do not connect anything to this pin.
Connect to 3.3 V or 5 V.
3
VDD
Power
-
4
NC
No connect. Do not connect anything to this pin.
Connect to ground.
5
GND
CLK2
NC
Power
Output
-
6
Output clock 2, determined by F0 - F1. Can be reference, REF/2, CLK1/2 , or off.
No connect. Do not connect anything to this pin.
Serial clock. See timing diagram.
7
8
SCLK
STROBE
NC
Input
Input
-
9
Strobe to load data. See timing diagram.
10
11
12
No connect. Do not connect anything to this pin.
Output clock 1, determined by R0 - R6, V0 - V8, S0 - S2, and input frequency.
Data input. Serial input for three words which set the output clock(s).
CLK1
DATA
Output
Input
Powers down entire chip, tri states CLK1 and CLK2 outputs when low. Internal
pull-up.
13
14
15
PDTS
NC
Input
-
-
No connect. Do not connect anything to this pin.
No connect. Do not connect anything to this pin.
NC
Input crystal connection. Connect to a crystal or leave unconnected for clock
input.
16
X2
XO
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
2
ICS307-01/-02 REV H 090209
ICS307-01/-02
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Determining the Output Frequency
On power-up, the ICS307-01 on-chip registers can have
random values so almost any frequency may be output
from the part. CLK1 will always have some clock signal
present, but CLK2 could possibly be OFF (low).
And for the industrial temperature range:
VDW + 8
RDW + 2
The ICS307-02 on-chip registers are initially configured
to provide a x1 output clock on both the CLK1 and CLK2
outputs. The output frequency will be the same as the
input clock or crystal. This is useful if the ICS307 will
provide the initial system clock at power-up. Since this
feature is an advantage in most systems, the
60MHz < InputFrequency ⋅ 2 ⋅ ------------------------ < 3 60 M H z
Input Frequency
200kHz < ------------------------------------------
RDW + 2
ICS307-02 is recommended for new designs.
With programming, the user has full control in changing
the desired output frequency to any value over the
range shown in Table 1 on page 4. The output of the
ICS307 can be determined by the following equation:
To determine the best combination of VCO, reference,
and output dividers, see the online calculator at
www.idt.com or contact IDT by sending an e-mail to
ics-mk@icst.com with the desired input crystal or clock
and the desired output frequency.
VDW + 8
(RDW + 2) ⋅ OD
---------------------------------------------
CLK1Frequency = InputFrequency ⋅ 2 ⋅
Where:
VCO Divider Word (VDW) = 4 to 511 (0, 1, 2, 3
are not permitted)
Reference Divider Word (RDW) = 1 to 127 (0 is
not permitted)
Output Divider = values on page 4
The following operating ranges should be observed. For
the commercial temperature range:
VDW + 8
55MHz < InputFrequency ⋅ 2 ⋅ ------------------------ < 4 00 M H z
RDW + 2
InputFrequency
---------------------------------------------
200kHz <
RDW + 2
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
3
ICS307-01/-02 REV H 090209
ICS307-01/-02
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Setting the Device Characteristics
The tables below show the settings which can be configured, as well as the VCO and Reference dividers.
Table 1. Output Divide and Maximum Output Frequency
S2 S1 S0
CLK1 Output
Divide
Max. Frequency
5 V or 3.3 V (MHz)
Max. Frequency
Industrial Temp. Version
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10
2
40
200
50
36
180
45
8
4
100
80
90
5
72
7
55
50
3
135
67
120
60
6
Table 2. CLK2 Output
F1 F0
CLK2
REF
0
0
1
1
0
1
0
1
F
REF/2
OFF (Low)
F
CLK1/2
Table 3. Output Duty Cycle Configuration
TTL
0
Duty Cycle Measured At
Recommended VDD
1.4 V
5 V
1
VDD/2
3.3 V
Note: The TTL bit optimizes the duty cycle at different VDD. When VDD is 5 V, set to 0 for a near-50% duty
cycle with TTL levels. When VDD is 3.3 V, set this bit to 1 so the 50% duty cycle is achieved at VDD/2.
Table 4. Crystal Load Capacitance
C1
0
C0
0
VDD = 5V
VDD = 3.3V
22.1 - 0.094 f
22.9 - 0.108 f
23.5 - 0.120 f
24.2 - 0.135 f
22.3 - 0.083 f
23.1 - 0.093 f
23.7 - 0.106 f
24.4 - 0.120 f
0
1
1
0
1
1
Note: f is the crystal frequency in MHz between 10 and 27 MHz. Effective load capacitance will be higher
for crystal frequencies lower than 10 MHz. If a clock input is used, set C1 = 0 and C0 = 0.
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
4
ICS307-01/-02 REV H 090209
ICS307-01/-02
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Bypass Mode
If R6:0 is programmed to 0000000, the PLL is powered down and bypassed; the reference frequency will
come from both CLK1 and CLK2. It is possible to generate glitches going into and out of this mode.
Configuring the ICS307
The ICS307 can be programmed to set the output functions and frequencies. The three data bytes are
written in DATA pin in this order:
TTL
C1 C0
F1
F0
S2 S1 S0
V8 V7 V6 V5 V4 V3 V2 V1
V0 R6 R5 R4 R3 R2 R1 R0
MSB
LSB
MSB
LSB
MSB
LSB
C1 is loaded into the port first and R0 last.
R6:R0 Reference Divder Word (RDW)
V8:V0 VCO Divider Word (VDW)
S2:S0 Output Divider Select (OD)
F1:F0 Function of CLK2 Output
TTL
Duty Cycle Settings
C1:C0 Internal Load Capacitance for Crystal
The ICS307 can be reprogrammed at any time during operation. If R6:0, V8:0, TTL, or C1:0 are changed, the
frequency will transition smoothly to the new value over about 1 ms, without glitches or short cycles. If S2:0 is
changed, it is possible to generate glitches on CLK1 and also on CLK2 for F1:0 = 1 1.
Changing F1:0 will generate glitches on CLK2.
Power up default values for ICS307-02
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
The input frequency will come from both outputs.
A warning about using the default configuration with input frequencies lower than 13.75 MHz
The VCO will run only as low as its minimum frequency, which is guaranteed to be no more than 55 MHz.
So, in the powerup default condition, the PLL is guaranteed to lock to the input frequency down to 55/4 =
13.75 MHz. However, the part will typically run much slower. The typical minimum VCO frequency is about
30 - 40 MHz, depending on voltage, temperature, and lot variation; so in the powerup default setting, the
CLK2 output will be a minimum of 7.5 - 10 MHz even if the input frequency is lower than that. The output is
not locked to the reference input and so the frequency is not very stable and the phase noise is higher. In
this condition, the CLK2 output will accurately provide the reference frequency down to 0 Hz because this
signal path bypasses the PLL.
Power-down Mode
When the PDTS pin is pulled low, the chip will enter the power-down mode, where the output clocks are
tri-stated and the rest of the chip is powered down. The chip can be programmed during power-down
mode, however, if the chip is programmed during operation and enters power-down mode, the registers will
return to their settings and not reset when exiting power-down mode (PDTS pin is pulled high).
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
5
ICS307-01/-02 REV H 090209
ICS307-01/-02
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Programming Example
To generate 66.66 MHz from a 14.31818 MHz input, the RDW should be 59, the VDW should be 276, and
the Output Divide is 2. Selecting the minimum internal load capacitance, CMOS duty cycle, and CLK2 to be
OFF means that the following three bytes are sent to the ICS307:
00110001
Byte 1
10001010
Byte 2
00111011
Byte 3
As show in Figure 2, after these 24 bits are clocked into the ICS307, taking STROBE high will send this
data to the internal latch and the CLK output will lock within 10 ms.
Note: If STROBE is in the high state and SCLK is pulsed, DATA is clocked directly to the internal latch and
the output conditions will change accordingly. Although this will not damage the ICS307, it is recommended
that STROBE be kept low while DATA is being clocked into the ICS307 in order to avoid unintended
changes on the output clocks.
AC Parameters for Writing to the ICS307
Parameter
tSETUP
tHOLD
tW
Condition
Setup time
Min.
10
Max.
Units
ns
Hold time after SCLK
Data wait time
10
ns
10
ns
tS
Strobe pulse width
SCLK Frequency
40
ns
50
MHz
DATA
tsetup
C1
C0
TTL
thold
F1
R1
R0
SCLK
tw
ts
STROBE
Figure 2. Timing Diagram for Programming the ICS307
External Components/Crystal Selection
The ICS307 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be connected
close to the ICS307 to minimize lead inductance. A 33Ω terminating resistor can be used in series with CLK1 and
CLK2 outputs. A parallel resonant, fundamental mode crystal with a load (correlation) capacitance of C should be
used, where C is the value calculated from Table 4. For crystals with a specified load capacitance greater than C,
additional crystal capacitors may be connected from each of the pins X1 and X2 to ground as shown in the Block
Diagram on page 1. The value (in pF) of these crystal caps should be = (C -C)*2, where C is the crystal load
L
L
capacitance in pF and C is the capacitance value from Table 4. These external capacitors are only required for
applications where the exact frequency is critical. For a clock input, connect to X1 and leave X2 unconnected (no
capacitors on either pin).
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
6
ICS307-01/-02 REV H 090209
ICS307-01/-02
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS307-01/-02. These
ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional
operation of the device at these or any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
can affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70° C
Ambient Operating Temperature
Ambient Operating Temperature, Industrial
Storage Temperature
-40 to +85° C
-65 to +150° C
260°C
Soldering Temperature
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
° C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
+3.0
+5.5
V
DC Electrical Characteristics
VDD=3.3 V 5% , Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.0
5.5
V
Input High Voltage
Input Low Voltage
Input High Voltage
V
X1/ICLK only
(VDD/2)+1 VDD/2
V
V
V
IH
V
X1/ICLK only
VDD/2 (VDD/2)-1
IL
V
2
IH
Input Low Voltage
V
PDTS on ICS307-01
0.4
0.8
V
V
IL
All other inputs,
ICS307-01/02
Output High Voltage
Output Low Voltage
V
I
I
I
= -25 mA
= 25 mA
= -4 mA
2.4
V
V
V
OH
OH
OL
OH
V
0.4
OL
Output High Voltage,
CMOS level
V
VDD-0.4
OH
Operating Supply Current
IDD
20 MHz crystal
No load, 100 MHz out
26
13
mA
mA
100 MHz out, 3.3 V
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
7
ICS307-01/-02 REV H 090209
ICS307-01/-02
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Parameter
Short Circuit Current
Input Capacitance
Symbol
Conditions
Min.
Typ.
70
Max.
Units
mA
CLK outputs
C
R
4
pF
IN
On-Chip Pull-up Resistor
Pin 13
270
kΩ
PU
AC Electrical Characteristics
VDD = 3.3 V 5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Frequency
F
Fundamental
5
27
MHz
IN
crystal
Clock
2
6
50
MHz
MHz
Output Frequency (see Table 1)
200
I-temp version
6
180
MHz
ns
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
t
0.8 to 2.0 V, Note 1
2.0 to 8.0 V, Note 1
even output divides
odd output divides
1
1
OR
t
ns
OF
45
40
49-51
55
60
10
%
%
STROBE goes high
until CLK out
Power-up Time
3
ms
One Sigma Clock Period Jitter
Maximum Absolute Jitter
50
ps
ps
Deviation from mean
t
120
ja
Note 1: Measured with 15 pF load.
Thermal Characteristics
Parameter
Symbol
Conditions
Still air
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
120
115
105
58
° C/W
° C/W
° C/W
° C/W
JA
θ
1 m/s air flow
3 m/s air flow
JA
θ
JA
Thermal Resistance Junction to Case
θ
JC
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
8
ICS307-01/-02 REV H 090209
ICS307-01/-02
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
16
Symbol
Min
Max
1.75
0.25
0.51
0.25
10.00
4.00
Min
Max
A
A1
B
C
D
E
e
1.35
0.10
0.33
0.19
9.80
3.80
.0532
.0040
.013
.0075
.3859
.1497
.0688
.0098
.020
.0098
.3937
.1574
E
H
INDEX
AREA
1.27 BASIC
0.050 BASIC
1
2
H
h
L
5.80
0.25
0.40
0°
6.20
.2284
.010
.016
0°
.2440
.020
.050
8°
D
0.50
1.27
8°
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
ICS307M-01
ICS307M-01
ICS307M-01I
ICS307M-01I
ICS307M-02
ICS307M-02
ICS307M-02LF
ICS307M-02LF
ICS307M-02I
ICS307M-02I
307M-02ILF
307M-02ILF
Shipping packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
307M-01*
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
307M-01T*
307M-01I*
Tape and Reel
Tubes
307M-01IT*
307M-02*
Tape and Reel
Tubes
307M-02T*
307M-02LF
307M-02LFT
307M-02I*
Tape and Reel
Tubes
Tape and Reel
Tubes
307M-02IT*
307M-02ILF
307M-02ILFT
Tape and Reel
Tubes
Tape and Reel
*NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other
circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those
requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant
any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
9
ICS307-01/-02 REV H 090209
ICS307-01/-02
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
www.idt.com/go/clockhelp
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
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