29FCT2052ATQ8 [IDT]
QSOP-24, Reel;
| 型号： | 29FCT2052ATQ8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | QSOP-24, Reel |
| 文件： | 总7页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS
OCTAL REGISTERED
TRANSCEIVER
IDT29FCT2052AT/BT/CT
DESCRIPTION:
FEATURES:
• A, B, and C grades
The IDT29FCT2052T is an 8-bit registered transceiver built using an
advanceddualmetalCMOStechnology.Two8-bitback-to-backregisters
store data flowing in both directions between two bidirectional buses.
Separateclock,clockenableand3-stateoutputenablesignalsareprovided
foreachregister. BothAoutputsandBoutputsareguaranteedtosink64mA.
The IDT29FCT2052T has balanced drive outputs with current limiting
resistors. This offers low ground bounce, minimal undershoot and con-
trolledoutputfalltimes-reducingthe needforexternalseries terminating
resistors. TheIDT29FCT2052Tisaplug-inreplacementfortheIDT29FCT52T.
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility:
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High Drive outputs (-15mA IOH, 48mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Power off disable outputs permit "live insertion"
• Available in SOIC and QSOP packages
FUNCTIONALBLOCKDIAGRAM
CPA
CEA
OEB
CE
CP
0
1
Q0
Q1
Q2
Q3
Q4
B
B
0
1
A0
A1
A2
A3
A4
D
D
D2
D3
D4
B2
B3
B4
B5
B6
B7
A
Reg.
5
5
5
A
D
Q
A6
A7
D6
D7
Q6
Q7
0
0
Q
Q
Q
Q
D
1
2
3
1
D
2
D
B
Reg.
3
D
Q4
Q5
Q6
Q7
D4
D5
D6
D7
CE
CP
CPB
CEB
OEA
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MAY 2001
1
© 2001 Integrated Device Technology, Inc.
DSC-5502/1
IDT29FCT2052AT/BT/CT
FASTCMOSOCTALREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +7
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
24
23
22
21
20
19
18
17
16
15
14
13
1
2
B7
B6
VCC
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
° C
mA
A7
A6
A5
B5
3
4
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
B4
B3
B2
A4
A3
A2
5
6
7
8
9
SO24-2
SO24-8
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
B1
B0
A1
A0
OEB
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
CIN
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
Typ.
6
Max. Unit
OEA
CPB
CPA
10
11
10
12
pF
pF
CEA
GND
COUT
VOUT = 0V
8
CEB
12
NOTE:
1. This parameter is measured at characterization but not tested.
SOIC/ QSOP
TOP VIEW
REGISTERFUNCTIONTABLE(1)
(Applies to A or B Register)
Inputs
Internal
D
X
L
CP
X
↑
CE
H
L
Q
N C
L
Function
HoldData
LoadData
H
↑
L
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
NC = No Change
↑ = LOW-to-HIGH Transition
OUTPUTCONTROL(1)
Internal
OE
H
Q
X
L
Y-Outputs
Function
Z
L
DisableOutputs
EnableOutputs
L
L
H
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
2
IDT29FCT2052AT/BT/CT
INDUSTRIALTEMPERATURERANGE
FASTCMOSOCTALREGISTEREDTRANSCEIVER
PINDESCRIPTION
Name
I/O
I/O
I/O
I
Description
EightbidirectionallinescarryingtheARegisterinputsorBRegisteroutputs
EightbidirectionallinescarryingtheBRegisterinputsorARegisteroutputs
A0-7
B0-7
CPA
CEA
Clock for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of the CPA signal.
I
ClockEnable forthe ARegister. WhenCEAis LOW, data is enteredintothe ARegisteronthe LOW-to-HIGHtransitionofthe CPAsignal. When
CEA is HIGH, the A Register holds its contents, regardless of CPA signal transitions.
OEB
I
OutputEnablefortheARegister. WhenOEBisLOW,theARegisteroutputsareenabledontotheB0-7 lines. WhenOEBisHIGH,theB0-7 outputs
areinthehigh-impedancestate.
CPB
I
I
Clock for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of the CPB signal.
CEB
ClockEnable forthe BRegister. WhenCEBis LOW, data is enteredintothe BRegisteronthe LOW-to-HIGHtransitionofthe CPBsignal. When
CEB is HIGH, the B Register holds its contents, regardless of CPB signal transitions.
OEA
I
OutputEnablefortheBRegister. WhenOEAisLOW,theBRegisteroutputsareenabledontotheA0-7 lines. WhenOEAisHIGH,theA0-7 outputs
areinthehigh-impedancestate.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%
Symbol
VIH
VIL
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2
Typ.(2)
—
Max.
—
Unit
V
Input LOW Level
Guaranteed Logic LOW Level
VCC = Max.
—
—
—
—
—
—
—
—
—
—
0.8
±1
±1
±1
±1
±1
–1.2
—
V
IIH
Input HIGH Current(4)
Input LOW Current(4)
High Impedance Output Current
VI = 2.7V
VI = 0.5V
VI = 2.7V
VI = 0.5V
—
µA
µA
µA
IIL
VCC = Max.
—
IOZH
IOZL
II
VCC = Max., VI = VCC (Max.)
—
(4)
(3-State Output pins)
—
Input HIGH Current(4)
Clamp Diode Voltage
Input Hysteresis
VCC = Max., VI = VCC (Max.)
VCC = Min., IIN = –18mA
—
µA
V
VIK
VH
–0.7
200
0.01
—
mV
µ A
ICC
Quiescent Power Supply Current
VCC = 3V
1
VIN = GND or VCC
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
OutputLOWCurrent
Output HIGH Current
OutputHIGHVoltage
Test Conditions(1)
Min.
16
Typ.(2)
48
Max.
—
Unit
mA
mA
V
(3)
IODL
IODH
VOH
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V
(3)
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V
-16
2.4
-48
—
VCC = Min
IOH = –15mA
3.3
—
VIN = VIH or VIL
VCC = Min
VOL
Output LOWVoltage
IOL = 12mA
—
0.3
0.5
V
VIN = VIH or VIL
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
3
IDT29FCT2052AT/BT/CT
FASTCMOSOCTALREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V
—
0.5
2
mA
(3)
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
VIN = VCC
VIN = GND
—
0.06
0.12
mA/
MHz
OEA or OEB = GND
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
Outputs Open
fCP = 10MHz
VIN = VCC
VIN = GND
—
—
0.6
1.1
2.2
4.2
mA
50% Duty Cycle
OEA or OEB = GND
One Bit Toggling
VIN = 3.4V
VIN = GND
at fi = 5MHz
50% Duty Cycle
(5)
VCC = Max.
Outputs Open
fCP = 10MHz
VIN = VCC
VIN = GND
—
—
1.5
3.8
4
50% Duty Cycle
OEA or OEB = GND
Eight Bits Toggling
(5)
VIN = 3.4V
VIN = GND
13
at fi = 2.5MHz
50% Duty Cycle
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of ∆ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2+ fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Output Frequency
fi = Output Frequency
Ni = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.
4
IDT29FCT2052AT/BT/CT
INDUSTRIALTEMPERATURERANGE
FASTCMOSOCTALREGISTEREDTRANSCEIVER
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE(1)
29FCT2052AT
29FCT2052BT
29FCT2052CT
(2)
(2)
(2)
Symbol
tPLH
Parameter
Condition(1)
CL = 50pF
RL = 500Ω
Min.
Max.
10
Min.
Max.
Min.
Max.
Unit
PropagationDelay
2
2
1.5
1.5
2.5
1.5
3
7.5
2
1.5
1.5
2.5
1.5
3
6.3
ns
tPHL
CPA, CPB to An, Bn
OutputEnableTime
tPZH
tPZL
1.5
1.5
2.5
2
10.5
10
8
7
ns
ns
ns
ns
ns
ns
ns
OEA or OEB to An, Bn
OutputDisableTime
tPHZ
tPLZ
7.5
—
—
—
—
—
6.5
—
—
—
—
—
OEA or OEB to An, Bn
Set-up Time, HIGH or LOW
An, Bn to CPA, CPB
Hold Time, HIGH or LOW
An, Bn to CPA, CPB
Set-up Time, HIGH or LOW
CEA, CEB to CPA, CPB
Hold Time, HIGH or LOW
CEA, CEB to CPA, CPB
tSU
—
—
—
—
—
tH
tSU
tH
3
2
2
2
(3)
tW
Clock Pulse Width HIGH or LOW
3
3
3
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
5
IDT29FCT2052AT/BT/CT
FASTCMOSOCTALREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
V CC
SWITCHPOSITION
7.0V
Test
Switch
Closed
Open
500Ω
Open Drain
Disable Low
Enable Low
V OUT
VIN
Pulse
Generator
D.U.T.
All Other Tests
50pF
500Ω
T
R
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
L
C
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal link
Test Circuits for All Outputs
3V
1.5V
0V
DATA
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
3V
CLEAR
ETC.
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
Octal link
CLEAR
CLOCK ENABLE
ETC.
tSU
tH
Pulse Width
Octal link
Set-Up, Hold, and Release Times
ENABLE
DISABLE
3V
3V
SAME PHASE
INPUT TRANSITION
1.5V
0V
CONTROL
INPUT
1.5V
0V
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
OUTPUT
3.5V
1.5V
3.5V
VOL
VOH
1.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
3V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
Octal link
0V
Octal link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT29FCT2052AT/BT/CT
INDUSTRIALTEMPERATURERANGE
FASTCMOSOCTALREGISTEREDTRANSCEIVER
ORDERINGINFORMATION
XXXX
X
IDT
XX
FCT
Device Type
Package
Temp. Range
SO
Q
Small Outline IC (SO24-2)
Quarter-size Small Outline Package (SO24-8)
Octal Registered Transceiver
52AT
52BT
52CT
29
- 40°C to +85°C
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
logichelp@idt.com
(408) 654-6459
www.idt.com
7
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