2308A-3DCGI8 [IDT]

Clock Driver, PDSO16;
2308A-3DCGI8
型号: 2308A-3DCGI8
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

Clock Driver, PDSO16

光电二极管
文件: 总10页 (文件大小:96K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
3.3V ZERO DELAY CLOCK  
MULTIPLIER  
IDT2308A  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution for Applications ranging  
from 10MHz to 133MHz operating frequency  
• Distributes one clock input to two banks of four outputs  
• Separate output enable for each output bank  
• External feedback (FBK) pin is used to synchronize the outputs  
to the clock input  
TheIDT2308Aisahigh-speedphase-lockloop(PLL)clockmultiplier.Itis  
designedtoaddresshigh-speedclockdistributionandmultiplicationapplica-  
tions.Thezerodelayisachievedbyaligningthephasebetweentheincoming  
clockandtheoutputclock, operablewithintherangeof10to133MHz.  
TheIDT2308Ahastwobanksoffouroutputseachthatarecontrolledviatwo  
selectaddresses.Byproperselectionofinputaddresses,bothbankscanbe  
put in tri-state mode. In test mode, the PLL is turned off, and the input clock  
directlydrivestheoutputsforsystemtestingpurposes. Intheabsenceofan  
input clock, the IDT2308A enters power down. In this mode, the device will  
• Output Skew <200 ps  
• Low jitter <200 ps cycle-to-cycle  
• 1x, 2x, 4x output options (see table):  
– IDT2308A-1 1x  
– IDT2308A-2 1x, 2x  
– IDT2308A-3 2x, 4x  
drawlessthan12μAforCommercialTemperaturerangeandlessthan25μA  
forIndustrialtemperaturerange,andtheoutputsaretri-stated.  
The IDT2308A is available in six unique configurations for both pre-  
scaling and multiplication of the Input REF Clock. (See available options  
table.)  
ThePLLisclosedexternallytoprovidemoreflexibilitybyallowingtheuser  
tocontrolthedelaybetweentheinputclockandtheoutputs.  
TheIDT2308AischaracterizedforbothIndustrialandCommercialopera-  
tion.  
– IDT2308A-4 2x  
– IDT2308A-1H and -2H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
• Available in SOIC and TSSOP packages  
FUNCTIONALBLOCKDIAGRAM  
(-3, -4)  
16  
2
FBK  
REF  
2
CLKA1  
PLL  
1
3
CLKA2  
14  
CLKA3  
15  
CLKA4  
8
9
S2  
S1  
Control  
Logic  
2
(-2, -3)  
6
CLKB1  
CLKB2  
CLKB3  
CLKB4  
7
10  
11  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
MAY 2010  
1
c
2010 Integrated Device Technology, Inc.  
DSC 6587/9  
IDT2308A  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
PINCONFIGURATION  
ABSOLUTEMAXIMUMRATINGS(1)  
Symbol  
Rating  
Max.  
–0.5to+4.6  
–0.5to+5.5  
–0.5to  
Unit  
V
VDD  
SupplyVoltageRange  
InputVoltageRange(REF)  
InputVoltageRange  
(except REF)  
(2)  
VI  
VI  
V
1
2
16  
15  
14  
13  
12  
REF  
FBK  
V
CLKA1  
CLKA4  
CLKA3  
VDD  
VDD+0.5  
–50  
3
IIK (VI < 0)  
IO  
InputClampCurrent  
ContinuousOutputCurrent  
mA  
mA  
CLKA2  
±50  
4
5
6
VDD  
(VO = 0 to VDD)  
VDD or GND  
TA = 55°C  
(instillair)(3)  
TSTG  
GND  
CLKB1  
CLKB2  
S2  
GND  
CLKB4  
CLKB3  
S1  
ContinuousCurrent  
±100  
0.7  
mA  
W
MaximumPowerDissipation  
11  
10  
9
7
8
StorageTemperatureRange  
CommercialTemperature  
Range  
–65to+150  
0 to +70  
°C  
°C  
Operating  
Temperature  
Operating  
Temperature  
NOTES:  
IndustrialTemperature  
Range  
-40to+85  
°C  
SOIC/ TSSOP  
TOP VIEW  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may  
cause permanent damage to the device. This is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated in the  
operational sections of this specification is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect reliability.  
2. The input and output negative-voltage ratings may be exceeded if the input and output  
clamp-current ratings are observed.  
3. The maximum package power dissipation is calculated using a junction temperature  
PINDESCRIPTION  
of 150°C and a board trace length of 750 mils.  
Pin Number  
FunctionalDescription  
REF (1)  
CLKA1(2)  
CLKA2(2)  
VDD  
1
2
InputReferenceClock,5VoltTolerantInput  
Clock Output for Bank A  
Clock Output for Bank A  
3.3V Supply  
3
4
GND  
5
Ground  
CLKB1(2)  
CLKB2(2)  
S2(3)  
6
Clock Output for Bank B  
Clock Output for Bank B  
Select Input, Bit 2  
APPLICATIONS:  
• SDRAM  
• Telecom  
7
8
S1(3)  
9
Select Input, Bit 1  
• Datacom  
• PC Motherboards/Workstations  
• Critical Path Delay Designs  
CLKB3(2)  
CLKB4(2)  
GND  
10  
11  
12  
13  
14  
15  
16  
Clock Output for Bank B  
Clock Output for Bank B  
Ground  
VDD  
3.3V Supply  
CLKA3(2)  
CLKA4(2)  
FBK  
Clock Output for Bank A  
Clock Output for Bank A  
PLLFeedbackInput  
NOTES:  
1. Weak pull down.  
2. Weak pull down on all outputs.  
3. Weak pull ups on these inputs.  
2
IDT2308A  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
FUNCTION TABLE(1)SELECTINPUTDECODING  
S2  
L
S1  
L
CLK A  
Tri-State  
Driven  
Driven  
Driven  
CLK B  
Tri-State  
Tri-State  
Driven  
Output Source  
PLL Shut Down  
PLL  
PLL  
REF  
PLL  
Y
N
Y
N
L
H
L
H
H
H
Driven  
NOTE:  
1. H = HIGH Voltage Level  
L = LOW Voltage Level  
AVAILABLEOPTIONSFORIDT2308A  
Device  
FeedbackFrom  
Bank A or Bank B  
Bank A or Bank B  
Bank A  
BankAFrequency  
BankBFrequency  
IDT2308A-1  
IDT2308A-1H  
IDT2308A-2  
IDT2308A-2  
IDT2308A-2H  
IDT2308A-2H  
IDT2308A-3  
IDT2308A-3  
IDT2308A-4  
Reference  
Reference  
Reference  
Reference  
Reference/2  
Reference  
Reference/2  
Reference  
Reference  
Bank B  
2xReference  
Reference  
Bank A  
Bank B  
2xReference  
2xReference  
4xReference  
2xReference  
(1)  
Bank A  
ReferenceorReference  
2 x Reference  
Bank B  
Bank A or Bank B  
2 x Reference  
NOTE:  
1. Output phase is indeterminant (0° or 180° from input clock).  
ZERO DELAY AND SKEW CONTROL  
To close the feedback loop of the IDT2308A, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin  
willbedrivingatotalloadof7pFplusanyadditionalloadthatitdrives. Therelativeloadingofthisoutput(withrespecttotheremainingoutputs)canadjust  
theinput-outputdelay.  
Forapplicationsrequiringzeroinput-outputdelay, alloutputsincludingtheoneprovidingfeedbackshouldbeequallyloaded. Ensuretheoutputsare  
loaded equally, for zero output-output skew.  
3
IDT2308A  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
OPERATINGCONDITIONS-COMMERCIAL  
Symbol  
Parameter  
Test Conditions  
Min.  
3
Max.  
3.6  
70  
Unit  
V
VDD  
SupplyVoltage  
TA  
OperatingTemperature(AmbientTemperature)  
LoadCapacitancebelow100MHz  
LoadCapacitancefrom100MHzto133MHz  
InputCapacitance(1)  
0
°C  
pF  
pF  
pF  
CL  
30  
15  
CIN  
7
NOTE:  
1. Applies to both REF and FBK.  
DCELECTRICALCHARACTERISTICS-COMMERCIAL  
Symbol  
VIL  
Parameter  
Conditions  
Min.  
2
Typ.(1)  
Max.  
0.8  
Unit  
V
InputLOWVoltageLevel  
Input HIGH Voltage Level  
InputLOWCurrent  
Input HIGH Current  
OutputLOWVoltage  
VIH  
V
IIL  
VIN = 0V  
50  
μA  
μA  
V
IIH  
VIN = VDD  
100  
0.4  
VOL  
IOL = 8mA (-1, -2, -3, -4)  
IOL = 12mA (-1H, -2H)  
IOH = -8mA (-1, -2, -3, -4)  
IOH = -12mA (-1H, -2H)  
REF = 0MHz (S2 = S1 = H)  
VOH  
Output HIGH Voltage  
Power Down Current  
2.4  
V
IDD_PD  
12  
45  
70  
32  
50  
18  
30  
μA  
100MHz CLKA (-1, -2, -3, -4)  
100MHz CLKA (-1H, -2H)  
66MHz CLKA (-1, -2, -3, -4)  
66MHz CLKA (-1H, -2H)  
33MHz CLKA (-1, -2, -3, -4)  
33MHz CLKA (-1H, -2H)  
IDD  
SupplyCurrent  
UnloadedOutputs  
mA  
Select Inputs at VDD or GND  
4
IDT2308A  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
SWITCHINGCHARACTERISTICS-COMMERCIAL  
Symbol Parameter  
Conditions  
Min.  
10  
Typ.  
Max.  
100  
Unit  
MHz  
MHz  
MHz  
%
t1  
t1  
t1  
OutputFrequency  
30pFLoad, alldevices  
OutputFrequency  
20pF Load, -1H, -2H Devices  
15pF Load, -1, -2, -3, -4 devices  
Measured at 1.4V, FOUT = 66.66MHz  
30pFLoad  
10  
133.3  
133.3  
60  
OutputFrequency  
10  
Duty Cycle = t2 ÷ t1  
40  
50  
(-1, -2, -3, -4, -1H, -2H)  
Duty Cycle = t2 ÷ t1  
Measured at 1.4V, FOUT = 50MHz  
15pFLoad  
45  
50  
55  
%
(-1, -2, -3, -4, -1H, -2H)  
Rise Time (-1, -2, -3, -4)  
Rise Time (-1, -2, -3, -4)  
Rise Time (-1H, -2H)  
t3  
t3  
t3  
t4  
t4  
t4  
t5  
Measuredbetween0.8Vand2V, 30pFLoad  
Measuredbetween0.8Vand2V, 15pFLoad  
Measuredbetween0.8Vand2V, 30pFLoad  
Measuredbetween0.8Vand2V, 30pFLoad  
Measuredbetween0.8Vand2V, 15pFLoad  
Measuredbetween0.8Vand2V, 30pFLoad  
Alloutputsequallyloaded  
2.2  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
ps  
1.5  
Fall Time (-1, -2, -3, -4)  
2.2  
Fall Time (-1, -2, -3, -4)  
1.5  
FallTime(-1H)  
1.25  
200  
Output to Output Skew on same Bank  
(-1, -2, -3, -4)  
Output to Output Skew (-1H, -2H)  
Output Bank A to Output Bank B (-1, -4, -2H)  
Output Bank A to Output Bank B Skew (-2, -3)  
Alloutputsequallyloaded  
Alloutputsequallyloaded  
Alloutputsequallyloaded  
200  
200  
400  
ps  
ps  
ps  
t6  
t7  
t8  
Delay, REF Rising Edge to FBK Rising Edge  
Device to Device Skew  
MeasuredatVDD/2  
1
0
0
±250  
700  
ps  
ps  
Measured at VDD/2 on the FBK pins of devices  
Measured between 0.8V and 2V on -1H, -2H  
deviceusingTestCircuit2  
OutputSlewRate  
V/ns  
tJ  
Cycle to Cycle Jitter  
(-1, -1H, -4)  
Measuredat66.67MHz,loadedoutputs,15pFLoad  
Measuredat66.67MHz,loadedoutputs,30pFLoad  
Measuredat133.3MHz,loadedoutputs,15pFLoad  
Measuredat66.67MHz,loadedoutputs,30pFLoad  
Measuredat66.67MHz,loadedoutputs,15pFLoad  
Stable Power Supply, valid clocks presented  
on REF and FBK pins  
200  
200  
100  
400  
400  
1
ps  
ps  
tJ  
Cycle to Cycle Jitter  
(-2, -2H, -3)  
tLOCK  
PLLLockTime  
ms  
5
IDT2308A  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
OPERATINGCONDITIONS-INDUSTRIAL  
Symbol  
Parameter  
Test Conditions  
Min.  
3
Max.  
3.6  
+85  
30  
Unit  
V
VDD  
SupplyVoltage  
TA  
OperatingTemperature(AmbientTemperature)  
LoadCapacitancebelow100MHz  
LoadCapacitancefrom100MHzto133MHz  
InputCapacitance(1)  
-40  
°C  
pF  
CL  
15  
pF  
CIN  
7
pF  
NOTE:  
1. Applies to both REF and FBK.  
DCELECTRICALCHARACTERISTICS-INDUSTRIAL  
Symbol  
VIL  
Parameter  
Conditions  
Min.  
2
Typ.(1)  
Max.  
0.8  
Unit  
V
InputLOWVoltageLevel  
Input HIGH Voltage Level  
InputLOWCurrent  
Input HIGH Current  
OutputLOWVoltage  
VIH  
V
IIL  
VIN = 0V  
50  
μA  
μA  
V
IIH  
VIN = VDD  
100  
0.4  
VOL  
IOL = 8mA (-1, -2, -3, -4)  
IOL = 12mA (-1H, -2H)  
IOH = -8mA (-1, -2, -3, -4)  
IOH = -12mA (-1H, -2H)  
REF = 0MHz (S2 = S1 = H)  
VOH  
Output HIGH Voltage  
Power Down Current  
2.4  
V
IDD_PD  
25  
45  
70  
32  
50  
18  
30  
μA  
100MHz CLKA (-1, -2, -3, -4)  
100MHz CLKA (-1H, -2H)  
66MHz CLKA (-1, -2, -3, -4)  
66MHz CLKA (-1H, -2H)  
33MHz CLKA (-1, -2, -3, -4)  
33MHz CLKA (-1H, -2H)  
IDD  
SupplyCurrent  
UnloadedOutputs  
mA  
Select Inputs at VDD or GND  
6
IDT2308A  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
SWITCHINGCHARACTERISTICS-INDUSTRIAL  
Symbol Parameter  
Conditions  
Min.  
10  
Typ.  
Max.  
100  
Unit  
MHz  
MHz  
MHz  
%
t1  
t1  
t1  
OutputFrequency  
30pFLoad, alldevices  
OutputFrequency  
20pF Load, -1H, -2H Devices  
15pF Load, -1, -2, -3, -4 devices  
Measured at 1.4V, FOUT = 66.66MHz  
30pFLoad  
10  
133.3  
133.3  
60  
OutputFrequency  
10  
Duty Cycle = t2 ÷ t1  
40  
50  
(-1, -2, -3, -4, -1H, -2H)  
Duty Cycle = t2 ÷ t1  
Measured at 1.4V, FOUT = 50MHz  
15pFLoad  
45  
50  
55  
%
(-1, -2, -3, -4, -1H, -2H)  
Rise Time (-1, -2, -3, -4)  
Rise Time (-1, -2, -3, -4)  
Rise Time (-1H, -2H)  
t3  
t3  
t3  
t4  
t4  
t4  
t5  
Measuredbetween0.8Vand2V, 30pFLoad  
Measuredbetween0.8Vand2V, 15pFLoad  
Measuredbetween0.8Vand2V, 30pFLoad  
Measuredbetween0.8Vand2V, 30pFLoad  
Measuredbetween0.8Vand2V, 15pFLoad  
Measuredbetween0.8Vand2V, 30pFLoad  
Alloutputsequallyloaded  
2.2  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
ps  
1.5  
Fall Time (-1, -2, -3, -4)  
2.2  
Fall Time (-1, -2, -3, -4)  
1.5  
FallTime(-1H)  
1.25  
200  
Output to Output Skew on same Bank  
(-1, -2, -3, -4)  
Output to Output Skew (-1H, -2H)  
Output Bank A to Output Bank B (-1, -4, -2H)  
Output Bank A to Output Bank B Skew (-2, -3)  
Alloutputsequallyloaded  
Alloutputsequallyloaded  
Alloutputsequallyloaded  
200  
200  
400  
ps  
ps  
ps  
t6  
t7  
t8  
Delay, REF Rising Edge to FBK Rising Edge  
Device to Device Skew  
MeasuredatVDD/2  
1
0
0
±250  
700  
ps  
ps  
Measured at VDD/2 on the FBK pins of devices  
Measured between 0.8V and 2V on -1H, -2H  
deviceusingTestCircuit2  
OutputSlewRate  
V/ns  
tJ  
Cycle to Cycle Jitter  
(-1, -1H, -4)  
Measuredat66.67MHz,loadedoutputs,15pFLoad  
Measuredat66.67MHz,loadedoutputs,30pFLoad  
Measuredat133.3MHz,loadedoutputs,15pFLoad  
Measuredat66.67MHz,loadedoutputs,30pFLoad  
Measuredat66.67MHz,loadedoutputs,15pFLoad  
Stable Power Supply, valid clocks presented  
on REF and FBK pins  
200  
200  
100  
400  
400  
1
ps  
ps  
tJ  
Cycle to Cycle Jitter  
(-2, -2H, -3)  
tLOCK  
PLLLockTime  
ms  
7
IDT2308A  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
SWITCHINGWAVEFORMS  
t1  
t2  
1.4V  
1.4V  
1.4V  
Duty Cycle Timing  
3.3V  
0V  
0.8V  
t3  
0.8V  
2V  
2V  
Output  
t4  
All Outputs Rise/Fall Time  
1.4V  
Output  
1.4V  
Output  
t5  
Output to Output Skew  
VDD/2  
Input  
FBK  
VDD/2  
t6  
Input to Output Propagation Delay  
FBK,  
Device 1  
VDD/2  
FBK,  
Device 2  
VDD/2  
t7  
Device to Device Skew  
8
IDT2308A  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
TESTCIRCUITS  
TEST CIRCUIT 1  
TEST CIRCUIT 2  
VDD  
VDD  
1K  
1K  
CLK  
OUT  
CLK  
OUT  
0.1 F  
0.1 F  
0.1 F  
OUTPUTS  
OUTPUTS  
C
10pF  
LOAD  
VDD  
GND  
VDD  
0.1 F  
GND  
GND  
GND  
Test Circuit for t8, Output Slew Rate On -1H and -2H Devices  
Test Circuit for all Parameters Except t8  
9
IDT2308A  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
ORDERINGINFORMATION  
XXXXX  
XX  
X
IDT  
Package Process  
Device Type  
o
o
Blank  
I
Commercial (0 C to +70 C)  
o o  
Industrial (-40 C to +85 C)  
DC  
Small Outline  
DCG  
PG  
SOIC - Green  
Thin Shrink Small Outline Package  
PGG  
TSSOP - Green  
2308A-1  
2308A-2  
2308A-3  
2308A-4  
2308A-1H  
2308A-2H  
Zero Delay Clock Buffer with Standard Drive  
Zero Delay Clock Buffer with High Drive  
}
}
Ordering Code  
PackageType  
OperatingRange  
IDT2308A-1DCG  
IDT2308A-1DCGI  
16-Pin SOIC  
16-Pin SOIC  
Commercial  
Industrial  
IDT2308A-1HDCG  
IDT2308A-1HDCGI  
16-Pin SOIC  
16-Pin SOIC  
Commercial  
Industrial  
IDT2308A-1HPG  
IDT2308A-1HPGG  
IDT2308A-1HPGGI  
IDT2308A-1HPGI  
16-Pin TSSOP  
16-Pin TSSOP  
16-Pin TSSOP  
16-Pin TSSOP  
Commercial  
Commercial  
Industrial  
Industrial  
IDT2308A-2DCG  
IDT2308A-2DCGI  
16-Pin SOIC  
16-Pin SOIC  
Commercial  
Industrial  
IDT2308A-2HDCG  
IDT2308A-2HDCGI  
16-Pin SOIC  
16-Pin SOIC  
Commercial  
Industrial  
IDT2308A-3DCG  
IDT2308A-3DCGI  
16-Pin SOIC  
16-Pin SOIC  
Commercial  
Industrial  
IDT2308A-4DCG  
IDT2308A-4DCGI  
16-Pin SOIC  
16-Pin SOIC  
Commercial  
Industrial  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
for Tech Support:  
clockhelp@idt.com  
www.idt.com  
10  

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