181M-53 [IDT]
Clock Generator, 75MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8;
| 型号： | 181M-53 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 75MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8 光电二极管 |
| 文件： | 总7页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
LOW EMI CLOCK GENERATOR
ICS181-53
Description
Features
The ICS181-53 generates a low EMI output clock from
a clock or crystal input. The device uses IDT’s
proprietary mix of analog and digital Phase Locked
Loop (PLL) technology to spread the frequency
spectrum of the output, thereby reducing the frequency
amplitude peaks by several dB.
• Pin and function compatible to Cypress W181-53
• Packaged in 8-pin SOIC
• Provides a spread spectrum output clock
• Accepts a clock input and provides same frequency
dithered output
• Input frequency of 46 to 75 MHz for Clock input
The ICS181-53 offers center spread selection of
+/-0.625% and +/-1.875%. Refer to the MK1714-01/02
for the widest selection of input frequencies and
multipliers.
• Peak reduction by 7dB - 14dB typical on 3rd - 19th
odd harmonics
• Spread percentage selection for +/-0.625% and
+/-1.875%
IDT offers a complete line of EMI reducing clock
generators. Consult us when you need to remove
crystals and oscillators from your board.
• Operating voltage of 3.3 V and 5 V
• Advanced, low-power CMOS process
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
VDD
FS1
SSON#
PLL Clock
Synthesis
SS%
and Spread
Spectrum
Circuitry
CLK
CLKIN
Clock Buffer
GND
IDT™ / ICS™ LOW EMI CLOCK GENERATOR
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ICS181-53
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ICS181-53
LOW EMI CLOCK GENERATOR
SSCG
Pin Assignment
Spread Spectrum Select Table
CLKIN
NC
1
2
3
4
8
7
6
5
SSON#
FS1
SS%
(Pin 4)
Spread
Direction
Spread
Percentage (%)
GND
SS%
VDD
0
1
Center
Center
+/-0.625%
+/1.875%
CLKOUT
0 = connect to GND
1 = connect directly to VDD
8-pin (150 mil) SOIC
Note: SS% pin has an internal pull-up resistor
Frequency Range Selection Table
FS1
Frequency
(Pin 7) Range Selection
(MHz)
0
1
46-60
58-75
Pin Descriptions
Pin
Pin
Pin Type
Pin Description
Number
Name
1
2
3
4
5
6
7
8
CLKIN
NC
Input
—
Clock Input.
No connect. Do not connect this pin to anything.
Connect to ground.
GND
Power
Input
SS%
Select pin for spread amount. See table above. Internal pull-up resistor.
CLKOUT
VDD
Output Spread spectrum clock output per table above.
Power
Input
Input
Connect to 3.3 V or 5 V.
FS1
Select pin for input frequency. See table above. Internal pull-up resistor.
SSON#
Spread Spectrum Control. This pin enables spread spectrum when low.
Internal pull-down resistor.
IDT™ / ICS™ LOW EMI CLOCK GENERATOR
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ICS181-53
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ICS181-53
LOW EMI CLOCK GENERATOR
SSCG
PCB Layout Recommendations
External Components
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
The ICS181-53 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the VDD
pin as possible. No vias should be used between the
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via.
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 6 and 3, as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
2) To minimize EMI, the 33Ωseries termination resistor
(if needed) should be placed close to the clock output.
Series Termination Resistor
When the PCB trace between the clock output and the
load is over 1 inch, series termination should be used.
To series terminate a 50Ωtrace (a commonly used trace
impedance) place a 33Ωresistor in series with the clock
line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20Ω.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS181-53. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
value of these capacitors is given by the following
equation:
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS181-53. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
125°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
° C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
+3.135
+5.5
V
IDT™ / ICS™ LOW EMI CLOCK GENERATOR
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ICS181-53
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ICS181-53
LOW EMI CLOCK GENERATOR
SSCG
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ± 5%, Ambient Temperature 0 to +70° C
Parameter
Operating Voltage
Supply Current
Symbol
VDD
Conditions
Min.
Typ.
Max.
3.465
32
Units
3.135
V
mA
V
IDD
No load
18
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Input Capacitance
V
2.4
IH
V
0.8
V
IL
V
V
I
I
I
= -4 mA
= -15 mA
= 15 mA
VDD-0.4
2.4
V
OH
OH
OH
OH
OL
V
V
0.4
7
V
OL
C
All pins except CLKIN
CLKIN pin only
5
6
pF
pF
ohms
KΩ
ms
IN
10
Output Impedance
Input Pull-up Resistor
Power-up Time
Rout
25
500
First locked clock
cycle after steady
power
5
Unless stated otherwise, VDD = 5 V, ±10%, Ambient Temperature 0 to +70°C
Parameter
Operating Voltage
Supply Current
Symbol
VDD
Conditions
Min.
Typ.
5
Max.
5.5
Units
V
4.5
IDD
No load
30
50
mA
V
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Impedance
Input Capacitance
V
0.7VDD
2.4
IH
V
0.15VDD
0.4
V
IL
V
I
I
= -24 mA
= 24 mA
V
OH
OH
V
V
OL
OL
Rout
20
5
ohms
pF
pF
KΩ
ms
C
All pins except CLKIN
CLKIN pin only
7
IN
6
10
Input Pull-up Resistor
Power-up Time
500
First locked clock
cycle after steady
power
5
IDT™ / ICS™ LOW EMI CLOCK GENERATOR
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ICS181-53
REV B 081009
ICS181-53
LOW EMI CLOCK GENERATOR
SSCG
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5% or 5 V 10%, Ambient Temperature 0 to +70° C, C =15 pf
L
Parameter
Input/Output Clock Frequency
Input Clock Duty Cycle
Output Clock Duty Cycle
Output Rise Time
Symbol
Conditions
Min.
46
Typ. Max. Units
75
60
60
5
MHz
Time above VDD/2
Note 1
40
%
%
40
50
2
t
0.8 to 2.4 V, note 1
2.4 to 0.8 V, note 1
Cycle-to-cycle
ns
ns
ps
OR
Output Fall Time
t
2
5
OF
Jitter
250
300
Note 1: Measured with 15 pF load
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
150
140
120
40
° C/W
° C/W
° C/W
° C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
Marking Diagram
8
5
Notes:
1. ###### is the lot number.
181M-53
2. YYWW is the last two digits of the year and week that
the part was assembled.
######
YYWW
3. “LF” denotes Pb (lead) free package.
4. Bottom marking: country of origin.
1
4
Marking Diagram (Pb free)
8
5
181M53LF
######
YYWW
1
4
IDT™ / ICS™ LOW EMI CLOCK GENERATOR
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ICS181-53
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ICS181-53
LOW EMI CLOCK GENERATOR
SSCG
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
Min Max
8
Symbol
Min
1.35
0.10
0.33
0.19
4.80
3.80
Max
1.75
0.25
0.51
0.25
5.00
4.00
A
A1
B
C
D
E
e
.0532
.0040
.013
.0688
.0098
.020
E
H
INDEX
AREA
.0075
.1890
.1497
.0098
.1968
.1574
1.27 BASIC
0.050 BASIC
1
2
H
h
L
5.80
0.25
0.40
0°
6.20
.2284
.010
.016
0°
.2440
.020
.050
8°
0.50
1.27
8°
D
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
181M-53*
Marking
Shipping packaging
Tubes
Package
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
Temperature
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
181M-53T*
181M-53LF
181M-53LFT
Tape and Reel
Tubes
Tape and Reel
see page 5
*NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
“LF” denotes Pb free packaging.
While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for
either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits,
patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such
as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without
notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LOW EMI CLOCK GENERATOR
6
ICS181-53
REV B 081009
ICS181-53
LOW EMI CLOCK GENERATOR
SSCG
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
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