1339C-2SRI [IDT]
REAL-TIME CLOCK WITH SERIAL I2C INTERFACE; 具有串行I2C接口实时时钟
| 型号： | 1339C-2SRI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | REAL-TIME CLOCK WITH SERIAL I2C INTERFACE |
| 文件： | 总27页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
2
REAL-TIME CLOCK WITH SERIAL I C INTERFACE
IDT1339
General Description
Features
The IDT1339 serial real-time clock (RTC) is a low-power
clock/date device with two programmable time-of-day
alarms and a programmable square-wave output. Address
and data are transferred serially through an I2C bus. The
clock/date provides seconds, minutes, hours, day, date,
month, and year information. The date at the end of the
month is automatically adjusted for months with fewer than
31 days, including corrections for leap year. The clock
operates in either the 24-hour or 12-hour format with
AM/PM indicator. The IDT1339 has a built-in power-sense
circuit that detects power failures and automatically
switches to the backup supply, maintaining time, date, and
alarm operation.
•
Real-Time Clock (RTC) counts seconds, minutes, hours,
day, date, month, and year with leap-year compensation
valid up to 2100
•
Packaged in 8-pin MSOP, 8-pin SOIC, or 16-pin SOIC
(surface-mount package with an integrated crystal)
Fast mode I2C Serial interface
•
•
•
•
•
•
•
Two time-of-day alarms
Programmable square-wave output
Oscillator stop flag
Automatic power-fail detect and switch circuitry
Trickle-charge capability
Applications
Industrial temperature range (-40 to +85°C)
•
•
Handhelds (GPS, POS terminals)
Consumer Electronics (Set-Top Box, Digital Recording,
Network Applications)
•
•
•
•
Office (Fax/Printers, Copiers)
Medical (Glucometer, Medicine Dispensers)
Telecomm (Routers, Switches, Servers)
Other (Thermostats, Vending Machines, Modems, Utility
Meters)
Block Diagram
Crystal inside package
for 16-pin SOIC ONLY
1 Hz/4.096 kHz/
8.192 kHz/32.768 kHz
X1
X2
MUX/
Buffer
32.768 kHz
Oscillator and
Divider
SQW/INT
GND
VCC
Clock,
Calendar
Counter
Control
Logic
Power
Control
Trickle
Charger
VBACKUP
SCL
SDA
I2C
Interface
1 Byte 7 Bytes 7 Bytes 1 Byte
Control Buffer Alarm Status
IDT® REAL-TIME CLOCK WITH SERIAL I2C INTERFACE
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REAL-TIME CLOCK WITH SERIAL I2C INTERFACE
RTC
Pin Assignment (8-pin MSOP/8-pin SOIC)
Pin Assignment (16-pin SOIC)
X1
8
7
6
5
16
15
14
13
1
2
3
4
VCC
1
2
3
4
5
6
7
8
SCL
SQW/INT
VCC
SDA
X2
SQW/INT
SCL
IDT
1339
GND
VBACKUP
VBACKUP
IDT
1339C
GND
SDA
NC
NC
NC
NC
NC
NC
NC
NC
NC
12
11
10
9
NC
Pin Descriptions
Pin
Number
Pin
Name
Pin Description/Function
MSOP SOIC
1
2
—
—
X1
X2
Connections for standard 32.768 kHz quartz crystal. The internal oscillator circuitry is
designed for operation with a crystal having a specified load capacitance (CL) of 7 pF. An
external 32.768 kHz oscillator can also drive the IDT1339. In this configuration, the X1 pin
is connected to the external oscillator signal and the X2 pin is left floating.
3
14
VBACKUP Backup supply input. Supply voltage must be held between 1.3 V and 3.7 V for proper
operation. This pin can be connected to a primary cell, such as a lithium button cell.
Additionally, this pin can be connected to a rechargeable cell or a super cap that can be
charged using the trickle charger circuit. Diodes placed in series between the backup
source and the VBAT pin may prevent proper operation. If a backup supply is not required,
VBAT must be connected to ground.
4
5
15
16
GND
SDA
Connect to ground. DC power is provided to the device on these pins.
Serial data input/output. SDA is the input/output pin for the I2C serial interface. The SDA pin
is an open-drain output and requires an external pull-up resistor (2 kΩ typical).
6
7
1
2
SCL
Serial clock input. SCL is used to synchronize data movement on the serial interface. It is an
open-drain output and requires an external pull-up resistor (2 kΩ typical).
SQW/INT Square-Wave/Interrupt output. Programmable square-wave or interrupt output signal. The
SQW/INT pin is an open-drain output and requires an external pull-up resistor (10 kΩ
typical).
8
3
VCC
Primary power supply. When voltage is applied within normal limits, the device is fully
accessible and data can be written and read.
—
4 - 13
NC
No connect. These pins are unused and must be connected to ground.
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Typical Operating Circuit
CRYSTAL
VCC
VCC
VCC
1
2
8
RPU
2k
RPU
2k
VCC
10k
X1
X2
6
5
7
3
SCL
SQW/INT
CPU
IDT1339
VBACKUP
SDA
+
GND
4
-
Detailed Description
The following sections discuss in detail the Oscillator block,
Power Control block, Clock/Calendar Register, Alarms,
trickle Charger, and Serial I2C block.
Oscillator Block
Selection of the right crystal, correct load capacitance and
careful PCB layout are important for a stable crystal
oscillator. Due to the optimization for the lowest possible
current in the design for these oscillators, losses caused by
parasitic currents can have a significant impact on the
overall oscillator performance. Extra care needs to be taken
to maintain a certain quality and cleanliness of the PCB.
Crystal Selection
The key parameters when selecting a 32 kHz crystal to work
with IDT1339 RTC are:
In the above figure, X1 and X2 are the crystal pins of our
device. Cin1 and Cin2 are the internal capacitors which
include the X1 and X2 pin capacitance. Cex1 and Cex2 are
the external capacitors that are needed to tune the crystal
frequency. Ct1 and Ct2 are the PCB trace capacitances
between the crystal and the device pins. CS is the shunt
capacitance of the crystal (as specified in the crystal
manufacturer's datasheet or measured using a network
analyzer).
•
•
•
Recommended Load Capacitance
Crystal Effective Series Resistance (ESR)
Frequency Tolerance
Effective Load Capacitance
Please see diagram below for effective load capacitance
calculation. The effective load capacitance (CL) should
match the recommended load capacitance of the crystal in
order for the crystal to oscillate at its specified parallel
resonant frequency with 0ppm frequency error.
Note: IDT1339CSRI integrates a standard 32.768 kHz
( 20ppm) crystal in the package and contributes an
additional frequency error of 10ppm at nominal VCC (+3.3 V)
and TA=+25°C.
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ESR (Effective Series Resistance)
PCB Layout
Choose the crystal with lower ESR. A low ESR helps the
crystal to start up and stabilize to the correct output
frequency faster compared to high ESR crystals.
Frequency Tolerance
The frequency tolerance for 32 KHz crystals should be
specified at nominal temperature (+25°C) on the crystal
manufacturer datasheet. The crystals used with IDT1338
typically have a frequency tolerance of 20ppm at +25°C.
1339
Specifications for a typical 32 kHz crystal used with our
device are shown in the table below.
PCB Assembly, Soldering and Cleaning
Board-assembly production process and assembly quality
can affect the performance of the 32 kHz oscillator.
Depending on the flux material used, the soldering process
can leave critical residues on the PCB surface. High
humidity and fast temperature cycles that cause humidity
condensation on the printed circuit board can create
process residuals. These process residuals cause the
insulation of the sensitive oscillator signal lines towards
each other and neighboring signals on the PCB to decrease.
High humidity can lead to moisture condensation on the
surface of the PCB and, together with process residuals,
reduce the surface resistivity of the board. Flux residuals on
the board can cause leakage current paths, especially in
humid environments. Thorough PCB cleaning is therefore
highly recommended in order to achieve maximum
performance by removing flux residuals from the board after
assembly. In general, reduction of losses in the oscillator
circuit leads to better safety margin and reliability.
Parameter
Nominal Freq.
Symbol Min
Typ
Max Units
fO
ESR
CL
32.768
kHz
Series Resistance
Load Capacitance
50
kΩ
7
pF
PCB Design Consideration
•
Signal traces between IDT device pins and the crystal
must be kept as short as possible. This minimizes
parasitic capacitance and sensitivity to crosstalk and
EMI. Note that the trace capacitances play a role in the
effective crystal load capacitance calculation.
•
Data lines and frequently switching signal lines should be
routed as far away from the crystal connections as
possible. Crosstalk from these signals may disturb the
oscillator signal.
•
•
Reduce the parasitic capacitance between X1 and X2
signals by routing them as far apart as possible.
Power Control
The oscillation loop current flows between the crystal and
the load capacitors. This signal path (crystal to CL1 to
CL2 to crystal) should be kept as short as possible and
ideally be symmetric. The ground connections for both
capacitors should be as close together as possible.
Never route the ground connection between the
capacitors all around the crystal, because this long
ground trace is sensitive to crosstalk and EMI.
The power-control function is provided by a precise,
temperature-compensated voltage reference and a
comparator circuit that monitors the VCC level. The device is
fully accessible and data can be written and read when VCC
is greater than VPF. However, when VCC falls below VPF, the
internal clock registers are blocked from any access. If VPF
is less than VBACKUP, the device power is switched from VCC
to VBACKUP when VCC drops below VPF. If VPF is greater than
VBACKUP, the device power is switched from VCC to VBACKUP
when VCC drops below VBACKUP. The registers are
maintained from the VBACKUP source until VCC is returned to
nominal levels (Table 1). After VCC returns above VPF, read
and write access is allowed after tREC (see the
•
To reduce the radiation / coupling from oscillator circuit,
an isolated ground island on the GND layer could be
made. This ground island can be connected at one point
to the GND layer. This helps to keep noise generated by
the oscillator circuit locally on this separated island. The
ground connections for the load capacitors and the
oscillator should be connected to this island.
“Power-Up/Down Timing” diagram).
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Table 1. Power Control
Supply Condition
Read/Write Powered
Access
By
VBACKUP
VCC
VCC < VPF, VCC
VCC < VPF, VCC
VCC > VPF, VCC
VCC > VPF, VCC
<
>
<
>
VBACKUP
VBACKUP
VBACKUP
VBACKUP
No
No
Yes
VCC
Yes
VCC
Power-up/down Timing
Table 2. Power-up/down Characteristics
Ambient Temperature -40 to +85° C
Parameter
Symbol
tREC
Conditions
Min.
Typ.
Max.
Units
ms
Recovery at Power-up
(see note below)
2
VCC Fall Time; VPF(MAX) to VPF(MIN)
tVCCF
300
0
µs
V
CC Rise Time; VPF(MIN) to VPF(MAX)
tVCCR
µs
Note: This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay
occurs.
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Address Map
Table 3 (Timekeeper Registers) shows the address map for the IDT1339 registers. During a multibyte access, when the
address pointer reaches the end of the register space (10h), it wraps around to location 00h. On an I2C START, STOP, or
address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time
information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read
the registers in case of an update of the main registers during a read.
Table 3. Timekeeper Registers
Address
00h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
Seconds
Minutes
Range
00 - 59
00 - 59
0
0
10 seconds
10 minutes
AM/PM
Seconds
01h
Minutes
Hour
1 - 12
+ AM/PM
00 - 23
02h
0
12/24
10 hour
0
Hours
10 hour
03h
04h
05h
0
0
0
0
0
0
0
Day
Day
Date
1 - 7
10 date
Date
01 - 31
Century
0
10 month
Month
Month/Century
01 - 12 +
Century
06h
07h
10 year
Year
Year
00 - 99
00 - 59
A1M1
A1M2
10 seconds
Seconds
Alarm 1
Seconds
08h
10 minutes
Minutes
Alarm 1
Minutes
00 - 59
AM/PM
10 hour
1 - 12
+ AM/PM
00 - 23
09h
0Ah
0Bh
A1M3
A1M4
A2M2
12/24
10 hour
Hour
Alarm 1 Hours
DY/DT
10 date
Day, Date
Minutes
Alarm 1 Day,
Alarm 1 Date
1 - 7, 1 - 31
10 minutes
Alarm 2
Minutes
00 - 59
AM/PM
10 hour
1 - 12
+ AM/PM
00 - 23
0Ch
0Dh
A2M3
A2M4
12/24
10 hour
Hour
Alarm 2 Hours
DY/DT
10 date
Day, Date
Alarm 2 Day,
Alarm 2 Date
1 - 7, 1 - 31
0Eh
0Fh
10h
EOSC
OSF
0
0
BBSQI
0
RS2
0
RS1
0
INTCN
A2IE
A2F
A1IE
A1F
Control
Status
0
TCS3
TCS2
TCS1
TCS0
DS1
DS0
ROUT1
ROUT0 Trickle Charger
Note: Unless otherwise specified, the state of the registers are not defined when power is first applied or when VCC and VBACKUP falls
below the VBACKUP(min)
.
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Time and Date Operation
Alarms
The time and date information is obtained by reading the
appropriate register bytes. Table 3 shows the RTC registers.
The time and date are set or initialized by writing the
appropriate register bytes. The contents of the time and
date registers are in the BCD format. The IDT1339 can be
run in either 12-hour or 24-hour mode. Bit 6 of the hours
register is defined as the 12- or 24-hour mode-select bit.
When high, the 12-hour mode is selected. In the 12-hour
mode, bit 5 is the AM/PM bit with logic high being PM. In the
24-hour mode, bit 5 is the second 10-hour bit (20 to 23
hours). All hours values, including the alarms, must be
re-entered whenever the 12/24-hour mode bit is changed.
The century bit (bit 7 of the month register) is toggled when
the years register overflows from 99 to 00. The day-of-week
register increments at midnight. Values that correspond to
the day of week are user-defined, but must be sequential
(i.e., if 1 equals Sunday, then 2 equals Monday and so on).
Illogical time and date entries result in undefined operation.
The IDT1339 contains two time of day/date alarms. Alarm 1
can be set by writing to registers 07h to 0Ah. Alarm 2 can be
set by writing to registers 0Bh to 0Dh. The alarms can be
programmed (by the Alarm Enable and INTCN bits of the
Control Register) to activate the SQW/INT output on an
alarm match condition. Bit 7 of each of the time of day/date
alarm registers are mask bits (Table 4). When all the mask
bits for each alarm are logic 0, an alarm only occurs when
the values in the timekeeping registers 00h to 06h match the
values stored in the time of day/date alarm registers. The
alarms can also be programmed to repeat every second,
minute, hour, day, or date. Table 4 shows the possible
settings. Configurations not listed in the table result in
illogical operation.
The DY/DT bits (bit 6 of the alarm day/date registers) control
whether the alarm value stored in bits 0 to 5 of that register
reflects the day of the week or the date of the month. If
DY/DT is written to a logic 0, the alarm is the result of a
match with date of the month. If DY/DT is written to a logic
1, the alarm is the result of a match with day of the week.
When reading or writing the time and date registers,
secondary (user) buffers are used to prevent errors when
the internal registers update. When reading the time and
date registers, the user buffers are synchronized to the
internal registers on any start or stop, and when the address
pointer rolls over to zero. The countdown chain is reset
whenever the seconds register is written. Write transfers
occurs on the acknowledge pulse from the device. To avoid
rollover issues, once the countdown chain is reset, the
remaining time and date registers must be written within one
second. If enabled, the 1 Hz square-wave output transitions
high 500 ms after the seconds data transfer, provided the
oscillator is already running.
The device checks for an alarm match once per second.
When the RTC register values match alarm register
settings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is
set to logic 1. If the corresponding Alarm Interrupt Enable
‘A1IE’ or ‘A2IE’ is also set to logic 1 and the INTCN bit is set
to logic 1, the alarm condition activates the SQW/INT signal.
If the BBSQI bit is set to 1, the INT output activates while the
part is being powered by VBACKUP. The alarm output
remains active until the alarm flag is cleared by the user.
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Table 4. Alarm Mask Bits
DY/DT Alarm 1 Register Mask Bits (Bit 7)
Alarm Rate
A1M4
A1M3
A1M2
A1M1
X
X
X
X
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Alarm once per second.
Alarm when seconds match.
Alarm when minutes and seconds match.
Alarm when hours, minutes, and seconds match.
Alarm when date, hours, minutes, and seconds match.
Alarm when day, hours, minutes, and seconds match.
1
DY/DT Alarm 2 Register Mask Bits (Bit 7)
Alarm Rate
A2M4
A2M3
A2M2
X
X
X
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Alarm once per minute (00 sec. of every min.).
Alarm when minutes match.
Alarm when hours and minutes match.
Alarm when date, hours, and minutes match.
Alarm when day, hours, and minutes match.
1
Special-Purpose Registers
The IDT1339 has two additional registers (control and status) that control the RTC, alarms, and square-wave output.
Control Register (0Eh)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EOSC
0
BBSQI
RS2
RS1
INTCN
A2IE
A1IE
Bit 7: Enable Oscillator (EOSC). This bit when set to logic 0 starts the oscillator. When this bit is set to a logic 1,
the oscillator is stopped. This bit is enabled (logic 0) when power is first applied.
Bit 5: Battery-Backed Square-Wave and Interrupt Enable (BBSQI). This bit when set to a logic 1 enables the
square wave or interrupt output when VCC is absent and the IDT1339 is being powered by the VBACKUP pin. When
BBSQI is a logic 0, the SQW/INT pin goes high impedance when VCC falls below the power-fail trip point. This bit is
disabled (logic 0) when power is first applied.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the
square wave has been enabled. Table 5 shows the square-wave frequencies that can be selected with the RS bits.
These bits are both set to logic 1 (32 kHz) when power is first applied.
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Table 5. SQW/INT Output
INTCN
RS2
0
RS1
0
SQW/INT Output
1 Hz
A2IE
A1IE
0
0
0
0
1
1
1
X
X
X
X
0
X
X
X
X
1
0
1
4.096 kHz
8.192 kHz
32.768 kHz
A1F
1
0
1
1
X
X
X
X
A2F
1
0
X
X
A2F + A1F
1
1
Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output
pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 or alarm 2
registers activate the SQW/INT pin (provided that the alarm is enabled). When the INTCN bit is set to logic 0, a
square wave is output on the SQW/INT pin. This bit is set to logic 0 when power is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to a logic 1, this bit permits the Alarm 2 Flag (A2F) bit in the
status register to assert SQW/INT (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0,
the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the Alarm 1 Flag (A1F) bit in the status
register to assert SQW/INT (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the A1F
bit does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied.
Status Register (0Fh)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSF
0
0
0
0
0
A2F
A1F
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped
for some period of time and may be used to judge the validity of the clock and date data. This bit is edge triggered
and is set to logic 1 when the oscillator stops. The following are examples of conditions that can cause the OSF bit
to be set:
1) The first time power is applied.
2) The voltage on both VCC and VBACKUP are insufficient to support oscillation.
3) The EOSC bit is turned off.
4) External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to a logic 0.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the Alarm 2 Flag bit indicates that the time matched the alarm 2 registers. If
the A2IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A2F is cleared when
written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the Alarm 1 Flag bit indicates that the time matched the alarm 1 registers. If
the A1IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A1F is cleared when
written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
IDT® REAL-TIME CLOCK WITH SERIAL I2C INTERFACE
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Trickle Charger Register (10h)
Programmable Trickle Charger
The simplified “Programmable Trickle Charger” schematic shows the basic components of the trickle charger. The
trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accidental enabling, only
a pattern of 1010 on the TCS bits enables the trickle charger. All other patterns disable the trickle charger. The trickle
charger is disabled when power is first applied. The diode-select (DS) bits (bits 2 and 3) select whether or not a diode is
connected between VCC and VBACKUP. The ROUT bits (bits 0 and 1) select the value of the resistor connected between VCC
and VBACKUP. Table 6 shows the bit values.
Table 6. Trickle Charger Register (10h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
TCS3 TCS2 TCS1 TCS0
DS1
0
DS0
0
ROUT 1 ROUT 0
X
X
X
1
1
1
1
1
1
0
X
X
X
0
0
0
0
0
0
0
X
X
X
1
1
1
1
1
1
0
X
X
X
0
0
0
0
0
0
0
X
X
0
0
0
1
1
1
1
0
X
X
0
1
1
0
0
1
1
0
Disabled
Disabled
Disabled
1
1
X
0
X
1
No diode, 250Ω resistor
One diode, 250Ω resistor
No diode, 2kΩ resistor
One diode, 2kΩ resistor
No diode, 4kΩ resistor
One diode, 4kΩ resistor
Initial power-up values
1
0
0
1
1
0
0
1
1
0
0
0
Warning: The ROUT value of 250Ωmust not be selected whenever VCC is greater than 3.63 V.
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RTC
The user determines diode and resistor selection according to the maximum current desired for battery or super cap
charging. The maximum charging current can be calculated as illustrated in the following example. Assume that a 3.3 V
system power supply is applied to VCC and a super cap is connected to VBACKUP. Also assume that the trickle charger has
been enabled with a diode and resistor R2 between VCC and VBACKUP. The maximum current IMAX would therefore be
calculated as follows:
IMAX = (3.3 V - diode drop) / R2 (3.3 V - 0.7 V) / 2kΩ 1.3 mA
As the super cap or battery charges, the voltage drop between VCC and VBACKUP decreases and therefore the charge
current decreases.
2
I C Serial Data Bus
The IDT1339 supports the I2C bus protocol. A device that
sends data onto the bus is defined as a transmitter and a
device receiving data as a receiver. The device that controls
the message is called a master. The devices that are
controlled by the master are referred to as slaves. The bus
must be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and generates
the START and STOP conditions. The IDT1339 operates as
a slave on the I2C bus. Within the bus specifications, a
standard mode (100 kHz cycle rate) and a fast mode (400
kHz cycle rate) are defined. The IDT1339 works in both
modes. Connections to the bus are made via the open-drain
I/O lines SDA and SCL.
the line must be changed during the LOW period of the clock
signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions is
not limited, and is determined by the master device. The
information is transferred byte-wise and each receiver
acknowledges with a ninth bit.
Acknowledge: Each receiving device, when addressed, is
obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit.
The following bus protocol has been defined (see the “Data
Transfer on I2C Serial Bus” figure):
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse. Of course, setup and hold
times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the slave. In
this case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
•
•
Data transfer may be initiated only when the bus is not
busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH are interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
Timeout: Timeout is where a slave device resets its
interface whenever Clock goes low for longer than the
timeout, which is typically 35mSec. This added logic deals
with slave errors and recovering from those errors. When
timeout occurs, the slave interface should re-initialize itself
and be ready to receive a communication from the master,
but it will expect a Start prior to any new communication.
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line,
from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop data transfer: A change in the state of the data line,
from LOW to HIGH, while the clock line is HIGH, defines the
STOP condition.
Data valid: The state of the data line represents valid data
when, after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. The data on
IDT® REAL-TIME CLOCK WITH SERIAL I2C INTERFACE
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2
Data Transfer on I C Serial Bus
Depending upon the state of the R/W bit, two types of data
transfer are possible:
bit (see the “Data Write–Slave Receiver Mode” figure). The
slave address byte is the first byte received after the START
condition is generated by the master. The slave address
byte contains the 7-bit IDT1339 address, which is 1101000,
followed by the direction bit (R/W), which is 0 for a write.
After receiving and decoding the slave address byte the
slave outputs an acknowledge on the SDA line. After the
IDT1339 acknowledges the slave address + write bit, the
master transmits a register address to the IDT1339. This
sets the register pointer on the IDT1339, with the IDT1339
acknowledging the transfer. The master may then transmit
zero or more bytes of data, with the IDT1339 acknowledging
each byte received. The address pointer increments after
each data byte is transferred. The master generates a STOP
condition to terminate the data write.
1) Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after each received byte.
Data is transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is transmitted by
the master. The slave then returns an acknowledge bit. This
is followed by the slave transmitting a number of data bytes.
The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received
byte, a “not acknowledge” is returned. The master device
generates all of the serial clock pulses and the START and
STOP conditions. A transfer is ended with a STOP condition
or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial
transfer, the bus is not released. Data is transferred with the
most significant bit (MSB) first.
2) Slave Transmitter Mode (Read Mode): The first byte is
received and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates that the
transfer direction is reversed. Serial data is transmitted on
SDA by the IDT1339 while the serial clock is input on SCL.
START and STOP conditions are recognized as the
beginning and end of a serial transfer (see the “Data
Read–Slave Transmitter Mode” figure). The slave address
byte is the first byte received after the START condition is
generated by the master. The slave address byte contains
the 7-bit IDT1339 address, which is 1101000, followed by
the direction bit (R/W), which is 1 for a read. After receiving
and decoding the slave address byte the slave outputs an
acknowledge on the SDA line. The IDT1339 then begins to
transmit data starting with the register address pointed to by
The IDT1339 can operate in the following two modes:
1) Slave Receiver Mode (Write Mode): Serial data and
clock are received through SDA and SCL. After each byte is
received an acknowledge bit is transmitted. START and
STOP conditions are recognized as the beginning and end
of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction
IDT® REAL-TIME CLOCK WITH SERIAL I2C INTERFACE
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the register pointer. If the register pointer is not written to
before the initiation of a read mode the first address that is
read is the last one stored in the register pointer. The
address pointer is incremented after each byte is
transferred. The IDT1339 must receive a “not acknowledge”
to end a read.
Data Write – Slave Receiver Mode
Data Read (from current Pointer location) – Slave Transmitter Mode
Data Read (Write Pointer, then Read) – Slave Receive and Transmit
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Handling, PCB Layout, and Assembly
The IDT1339 package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions should
be taken to ensure that excessive shocks are avioded. Ultarsonic cleaning equipment should be avioded to prevent damage
to the crystal.
Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line.
All NC (no connect) pins must be connected to ground.
Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label must
be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive device
(MSD) classifications.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT1339. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
All Inputs and Outputs
Symbol
Rating
-0.3 V to +6.0 V
-55 to +125° C
260° C
Storage Temperature
Soldering Temperature
Recommended DC Operating Conditions
Parameter
Symbol
TA
Min.
-40
Typ.
Max.
+85
3.7
Units
° C
V
Ambient Operating Temperature
Backup Supply Voltage
VBACKUP
VPU
1.3
3.0
Pull-up Resistor Voltage (SQW/INT, SDA, SCL),
VCC = 0V
5.5
V
Logic 1
VIH
VIL
0.7VCC
-0.3
VCC + 0.3
0.3VCC
V
V
Logic 0
Supply Voltage
IDT1339-2, Note A
IDT1339-31, Note A
Power Fail Voltage
IDT1339-2, Note B
IDT1339-31, Note B
VPF
VPF
2.0
3.3
5.5
5.5
VCC
V
V
1.40
2.45
1.70
2.70
1.80
2.97
VPF
Note A: Operating voltages without a back up supply connected.
IDT® REAL-TIME CLOCK WITH SERIAL I2C INTERFACE
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Note B: When a back up supply voltage is connected choose proper part number 1339-2 or 1339-31 depending
upon the back up supply voltage.
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DC Electrical Characteristics
Unless stated otherwise, VCC = MIN to MAX, Ambient Temperature -40 to +85°C, Note 1
Parameter
Input Leakage
Symbol
ILI
Conditions
Note 2
Min.
Typ.
Max. Units
1
1
3
µA
µA
I/O Leakage
ILO
Note 3
Logic 0 Out
VCC > 2.0 V
IOL
IDT1339-2, Note 3
mA
Logic 0 Out
VOL = 0.4; VCC > VCC Min.
VCC > 2.0 V
IOL
IOL
IOL
IDT1339-31,
Note 3
3
3
mA
mA
µA
Logic 0 Out
VOL = 0.2 V (VCC);
1.8 V < VCC < 2.0 V
Note 3
Note 3
Logic 0 Out
VOL = 0.2 V (VCC);
1.3 V < VCC < 1.8 V
250
VCC Active Current
ICCA
ICCS
Note 4
450
150
200
µA
µA
VCC Standby Current, Note 5
VCC < 3.63 V
3.63 V < VCC < 5.5 V
Note 6
80
Trickle-charger Resistor Register
10h = A5h, VCC = Typ, VBACKUP = 0V
R1
R2
250
2000
4000
25
Ω
Ω
Trickle-charger Resistor Register
10h = A6h, VCC = Typ, VBACKUP = 0V
Trickle-charger Resistor Register
10h = A7h, VCC = Typ, VBACKUP = 0V
R3
Ω
VBACKUP Leakage Current
IBKLKG
100
nA
DC Electrical Characteristics
Unless stated otherwise, VCC = 0V, Ambient Temperature -40 to +85° C, Note 1
Parameter
Symbol
Conditions
Min.
Typ.
400
600
10
Max.
700
Units
nA
VBACKUP Current EOSC = 0, SQW Off
VBACKUP Current EOSC = 0, SQW On
VBACKUP Current EOSC = 1
IBKOSC Note 7
IBKSQW Note 7
1000
100
nA
IBKDR
Note 7
nA
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AC Electrical Characteristics
Unless stated otherwise, VCC = MIN to MAX, Ambient Temperature -40 to +85° C, Note 13
Parameter
SCL Clock Frequency
Symbol
Conditions
Fast Mode
Min.
Typ. Max. Units
fSCL
100
400
100
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
pF
Standard Mode
Fast Mode
Bus Free Time Between a STOP and
START Condition
tBUF
1.3
Standard Mode
4.7
Hold Time (Repeated) START
Condition, Note 8
tHD:STA Fast Mode
Standard Mode
Fast Mode
0.6
4.0
Low Period of SCL Clock
tLOW
1.3
Standard Mode
Fast Mode
4.7
High Period of SCL Clock
tHIGH
0.6
Standard Mode
Fast Mode
4.0
Setup Time for a Repeated START
Condition
tSU:STA
0.6
Standard Mode
4.7
0
Data Hold Time, Notes 9, 10
tHD:DAT Fast Mode
Standard Mode
Fast Mode
0.9
0
Data Setup Time, Note 11
tSU:DAT
100
Standard Mode
Fast Mode
250
Rise Time of Both SDA and SCL
Signals, Note 12
tR
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
0.6
300
1000
300
Standard Mode
Fast Mode
Fall Time of Both SDA and SCL Signals,
Note 12
tF
Standard Mode
300
Setup Time for STOP Condition
tSU:STO Fast Mode
Standard Mode
4.0
Capacitive Load for Each Bus Line,
Note 12
CB
400
10
I/O Capacitance (SDA, SCL)
CI/O
tOSF
Note 13
Note 14
pF
Oscillator Stop Flag (OSF) Delay
100
ms
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in
battery-backup mode.
Note 1: Limits at -40°C are guaranteed by design and are not production tested.
Note 2: SCL only.
Note 3: SDA and SQW/INT.
Note 4: ICCA—SCL at fSC max, VIL = 0.0V, VIH = VCC, trickle charger disabled.
Note 5: Specified with the I2C bus inactive, VIL = 0.0V, VIH = VCC, trickle charger disabled.
Note 6: VCC must be less than 3.63 V if the 250Ω resistor is selected.
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Note 7: Using recommended crystal on X1 and X2.
Note 8: After this period, the first clock pulse is generated.
Note 9: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 10: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL
signal.
Note 11: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > to 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR(MAX)
tSU:DAT = 1000 + 250 = 1250 ns before the SCL line is released.
+
Note 12: CB—total capacitance of one bus line in pF.
Note 13: Guaranteed by design. Not production tested.
Note 14: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the
voltage range of 0.0V < VCC VCCMAX and 1.3 V < VBACKUP < 3.7 V.
<
Timing Diagram
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Typical Operating Characteristics (V =3.3V, T =25° C)
CC A
IBACKUP vs VBACKUP
Icc vs Vcc
(IDT1339-31)
RS1=RS0=00
(IDT1339-31)
SDA=GND
425
420
415
410
405
400
395
390
385
380
20
16
12
8
INTC=1
INTC=0
SCL=400kHz
SCL=0Hz
4
0
2.7
3.2
3.7
4.2
4.7
5.2
1.3
1.8
2.3
2.8
3.3
Supply current (uA)
VBACKUP (V)
IBACKUP vs Temperature
Oscillator Frequency vs Supply Voltage
(IDT1339-31)
(IDT1339-31)
RS1=RS0=00
32768.1
32768.05
32768
500
460
420
380
340
300
INTC=1
INTC=0
Freq
2.8
3.3
3.8
4.3
4.8
5.3
-40
-20
0
20
40
60
80
Frequency (Hz)
Temperature (C)
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Thermal Characteristics for 8MSOP
Parameter
Symbol
θJA
Conditions
Still air
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
95
°C/W
Thermal Resistance Junction to Case
θJC
48
°C/W
Thermal Characteristics for 8SOIC
Parameter
Symbol
Conditions
Still air
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θJA
θJA
θJA
θJC
150
140
120
40
° C/W
° C/W
° C/W
° C/W
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
Thermal Characteristics for 16SOIC
Parameter
Symbol
Conditions
Still air
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θJA
θJA
θJA
θJC
120
115
105
58
°C/W
°C/W
°C/W
°C/W
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
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Marking Diagram (8 MSOP)
Marking Diagram (16 SOIC)
16
9
31GI
YWW$
92GI
YWW$
IDT
1339C-31
SRI
#YYWW**$
IDT1339-31DVGI
IDT1339-2DVGI
1
8
9
Marking Diagram (8 SOIC)
IDT1339C-31SRI
8
5
8
5
16
IDT1339
-31DCGI
#YYWW$
IDT1339
-2DCGI
#YYWW$
IDT
1339C-2
SRI
#YYWW**$
1
4
1
4
IDT1339-31DCGI
IDT1339-2DCGI
1
8
IDT1339C-2SRI
Notes:
1. ‘#’ is the lot number.
2. ‘$’ is the assembly mark code.
3. YYWW is the last two digits of the year and week that the
part was assembled.
4. “G” denotes RoHS compliant package.
5. “I” denotes industrial grade.
6. Bottom marking: country of origin if not USA.
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Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
8
Symbol
Min
1.35
0.10
0.33
0.19
4.80
3.80
Max
1.75
0.25
0.51
0.25
5.00
4.00
Min
Max
A
A1
B
C
D
E
e
.0532
.0040
.013
.0688
.0098
.020
E
H
INDEX
AREA
.0075
.1890
.1497
.0098
.1968
.1574
1.27 BASIC
0.050 BASIC
1
2
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
.2284
.010
.016
0°
.2440
.020
.050
8°
D
L
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
α
B
L
.10 (.004)
C
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Package Outline and Package Dimensions (8-pin MSOP, 3.00 mm Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Min Max
Inches*
8
Symbol
Min
Max
A
A1
A2
b
--
1.10
0.15
0.97
0.38
0.23
--
0.043
0.006
0.038
0.015
0.009
0
0
0.79
0.22
0.08
0.031
0.008
0.003
E1
E
INDEX
AREA
C
D
3.00 BASIC
0.118 BASIC
0.193 BASIC
0.118 BASIC
0.0256 Basic
E
4.90 BASIC
3.00 BASIC
0.65 Basic
E1
e
1
2
L
0.40
0°
0.80
8°
0.10
0.016
0.032
8°
D
α
0°
aaa
-
-
0.004
*For reference only. Controlling dimensions in mm.
A
2
A
A
1
c
- C -
e
SEATING
PLANE
α
b
L
aaa
C
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Package Outline and Package Dimensions (16-pin SOIC, 300 mil Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches*
Min Max
16
Symbol
Min
--
Max
2.65
--
A
A1
A2
b
--
0.104
--
0.10
2.05
0.33
0.18
10.10
10.00
7.40
0.0040
0.081
0.013
0.007
0.397
0.394
0.291
2.55
0.51
0.32
10.50
10.65
7.60
0.100
0.020
0.013
0.413
0.419
0.299
E1
E
INDEX
AREA
c
D
E
1 2
E1
e
1.27 Basic
0.050 Basic
D
L
0.40
0°
1.27
8°
0.016
0.050
8°
α
0°
aaa
-
0.10
-
0.004
*For reference only. Controlling dimensions in mm.
A
2
A
A
1
c
- C-
e
SEATING
PLANE
α
b
L
aaa
C
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Ordering Information
Part / Order Number
1339-2DVGI
Marking
Shipping Packaging
Tubes
Package
8-pin MSOP
8-pin MSOP
8-pin SOIC
8-pin SOIC
16-pin SOIC
16-pin SOIC
8-pin MSOP
8-pin MSOP
8-pin SOIC
8-pin SOIC
16-pin SOIC
16-pin SOIC
Temperature
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
1339-2DVGI8
1339-2DCGI
Tape and Reel
Tubes
1339-2DCGI8
1339C-2SRI
Tape and Reel
Tubes
1339C-2SRI8
1339-31DVGI
1339-31DVGI8
1339-31DCGI
1339-31DCGI8
1339C-31SRI
1339C-31SRI8
Tape and Reel
Tubes
see page 20
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
The IDT1339 packages are RoHS compliant. Packages without the integrated crystal are Pb-free; packages that include the
integrated crystal (as designated with a “C” before the dash number) may include lead that is exempt under RoHS
requirements. The lead finish is JESD91 category e3.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Revision History
Rev. Originator
Date
Description of Change
A
B
C
S. Sharma
J. Sarma
J. Sarma
06/26/07 New device. Preliminary release.
11/01/07 Updated ordering info for 16-pin SOIC package.
01/17/08 Added 8-pin SOIC package; updated “Power-up/down Characteristics” table; updates to “Absolute
Maximum Ratings” table.
D
E
F
J. Sarma
J.Sarma
J.Sarma
02/11/08 Combined part numbers for 1339-3 and 1339-33 into one part number: 1339-31.
03/28/08 Added new note to Part Ordering information pertaining to RoHS compliance and Pb-free devices.
05/18/08 Changed the part number for the 16PIN SOIC package from IDT1339C-31SOGI to
IDT1339C-31SRI and the IDT1339C-2SOGI changed to IDT1339C-2SRI
G
H
J.Sarma
J.Sarma
08/04/08 Removed “Preliminary”; removed UL statement from pin 3 description.
11/20/08 Updated Block Diagram, Detailed description section(s), Operating Circuit diagram, and Typical
Operating Characteristics diagrams.
I
J.Sarma
S.S.
12/03/08 Updated Block Diagram, Features bullets, Pin descriptions, Typical Operating Characteristics
diagrams; added marking diagrams.
J
11/10/09 Added “Handling, PCB Layout, and Assembly” section.
03/29/10 Added “Timeout” paragraph on page 11.
K
IDT® REAL-TIME CLOCK WITH SERIAL I2C INTERFACE
26
IDT1339
REV K 032910
IDT1339
REAL-TIME CLOCK WITH SERIAL I2C INTERFACE
RTC
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