1338BC-31SRI [IDT]
Real Time Clock, Non-Volatile, 1 Timer(s), PDSO16, 0.300 INCH, ROHS COMPLIANT, SOIC-16;
| 型号： | 1338BC-31SRI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Real Time Clock, Non-Volatile, 1 Timer(s), PDSO16, 0.300 INCH, ROHS COMPLIANT, SOIC-16 光电二极管 外围集成电路 |
| 文件： | 总23页 (文件大小：427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
IDT1338B-31
• Others (Thermostats, Vending Machines, Modems, Utility
General Description
The IDT1338B-31 is a serial real-time clock (RTC) device
that consumes ultra-low power and provides a full
binary-coded decimal (BCD) clock/calendar with 56 bytes
of battery backed Non-Volatile Static RAM. The
clock/calendar provides seconds, minutes, hours, day, date,
month, and year information. The clock operates in either
the 24-hour or 12-hour format with AM/PM indicator. The
end of the month date is automatically adjusted for months
with fewer than 31 days, including corrections for leap year.
Access to the clock/calendar registers is provided by an I C
interface capable of operating in fast I C mode. Built-in
Power-sense circuitry detects power failures and
automatically switches to the backup supply, maintaining
time and date operation.
Meters)
Features
• Real-Time Clock (RTC) counts seconds, minutes, hours,
day, date, month, and year with leap-year compensation
valid up to 2100
• 56-Byte battery-backed Non Volatile RAM for data
storage
2
• Fast mode I C Serial interface
2
2
• Automatic power-fail detect and switch circuitry
• Programmable square-wave output
• Packaged in 8-pin MSOP, 8-pin SOIC, or 16-pin SOIC
(surface-mount package with an integrated crystal)
Applications
• Industrial temperature range (-40°C to +85°C)
• Telecom (Routers, Switches, Servers)
• Handheld (GPS, Point of Sale POS terminals)
• Consumer Electronics (Set-Top Box, Digital Recording,
Network Applications, Digital photo frames)
• Office (Fax/Printers, Copiers)
• Medical (Glucometer, Medicine Dispensers)
Block Diagram
Crystal inside package
for 16-pin SOIC ONLY
1 Hz/4.096 kHz/
8.192 kHz/32.768 kHz
X1
32.768 kHz
Oscillator and
Divider
MUX/
Buffer
SQW/OUT
X2
VCC
GND
VBAT
Power
Control
Control
Logic
Clock, Calendar
Counter
SCL
SDA
I2C
Interface
56 Byte
RAM
1 Byte 7 Bytes
Control
Buffer
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Pin Assignment (8-pin MSOP/8-pin SOIC)
Pin Assignment (16-pin SOIC)
16
15
14
13
1
2
3
4
5
6
7
8
SCL
SDA
X1
X2
8
7
6
5
1
2
3
4
VCC
SQW/OUT
GND
VBAT
SQW/OUT
SCL
IDT
1338
VCC
NC
VBAT
GND
IDT
1338C
NC
NC
NC
NC
NC
SDA
NC
NC
NC
12
11
10
9
NC
Pin Descriptions
Pin
Number
Pin
Name
Pin Description/Function
8MSOP, 16SOIC
8SOIC
1
2
—
—
X1
X2
Connections for standard 32.768 kHz quartz crystal. The internal oscillator circuitry is designed
for operation with a crystal having a specified load capacitance (CL) of 12.5 pF. An external
32.768 kHz oscillator can also drive the IDT1338B-31. In this configuration, the X1 pin is
connected to the external oscillator signal and the X2 pin is left floating.
3
14
VBAT
Backup Supply Input for Lithium Coin Cell or Other Energy Source. Battery voltage must be held
between the minimum and maximum limits for proper operation. Diodes placed in series
between the backup source and the VBAT pin may prevent proper operation. If a backup supply is
not required, VBAT must be connected to ground.
4
5
15
16
GND
SDA
Connect to ground.
Serial data input/output. SDA is the input/output pin for the I2C serial interface. It is an open-drain
output and requires an external pull-up resistor (2 Kohm typical).
6
7
1
2
SCL
Serial clock input. SCL is used to synchronize data movement on the serial interface. It is an
open-drain output and requires an external pull-up resistor (2 Kohm typical)
SQW/OUT Square-Wave/Output driver. When enabled and the SQWE bit set to 1, the SQW/OUT pin
outputs one of four square-wave frequencies (1 Hz, 4 kHz, 8 kHz, 32 kHz). It is an open drain
output and requires an external pull-up resistor (10K ohm typical). Operates when the device is
powered with VCC or VBAT
.
8
3
VCC
NC
Device power supply. When voltage is applied within specified limits, the device is fully
accessible by I2C and data can be written and read.
—
4 - 13
No connect. These pins are unused and must be connected to ground for proper operation.
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Typical Operating Circuit
CRYSTAL
VCC
VCC
VCC
2k
VCC
10k
2k
X1
X2
SCL
SQW/OUT
CPU
IDT1338
VBAT
SDA
+
-
GND
Detailed Description
The following sections discuss in detail the Oscillator block,
Power Control block, Clock/Calendar Register Block and
2
Serial I C block.
Oscillator Block
Selection of the right crystal, correct load capacitance and
careful PCB layout are important for a stable crystal
oscillator. Due to the optimization for the lowest possible
current in the design for these oscillators, losses caused by
parasitic currents can have a significant impact on the
overall oscillator performance. Extra care needs to be taken
to maintain a certain quality and cleanliness of the PCB.
Crystal Selection
The key parameters when selecting a 32 kHz crystal to work
with IDT1338 RTC are:
In the above figure, X1 and X2 are the crystal pins of our
device. Cin1 and Cin2 are the internal capacitors which
include the X1 and X2 pin capacitance. Cex1 and Cex2 are
the external capacitors that are needed to tune the crystal
frequency. Ct1 and Ct2 are the PCB trace capacitances
between the crystal and the device pins. CS is the shunt
capacitance of the crystal (as specified in the crystal
manufacturer's datasheet or measured using a network
analyzer).
• Recommended Load Capacitance
• Crystal Effective Series Resistance (ESR)
• Frequency Tolerance
Effective Load Capacitance
Please see diagram below for effective load capacitance
calculation. The effective load capacitance (CL) should
match the recommended load capacitance of the crystal in
order for the crystal to oscillate at its specified parallel
resonant frequency with 0ppm frequency error.
Note: IDT1338CSRI integrates a standard 32.768 kHz
crystal in the package and contributes an additional
frequency error of 10ppm at nominal VCC (+3.3 V) and
TA=+25°C.
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the oscillator circuit locally on this separated island. The
ground connections for the load capacitors and the
oscillator should be connected to this island.
ESR (Effective Series Resistance)
Choose the crystal with lower ESR. A low ESR helps the
crystal to start up and stabilize to the correct output
frequency faster compared to high ESR crystals.
PCB Layout
Frequency Tolerance
The frequency tolerance for 32 KHz crystals should be
specified at nominal temperature (+25°C) on the crystal
manufacturer datasheet. The crystals used with IDT1338
typically have a frequency tolerance of +/-20ppm at +25°C.
Specifications for a typical 32kHz crystal used with our
device are shown in the table below.
Parameter
Nominal Freq.
Symbol Min
Typ
Max Units
PCB Assembly, Soldering and Cleaning
fO
ESR
CL
32.768
kHz
Board-assembly production process and assembly quality
can affect the performance of the 32 KHz oscillator.
Depending on the flux material used, the soldering process
can leave critical residues on the PCB surface. High
humidity and fast temperature cycles that cause humidity
condensation on the printed circuit board can create
process residuals. These process residuals cause the
insulation of the sensitive oscillator signal lines towards
each other and neighboring signals on the PCB to decrease.
High humidity can lead to moisture condensation on the
surface of the PCB and, together with process residuals,
reduce the surface resistivity of the board. Flux residuals on
the board can cause leakage current paths, especially in
humid environments. Thorough PCB cleaning is therefore
highly recommended in order to achieve maximum
performance by removing flux residuals from the board after
assembly. In general, reduction of losses in the oscillator
circuit leads to better safety margin and reliability.
Series Resistance
Load Capacitance
50
kΩ
12.5
pF
PCB Design Consideration
• Signal traces between IDT device pins and the crystal
must be kept as short as possible. This minimizes
parasitic capacitance and sensitivity to crosstalk and
EMI. Note that the trace capacitances play a role in the
effective crystal load capacitance calculation.
• Data lines and frequently switching signal lines should be
routed as far away from the crystal connections as
possible. Crosstalk from these signals may disturb the
oscillator signal.
• Reduce the parasitic capacitance between X1 and X2
signals by routing them as far apart as possible.
• The oscillation loop current flows between the crystal and
the load capacitors. This signal path (crystal to CL1 to
CL2 to crystal) should be kept as short as possible and
ideally be symmetric. The ground connections for both
capacitors should be as close together as possible.
Never route the ground connection between the
capacitors all around the crystal, because this long
ground trace is sensitive to crosstalk and EMI.
• To reduce the radiation / coupling from oscillator circuit,
an isolated ground island on the GND layer could be
made. This ground island can be connected at one point
to the GND layer. This helps to keep noise generated by
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Table 1. Power Control
Power Control
A precise, temperature-compensated voltage reference and
a comparator circuit provides power-control function that
monitors the VCC level. The device is fully accessible and
Supply Condition
Read/Write Powered
Access
By
VCC < VPF, VCC < V
VCC < VPF, VCC > V
VCC > VPF, VCC < V
VCC > VPF, VCC > V
No
V
BAT
BAT
BAT
BAT
BAT
data can be written and read when VCC is greater than V .
PF
No
VCC
However, when VCC falls below V , the internal clock
PF
registers are blocked from any access. If V is less than
Yes
VCC
VCC
PF
V
, the device power is switched from VCC to V
when
BAT
BAT
Yes
VCC drops below V . If V is greater than V , the device
PF
PF
BAT
power is switched from VCC to V
when VCC drops below
BAT
V
. The registers are maintained from the V
source
BAT
BAT
until VCC is returned to nominal levels (Table 1). After VCC
returns above V , read and write access is allowed after
PF
t
(see the “Power-Up/Down Timing” diagram).
REC
Power-up/down Timing
Table 2. Power-up/down Characteristics
Ambient Temperature -40 to +85°C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
ms
Recovery at Power-up
t
(see note below)
2
REC
V
V
Fall Time; V
to V
t
300
0
µs
CC
CC
PF(MAX)
PF(MIN)
VCCF
VCCR
Rise Time; V
to V
t
µs
PF(MIN)
PF(MAX)
Note: This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay
occurs.
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RTC and RAM Address Map
The address map for the RTC and RAM registers shown in Table 3. The RTC registers and control register are located in
address locations 00H to 07H The RAM registers are located in address locations 08H to 3FH. During a multibyte access,
when the register pointer reaches 3FH (the end of RAM space) it wraps around to location 00H (the beginning of the clock
2
space). On an I C START, STOP, or register pointer incrementing to location 00H, the current time and date is transferred to
a second set of registers. The time and date in the secondary registers are read in a multibyte data transfer, while the clock
continues to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read.
Table 3. RTC and RAM Address Map
Address
00H
Bit 7
CH
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
Seconds
Minutes
Range
00 - 59
00 - 59
10 seconds
10 minutes
AM/PM
Seconds
01H
Minutes
Hour
1 - 12
+ AM/PM
00 - 23
02H
0
12/24
10 hour
0
Hours
10 hour
03H
04H
05H
06H
07H
0
0
0
0
0
0
0
0
0
Day
Day
Date
1 - 7
10 date
Date
Month
Year
01 - 31
01 - 12
00 - 99
0
10 month
Month
10 year
OSF
Year
OUT
0
SQWE
0
RS1
RS0
Control
RAM 56 x 8
08H -
3FH
00H - FFH
Note: Bits listed as “0” should always be written and read as 0.
Clock and Calendar
Table 3 shows the address map of the RTC registers. The
time and date information is obtained by reading the
appropriate register bytes. The time and calendar are set or
initialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the BCD
format. Bit 7 of Register 0 is the clock halt (CH) bit. When
this bit is set to 1, the oscillator is disabled. When cleared to
0, the oscillator is enabled. The clock can be halted
whenever the timekeeping functions are not required, which
date registers, the user buffers are synchronized to the
internal registers on any start or stop, and when the address
pointer rolls over to zero. The countdown chain is reset
whenever the seconds register is written. Write transfers
occurs on the acknowledge pulse from the device. To avoid
rollover issues, once the countdown chain is reset, the
remaining time and date registers must be written within one
second. If enabled, the 1 Hz square-wave output transitions
high 500 ms after the seconds data transfer, provided the
oscillator is already running.
decreases V
current.
BAT
The day-of-week register increments at midnight. Values
that correspond to the day of week are user-defined but
must be sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on). Illogical time and date entries result in
undefined operation.
Note that the initial power-on state of all registers,
unless otherwise specified, is not defined. Therefore, it
is important to enable the oscillator (CH = 0) during
initial configuration.
The IDT1338B-31 runs in either 12-hour or 24-hour mode.
Bit 6 of the hours register is defined as the 12-hour or
24-hour mode-select bit. When high, the 12-hour mode is
selected. In the 12-hour mode, bit 5 is the AM/PM bit, with
When reading or writing the time and date registers,
secondary (user) buffers are used to prevent errors when
the internal registers update. When reading the time and
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logic high being PM. In the 24-hour mode, bit 5 is the second
10-hour bit (20–23 hours). If the 12/24-hour mode select is
changed, the hours register must be re-initialized to the new
format.
update of the main registers during a read.
2
On an I C START, the current time is transferred to a second
set of registers. The time information is read from these
secondary registers, while the clock continues to run. This
eliminates the need to re-read the registers in case of an
Table 4. Control Register (07H)
The control register controls the operation of the SQW/OUT pin and provides oscillator status.
Bit #
Name
POR
Bit 7
OUT
1
Bit 6
Bit 5
OSF
1
Bit 4
SQWE
1
Bit 3
Bit 2
Bit 1
RS1
1
Bit 0
RS0
1
0
0
0
0
0
0
Bit 7: Output Control (OUT). Controls the output level of the SQW/OUT pin when the square-wave output is disabled. If SQWE
= 0, the logic level on the SQW/OUT pin is 1 if OUT = 1; it is 0 if OUT = 0.
Bit 5: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time
period and can be used to judge the validity of the clock and calendar data. This bit is edge triggered, and is set to logic 1 when
the internal circuitry senses the oscillator has transitioned from a normal run state to a STOP condition. The following are
examples of conditions that may cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on VCC and VBAT are insufficient to support oscillation.
3) The CH bit is set to 1, disabling the oscillator.
4) External influences on the crystal (i.e., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF to logic 1 leaves
the value unchanged.
Bit 4: Square-Wave Enable (SQWE). When set to logic 1, this bit enables the oscillator output to operate with either VCC or
VBAT applied. The frequency of the square-wave output depends upon the value of the RS0 and RS1 bits.
Bits 1 and 0: Rate Select (RS1 and RS0). These bits control the frequency of the square-wave output when the square-wave
output has been enabled. The table below lists the square-wave frequencies that can be selected with the RS bits.
Table 5. Square Wave Output
OUT
RS1
RS0
SQW Output
1 Hz
SQWE
X
X
X
X
0
0
0
1
1
X
X
0
1
0
1
X
X
1
1
1
1
0
0
4.096 kHz
8.192 kHz
32.768 kHz
0
1
1
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2
acknowledges with a ninth bit.
I C Serial Data Bus
2
The IDT1338B-31 supports the I C bus protocol. A device
that sends data onto the bus is defined as a transmitter and
a device receiving data as a receiver. The device that
controls the message is called a master. The devices that
are controlled by the master are referred to as slaves. The
bus must be controlled by a master device that generates
the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The
Acknowledge: Each receiving device, when addressed, is
obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse. Of course, setup and hold
times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the slave. In
this case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
2
IDT1338B-31 operates as a slave on the I C bus. Within the
bus specifications, a standard mode (100 kHz maximum
clock rate) and a fast mode (400 kHz maximum clock rate)
are defined. The IDT1338B-31 works in both modes.
Connections to the bus are made via the open-drain I/O
lines SDA and SCL.
The following bus protocol has been defined (see the “Data
2
Transfer on I C Serial Bus” figure):
• Data transfer may be initiated only when the bus is not
busy.
• During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH are interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line,
from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop data transfer: A change in the state of the data line,
from LOW to HIGH, while the clock line is HIGH, defines the
STOP condition.
Data valid: The state of the data line represents valid data
when, after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. The data on
the line must be changed during the LOW period of the clock
signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions is
not limited, and is determined by the master device. The
information is transferred byte-wise and each receiver
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2
Data Transfer on I C Serial Bus
Depending upon the state of the R/W bit, two types of data
transfer are possible:
bit (see the “Data Write–Slave Receiver Mode” figure). The
slave address byte is the first byte received after the START
condition is generated by the master. The slave address
byte contains the 7-bit IDT1338B-31 address, which is
1101000, followed by the direction bit (R/W), which is 0 for a
write. After receiving and decoding the slave address byte
the slave outputs an acknowledge on the SDA line. After the
IDT1338B-31 acknowledges the slave address + write bit,
the master transmits a register address to the IDT1338B-31.
This sets the register pointer on the IDT1338B-31, with the
IDT1338B-31 acknowledging the transfer. The master may
then transmit zero or more bytes of data, with the
1) Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after each received byte.
Data is transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is transmitted by
the master. The slave then returns an acknowledge bit. This
is followed by the slave transmitting a number of data bytes.
The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received
byte, a “not acknowledge” is returned. The master device
generates all of the serial clock pulses and the START and
STOP conditions. A transfer is ended with a STOP condition
or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial
transfer, the bus is not released. Data is transferred with the
most significant bit (MSB) first.
IDT1338B-31 acknowledging each byte received. The
address pointer increments after each data byte is
transferred. The master generates a STOP condition to
terminate the data write.
2) Slave Transmitter Mode (Read Mode): The first byte is
received and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates that the
transfer direction is reversed. Serial data is transmitted on
SDA by the IDT1338B-31 while the serial clock is input on
SCL. START and STOP conditions are recognized as the
beginning and end of a serial transfer (see the “Data
Read–Slave Transmitter Mode” figure). The slave address
byte is the first byte received after the START condition is
generated by the master. The slave address byte contains
the 7-bit IDT1338B-31 address, which is 1101000, followed
by the direction bit (R/W), which is 1 for a read. After
receiving and decoding the slave address byte the slave
outputs an acknowledge on the SDA line. The IDT1338B-31
The IDT1338B-31 can operate in the following two modes:
1) Slave Receiver Mode (Write Mode): Serial data and
clock are received through SDA and SCL. After each byte is
received an acknowledge bit is transmitted. START and
STOP conditions are recognized as the beginning and end
of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction
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then begins to transmit data starting with the register
address pointed to by the register pointer. If the register
pointer is not written to before the initiation of a read mode
the first address that is read is the last one stored in the
register pointer. The address pointer is incremented after
each byte is transferred. The IDT1338B-31 must receive a
“not acknowledge” to end a read.
Data Write – Slave Receiver Mode
Data Read (from current Pointer location) – Slave Transmitter Mode
Data Read (Write Pointer, then Read) – Slave Receive and Transmit
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Handling, PCB Layout, and Assembly
The IDT1338B-31 package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions
should be taken to ensure that excessive shocks are avioded. Ultarsonic cleaning equipment should be avioded to prevent
damage to the crystal.
Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line.
All NC (no connect) pins must be connected to ground.
Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label must
be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive device
(MSD) classifications.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT1338B-31. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Voltage Range on Any Pin Relative to Ground
Storage Temperature
Rating
-0.3 V to +6.0 V
-55 to +125° C
260°C
Soldering Temperature
Recommended DC Operating Conditions
(V = V
to V
, TA = -40°C to +85°C, unless otherwise noted. Typical values are at V = 3.3 V,
CC
CC(MIN)
CC(MAX) CC
TA = +25°C, unless otherwise noted.) (Note 1)
Parameter
Symbol
Min.
-40
Typ.
Max.
+85
Units
Ambient Operating Temperature
T
° C
A
V
Input Voltage, Note 2
V
1.3
3.0
3.7
BAT
BAT
Pull-up Resistor Voltage (SQW/OUT), Note 2
Logic 1, Note 2
V
5.5
V
V
V
PU
V
0.7VCC
-0.3
VCC + 0.3
+0.3VCC
IH
Logic 0, Note 2
V
IL
Supply Voltage
IDT1338-18
V
V
1.8
3.3
5.5
5.5
PF
V
V
V
CC
IDT1338-31
PF
Power Fail Voltage
IDT1338-18
1.40
2.45
1.62
2.7
1.71
2.97
V
PF
IDT1338-31
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 11
IDT1338B-31 REV A 112309
IDT1338B-31
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
RTC
DC Electrical Characteristics
(V = V
to V
, TA = -40°C to +85°C, unless otherwise noted. Typical values are at V = 3.3 V,
CC(MAX) CC
CC
CC(MIN)
TA = +25°C, unless otherwise noted.) (Note 1)
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Input Leakage
I
Note 3
Note 4
1
µA
µA
LI
I/O Leakage
I
1
LO
VCC > 2 V; V = 0.4 V
3.0
3.0
3.0
3.0
mA
OL
SDA Logic 0 Output
I
OLSDA
VCC < 2 V; V = 0.2VCC
OL
VCC > 2 V; V = 0.4 V
mA
mA
OL
1.71 V < VCC < 2 V;
SQW/OUT Logic 0 Output
I
V
= 0.2VCC
OLSQW
OL
1.3 V < VCC < 1.71 V;
= 0.2VCC
250
µA
V
OL
IDT1338-18
75
150
200
325
IDT1338-31; VCC < 3.63 V
120
Active Supply Current (Note 5)
Standby Current (Note 6)
I
I
µA
CCA
IDT1338-31; 3.63 V < VCC
5.5 V
<
<
IDT1338-18
60
85
100
125
200
IDT1338-31; VCC < 3.63 V
µA
nA
CCS
IDT1338-31; 3.63 V < VCC
5.5 V
V
Leakage Current (VCC Active)
I
25
100
BAT
BATLKG
DC Electrical Characteristics
(V = 0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at V
= 3.0 V, TA = +25°C, unless
CC
BAT
otherwise noted.) (Note 1)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
V
Current (OSC ON); V
=3.7 V,
=3.7 V,
I
Note 7
800
1200
nA
BAT
BAT
BAT
BATOSC1
SQW/OUT OFF
V
Current (OSC ON); V
I
Note 7
Note 7
1025
10
1400
100
nA
nA
BAT
BATOSC2
SQW/OUT ON
V
Data-Retention Current
I
BATDAT
BAT
(OSC OFF); V
=3.7 V
BAT
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 12
IDT1338B-31 REV A 112309
IDT1338B-31
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
RTC
AC Electrical Characteristics
(V = V
to V
, TA = -40°C to +85°C) (Note 1)
CC(MAX)
CC
CC(MIN)
Parameter
Symbol
Conditions
Min.
100
Typ. Max. Units
SCL Clock Frequency
f
Fast Mode
400
100
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
pF
SCL
Standard Mode
Fast Mode
0
Bus Free Time Between a STOP and
START Condition
t
1.3
BUF
Standard Mode
Fast Mode
4.7
Hold Time (Repeated) START
Condition, Note 8
t
0.6
HD:STA
Standard Mode
Fast Mode
4.0
Low Period of SCL Clock
t
1.3
LOW
Standard Mode
Fast Mode
4.7
High Period of SCL Clock
t
0.6
HIGH
Standard Mode
Fast Mode
4.0
Setup Time for a Repeated START
Condition
t
0.6
SU:STA
Standard Mode
Fast Mode
4.7
Data Hold Time (Notes 9, 10)
t
0
0.9
HD:DAT
Standard Mode
Fast Mode
0
Data Setup Time (Note 11)
t
100
SU:DAT
Standard Mode
Fast Mode
250
Rise Time of Both SDA and SCL
Signals (Note 12)
t
20 + 0.1C
20 + 0.1C
20 + 0.1C
20 + 0.1C
0.6
300
1000
300
R
B
B
B
B
Standard Mode
Fast Mode
Fall Time of Both SDA and SCL Signals
(Note 12)
t
F
Standard Mode
Fast Mode
300
Setup Time for STOP Condition
t
SU:STO
Standard Mode
4.0
Capacitive Load for Each Bus Line
(Note 12)
C
400
10
B
I/O Capacitance (SDA, SCL)
C
Note 13
Note 14
pF
I/O
Oscillator Stop Flag (OSF) Delay
t
100
ms
OSF
WARNING: Negative undershoots below 0.3 V while the device is in battery-backed mode may cause loss
of data.
Note 1: Limits at -40°C are guaranteed by design and are not production tested.
Note 2: All voltages referenced to ground.
Note 3: SCL only.
Note 4: SDA and SQW/OUT.
Note 5: I
—SCL clocking at max frequency = 400 kHz.
CCA
2
Note 6: Specified with the I C bus inactive.
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 13
IDT1338B-31 REV A 112309
IDT1338B-31
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
RTC
Note 7: Measured with a 32.768 kHz crystal on X1 and X2.
Note 8: After this period, the first clock pulse is generated.
Note 9: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
of
IHMIN
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 10: The maximum t
need only be met if the device does not stretch the LOW period (t
) of the SCL
HD:DAT
LOW
signal.
Note 11: A fast-mode device can be used in a standard-mode system, but the requirement t
> to 250 ns must
SU:DAT
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
+
R(MAX)
t
= 1000 + 250 = 1250 ns before the SCL line is released.
SU:DAT
Note 12: C —total capacitance of one bus line in pF.
B
Note 13: Guaranteed by design. Not production tested.
Note 14: The parameter t
is the period of time the oscillator must be stopped for the OSF flag to be set over the
OSF
voltage range of 0.0V < VCC < VCCMAX and 1.3 V < V
< 3.7 V.
BACKUP
Timing Diagram
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 14
IDT1338B-31 REV A 112309
IDT1338B-31
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
RTC
Typical Operating Characteristics
IBAT vs VBAT
(IDT1338-31)
Icc vs Vcc
(IDT1338-31)
734
694
654
614
574
534
494
25
20
15
10
5
SQWE=1
SQWE=0
SCL=400kHz
SCL=0Hz
0
1.3
1.8
2.3
2.8
3.3
2.7
3.2
3.7
4.2
4.7
5.2
VBat (V)
Vcc (V)
Oscillator Frequency vs Supply Voltage
IBAT vs Temperature
32767.950000
32767.900000
32767.850000
32767.800000
32767.750000
800
700
600
500
400
SQWE=1
SQWE=0
Freq
-40
-20
0
20
40
60
80
2.7
3.2
3.7
4.2
4.7
5.2
Temperature (C)
Oscillator Supply Voltage (V)
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 15
IDT1338B-31 REV A 112309
IDT1338B-31
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
RTC
Thermal Characteristics for 8MSOP
Parameter
Symbol
Conditions
Min.
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
Still air
95
° C/W
JA
Thermal Resistance Junction to Case
θ
48
° C/W
JC
Thermal Characteristics for 8SOIC
Parameter
Symbol
Conditions
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
150
140
120
40
° C/W
° C/W
° C/W
° C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
Thermal Characteristics for 16SOIC
Parameter
Symbol
Conditions
Still air
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
120
115
105
58
° C/W
° C/W
° C/W
° C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 16
IDT1338B-31 REV A 112309
IDT1338B-31
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
RTC
Marking Diagram (8 MSOP)
Marking Diagram (16 SOIC)
16
9
38GI
YWW$
IDT
1338BC-31
SRI
#YYWW**$
IDT1338-31DVGI
1
8
Marking Diagram (8 SOIC)
IDT1338BC-31SRI
8
5
IDT1338B
-31DCGI
#YYWW$
1
4
IDT1338B-31DCGI
Notes:
1. ‘#’ is the lot number.
2. ‘$’ is the assembly mark code.
3. YYWW is the last two digits of the year and week that the
part was assembled.
4. “G” denotes RoHS compliant package.
5. “I” denotes industrial grade.
6. Bottom marking: country of origin if not USA.
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 17
IDT1338B-31 REV A 112309
IDT1338B-31
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
RTC
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
8
Symbol
Min
1.35
0.10
0.33
0.19
4.80
3.80
Max
1.75
0.25
0.51
0.25
5.00
4.00
Min
Max
A
A1
B
C
D
E
e
.0532
.0040
.013
.0075
.1890
.1497
.0688
.0098
.020
.0098
.1968
.1574
E
H
INDEX
AREA
1.27 BASIC
0.050 BASIC
1
2
H
h
L
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
.2284
.010
.016
0°
.2440
.020
.050
8°
D
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 18
IDT1338B-31 REV A 112309
IDT1338B-31
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
RTC
Package Outline and Package Dimensions (8-pin MSOP, 3.00 mm Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Min Max
Inches*
8
Symbol
Min
Max
A
A1
A2
b
--
1.10
0.15
0.97
0.38
0.23
--
0.043
0.006
0.038
0.015
0.009
0
0
0.79
0.22
0.08
0.031
0.008
0.003
E1
E
INDEX
AREA
C
D
E
3.00 BASIC
4.90 BASIC
3.00 BASIC
0.65 Basic
0.118 BASIC
0.193 BASIC
0.118 BASIC
0.0256 Basic
E1
e
1
2
L
0.40
0.80
0.016
0.032
D
α
0°
8°
0°
8°
aaa
-
0.10
-
0.004
*For reference only. Controlling dimensions in mm.
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa
C
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 19
IDT1338B-31 REV A 112309
IDT1338B-31
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
RTC
Package Outline and Package Dimensions (16-pin SOIC, 300 mil Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches*
Min Max
16
Symbol
Min
--
Max
2.65
--
2.55
0.51
0.32
10.50
10.65
7.60
A
A1
A2
b
c
D
--
0.104
--
0.10
2.05
0.33
0.18
10.10
10.00
7.40
0.0040
0.081
0.013
0.007
0.397
0.394
0.291
0.100
0.020
0.013
0.413
0.419
0.299
E1
E
INDEX
AREA
E
E1
e
1 2
1.27 Basic
0.050 Basic
D
L
α
0.40
0°
1.27
8°
0.016
0°
0.050
8°
aaa
-
0.10
-
0.004
*For reference only. Controlling dimensions in mm.
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa
C
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 20
IDT1338B-31 REV A 112309
IDT1338B-31
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
RTC
Ordering Information
Part / Order Number
1338B-31DVGI
Marking
see page 17
Shipping Packaging
Tubes
Package
8-pin MSOP
8-pin MSOP
8-pin SOIC
8-pin SOIC
16-pin SOIC
16-pin SOIC
Temperature
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
1338B-31DVGI8
1338B-31DCGI
1338B-31DCGI8
1338BC-31SRI
Tape and Reel
Tubes
Tape and Reel
Tubes
1338BC-31SRI8
Tape and Reel
The IDT1338 packages are RoHS compliant. Packages without the integrated crystal are Pb-free; packages that include the
integrated crystal (as designated with a “C” before the dash number) may include lead that is exempt under RoHS
requirements. The lead finish is JESD91 category e3.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 21
IDT1338B-31 REV A 112309
IDT1338B-31
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
RTC
Revision History
Rev. Originator
LPL
Date
Description of Change
A
11/23/09 New device. Initial release.
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 22
IDT1338B-31 REV A 112309
IDT1338B-31
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
RTC
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www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
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Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
1338BC-31SRI8
Real Time Clock, Non-Volatile, 1 Timer(s), PDSO16, 0.300 INCH, ROHS COMPLIANT, SOIC-16
IDT
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