ICS844002I-01 [ICSI]
FEMTOCLOCKS? CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER; FEMTOCLOCKS ™ CRYSTAL - TO- LVDS频率合成器
| 型号： | ICS844002I-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER |
| 文件： | 总12页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS844002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS844002I-01 is a 2 output LVDS • Two LVDS outputs
Synthesizer optimized to generate Ethernet
ICS
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
HiPerClockS™
reference clock frequencies and is a mem-
ber of the HiPerClocksTM family of high
performance clock solutions from ICS. Using a
• Supports the following output frequencies: 156.25MHz,
125MHz, 62.5MHz
25MHz, 18pF parallel resonant crystal, the following
frequencies can be generated based on the 2 frequency
select pins (F_SEL[1:0]): 156.25MHz, 125MHz and
62.5MHz. The ICS844002I-01 uses ICS’ 3rd generation
low phase noise VCO technology and can achieve <1ps
typical rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS844002I-01 is packaged in a small
20-pin TSSOP package.
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.41ps (typical)
• Full 2.5V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both, standard and RoHS/Lead-Free compliant
packages
PIN ASSIGNMENT
FREQUENCY SELECT FUNCTION TABLE
nc
VDDO
Q0
VDDO
1
20
19
18
17
16
15
14
13
12
11
Output Frequency (MHz)
Q1
2
M Divider N Divider
nQ1
3
(25MHz Reference)
F_SEL1 F_SEL0
Value
Value
GND
VDD
nQ0
MR
4
5
0
0
1
1
0
1
0
1
25
4
156.25
125
nXTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
nPLL_SEL
nc
VDDA
F_SEL0
VDD
6
7
8
9
25
25
5
10
62.5
Not Used
Not Used
10
ICS844002I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
BLOCK DIAGRAM
Pulldown
2
F_SEL[1:0]
Pulldown
nPLL_SEL
Q0
F_SEL[1:0]
0 0 ÷4
nQ0
Pulldown
REF_CLK
1
0
1
0 1 ÷5
25MHz
XTAL_IN
1 0 ÷10
1 1 not used
VCO
Phase
Detector
Q1
625MHz
OSC
0
(w/25MHz
Reference)
nQ1
XTAL_OUT
Pulldown
nXTAL_SEL
M = 25 (fixed)
Pulldown
MR
844002AGI-01
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REV.A JANUARY 5, 2006
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ICS844002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
1, 7
Name
nc
Type
Unused
Description
No connect.
2, 20
3, 4
VDDO
Power
Ouput
Output supply pins.
Q0, nQ0
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
5
MR
Input
Pulldown
Selects between the PLL and REF_CLK as input to the dividers.
6
nPLL_SEL
VDDA
Input
Pulldown When LOW, selects PLL (PLL Enable). When HIGH, deselects the
reference clock (PLL Bypass). LVCMOS/LVTTL interface levels.
8
Power
Input
Power
Input
Input
Analog supply pin.
F_SEL0,
F_SEL1
9, 11
10, 16
12, 13
14
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
VDD
XTAL_OUT,
XTAL_IN
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
REF_CLK
Pulldown LVCMOS/LVTTL clock input.
Selects between crystal or REF_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
15
nXTAL_SEL
Input
17
GND
Power
Output
Power supply ground.
18, 19
nQ1, Q1
Differential output pair. LVDS interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
RPULLDOWN Input Pulldown Resistor
51
kΩ
844002AGI-01
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REV.A JANUARY 5, 2006
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ICS844002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
PackageThermal Impedance, θ
73.2°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD =VDDA =VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.375
2.375
2.375
2.5
2.5
2.5
2.625
2.625
2.625
85
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
9
70
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VDD = 2.5V
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
1.7
VDD + 0.3
0.7
V
V
VDD = 2.5V
-0.3
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
Input
High Current
IIH
VDD = VIN = 2.625V
150
µA
µA
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
Input
Low Current
IIL
VDD = 2.625V, VIN = 0V
-150
TABLE 3C. LVDS DC CHARACTERISTICS, VDD =VDDA =VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOD
Differential Output Voltage
240
550
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
40
1.1
50
0.7
1.5
Δ VOS
VOS Magnitude Change
mV
844002AGI-01
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REV.A JANUARY 5, 2006
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ICS844002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
25
Mode of Oscillation
Frequency
22.4
27.2
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 5. AC CHARACTERISTICS, VDD = VDDA =VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
Minimum Typical Maximum Units
140
112
56
170
136
68
MHz
MHz
MHz
ps
fOUT
Output Frequency
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
5
20
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz,(1.875MHz - 20MHz)
20ꢀ to 80ꢀ
0.41
0.44
0.47
ps
RMS Phase Jitter (Random);
NOTE 3
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
250
48
550
52
ps
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
844002AGI-01
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REV.A JANUARY 5, 2006
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ICS844002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TYPICAL PHASE NOISE AT 156.25MHZ
0
-10
-20
-30
Ethernet Filter
-40
156.25MHz
RMS Phase Jitter (Random)
-50
-60
1.875Mhz to 20MHz = 0.41ps (typical)
-70
-80
-90
-100
-110
-120
Raw Phase Noise Data
-130
-140
-150
-160
-170
Phase Noise Result by adding
Ethernet Filter to raw data
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
844002AGI-01
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REV.A JANUARY 5, 2006
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ICS844002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
VDD,
VDDO
Phase Noise Plot
VDDA
SCOPE
Qx
2.5V 5ꢀ
POWER SUPPLY
Float GND
Phase Noise Mask
LVDS
+
–
nQx
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
2.5V CORE/2.5V OUTPUT LOAD ACTEST CIRCUIT
RMS PHASE JITTER
nQx
Qx
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
Clock
Outputs
20ꢀ
nQy
Qy
tsk(o)
OUTPUT SKEW
PROPAGATION DELAY
VDD
nQ0, nQ1
Q0, Q1
out
out
tPW
tPERIOD
➤
DC Input
LVDS
tPW
odc =
x 100ꢀ
VOS/Δ VOS
tPERIOD
➤
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OFFSETVOLTAGE SETUP
VDD
➤
out
out
LVDS
DC Input
100
V
OD/Δ VOD
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844002AGI-01
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REV.A JANUARY 5, 2006
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ICS844002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS844002I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
2.5V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
below were determined using a 25MHz, 18pF parallel reso-
nant crystal and were chosen to minimize the ppm error.
The ICS844002I-01 has been characterized with 18pF paral-
lel resonant crystals.The capacitor values shown in Figure 2
XTAL_OUT
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
844002AGI-01
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REV.A JANUARY 5, 2006
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ICS844002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS
LVDS
For applications not requiring the use of the crystal oscillator All unused LVDS output pairs can be either left floating or
input, both XTAL_IN and XTAL_OUT can be left floating. terminated with 100Ω across. If they are left floating, we
Though not required, but for additional protection, a 1kΩ recommend that there is no trace attached.
resistor can be tied from XTAL_IN to ground.
REF_CLK INPUT:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
2.5V LVDS DRIVER TERMINATION
Figure 3 shows a typical termination for LVDS driver in
characteristic impedance of 100Ω differential (50Ω single)
transmission line environment. For buffer with multiple LDVS
driver, it is recommended to terminate the unused outputs.
2.5V
2.5V
LVDS_Driver
+
R1
100
-
100Ω Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVERT ERMINATION
844002AGI-01
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REV.A JANUARY 5, 2006
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ICS844002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844002I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844002I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 2.5V + 5ꢀ = 2.625V, which gives worst case results.
·
·
Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 85mA = 223mW
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 2.625V * 70mA = 184mW
Total Power_MAX = 223mW + 184mW = 407mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
qJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming
a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.407W * 66.6°C/W = 112°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θ
JA by Velocity (Meters per Second)
0
200
98.0°C/W
500
88.0°C/W
Single-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
844002AGI-01
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REV.A JANUARY 5, 2006
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ICS844002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOWT ABLE FOR 20 LEAD TSSOP
θ
JA by Velocity (Meters per Second)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC StandardTest Boards
Multi-Layer PCB, JEDEC StandardTest Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS844002I-01 is: 2914
844002AGI-01
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REV.A JANUARY 5, 2006
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ICS844002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
844002AGI-01
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REV.A JANUARY 5, 2006
11
ICS844002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS844002AGI-01
ICS844002AGI-01T
ICS844002AGI-01LF
ICS844002AGI-01LFT
ICS44002AI01
ICS44002AI01
ICS4002AI01L
ICS4002AI01L
20 Lead TSSOP
tube
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
20 Lead TSSOP
2500 tape & reel
tube
20 Lead "Lead-Free" TSSOP
20 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
844002AGI-01
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REV.A JANUARY 5, 2006
12
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