ICS84330BVT [ICSI]
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER; 700MHZ ，低抖动，水晶- TO- 3.3V的差分LVPECL频率合成器
| 型号： | ICS84330BVT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总19页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS84330
Integrated
Circuit
Systems, Inc.
700MH , LOW JITTER, CRYSTAL-TO-3.3V
Z
D
IFFERENTIAL LVPECL FREQUENCY
SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS84330 is a general purpose, single output • Fully integrated PLL, no external loop filter requirements
ICS
high frequency synthesizer and a member of the
HiPerClockS™family of High Performance Clock
• Crystal oscillator interface: 10MHz to 25MHz
Solutions from ICS. The VCO operates at a fre-
• 1 differential 3.3V LVPECL output
HiPerClockS™
• Output frequency range: 25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming M and N dividers
during power-up
quency range of 250MHz to 700MHz.TheVCO and
output frequency can be programmed using the serial or parallel
interfaces to the configuration logic. The output can be config-
ured to divide the VCO frequency by 1, 2, 4, and 8. Output fre-
quency steps from 250KHz to 2MHz can be achieved using a
16MHz crystal depending on the output divider setting.
• RMS Period jitter: 5ps (maximum)
• Cycle-to-cycle jitter: 40ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Pin compatible with the MC12430
• Lead-Free/Annealed package available
• Industrial temperature information available upon request
PIN ASSIGNMENT
BLOCK DIAGRAM
25 24 23 22 21 20 19
OE
XTAL1
S_CLOCK
26
18
N1
N0
M8
M7
M6
M5
M4
1
0
OSC
S_DATA
S_LOAD
27
28
1
17
16
15
14
13
12
XTAL2
ICS84330
28-Lead PLCC
V Package
FREF_EXT
VCCA
FREF_EXT
XTAL_SEL
÷ 16
11.6mm x 11.4mm x 4.1mm
body package
2
XTAL_SEL
3
TopView
XTAL1
4
PLL
PHASE DETECTOR
÷2
÷4
÷8
÷1
5
6
7
8
9 10 11
1
0
FOUT
VCO
÷ 2
nFOUT
TEST
÷ M
S_LOAD
S_DATA
CONFIGURATION
INTERFACE
LOGIC
S_CLOCK
nP_LOAD
32 31 30 29 28 27 26 25
24
1
2
3
4
5
6
7
8
S_CLOCK
S_DATA
S_LOAD
VCCA
n/c
M0:M8
N0:N1
23
22
21
20
19
18
17
N1
N0
M8
M7
M6
M5
M4
ICS84330
32-Lead LQFP
Y package
VCCA
7mm x 7mm x 1.4mm
body package
TopView
FREF_EXT
XTAL_SEL
XTAL1
9
10 11 12 13 14 15 16
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
1
ICS84330
Integrated
Circuit
Systems, Inc.
700MH
Z
, LOW
J
ITTER, CRYSTAL
-TO-3.3V
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER
S
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 6, NOTE 1.
latched and the M divider remains loaded until the next LOW
transition on nP_LOAD or until a serial event occurs.TheTEST
output is Mode 000 (shift register out) when operating in the
parallel input mode.The relationship between theVCO frequency,
the crystal frequency and the M divider is defined as follows:
The ICS84330 features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A quartz crystal is used as the input to the on-chip
oscillator.The output of the oscillator is divided by 16 prior to
the phase detector.With a 16MHz crystal this provides a 1MHz
reference frequency. The VCO of the PLL operates over a
range of 250MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
fxtal
16
x
fVCO =
2M
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are
defined as 125 ≤ M ≤ 350. The frequency out is defined as
follows:
fVCO fxtal 2M
The phase detector and the M divider force the VCO output fre-
quency to be 2M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock.The output of the
VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers.The divider provides a 50% output duty
cycle.
fout
x
=
=
N
N
16
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW.The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider when S_LOAD tran-
sitions from LOW-to-HIGH.The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD.
If S_LOAD is held HIGH, data at the S_DATA input is passed
directly to the M divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and
test bitsT2:T0.The internal registers T2:T0 determine the state
of the TEST output as follows:
The programmable features of the ICS84330 support two input
modes to program the M divider and N output divider.The two
input operational modes are parallel and serial. Figure 1 shows
the timing diagram for each mode. In parallel mode the nP_LOAD
input is LOW.The data on inputs M0 through M8 and N0 through
N1 is passed directly to the M divider and N output divider. On
the LOW-to-HIGH transition of the nP_LOAD input, the data is
T2
0
0
0
0
T1
0
0
1
1
T0
0
1
0
1
TEST Output
fOUT
fOUT
fOUT
fOUT
fOUT
Shift Register Out
High
PLL Reference Xtal ÷ 16
(VCO ÷ M) /2 (non 50% Duty Cycle M divider)
1
0
0
fOUT
fOUT
LVCMOS Output Frequency < 200MHz
1
1
1
0
1
1
1
0
1
Low
(S_CLOCK ÷ M) /2 (non 50% Duty Cycle M divider)
fOUT ÷ 4
fOUT
S_CLOCK ÷ N divider
fOUT
S
ERIAL LOADING
S_CLOCK
S_DATA
T2
T1
T0
N1
N0
M8
M7
M6
M5
M4 M3
M2
M1
M0
t
t
H
S
S_LOAD
nP_LOAD
t
S
P
ARALLEL LOADING
M, N
M0:M8, N0:N1
nP_LOAD
t
t
H
Time
S
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
www.icst.com/products/hiperclocks.html
84330BV
REV. B JULY 26, 2004
2
ICS84330
Integrated
Circuit
Systems, Inc.
700MH
Z
, LOW
J
ITTER, CRYSTAL
-TO-3.3V
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER
S
TABLE 1. PIN DESCRIPTIONS
Name
Type
Description
Analog supply pin.
VCCA
Power
Crystal oscillator interface. XTAL1 is an oscillator input.
XTAL2 is an oscillator output.
XTAL1, XTAL2
Selects between the crystal oscillator or FREF_EXT inputs as the PLL reference
source. Selects XTAL inputs when HIGH. Selects FREF_EXT when LOW.
LVCMOS / LVTTL interface levels.
XTAL_SEL
OE
Input
Input
Input
Pullup
Pullup
Pullup
Output enable. LVCMOS / LVTTL interface levels.
Parallel load input. Determines when data present at M8:M0 is loaded into
M divider, and when data present at N1:N0 sets the N output divide value.
LVCMOS / LVTTL interface levels.
nP_LOAD
M0, M1, M2
M3, M4, M5
M6, M7, M8
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS / LVTTL interface levels.
Input
Pullup
Pullup
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
N0, N1
VEE
Input
Power
Output
Negative supply pins.
Test output which is used in the serial mode of operation.
LVCMOS / LVTTL interface levels.
TEST
VCC
nFOUT, FOUT
nc
Power
Output
Unused
Input
Core supply pins.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Do not connect.
FREF_EXT
Pulldown PLL reference input. LVCMOS / LVTTL interface levels.
Clocks the serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the M divider.
LVCMOS / LVTTL interface levels.
S_CLOCK
S_DATA
Input
Input
Input
Pulldown
Pulldown
S_LOAD
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
3
ICS84330
Integrated
Circuit
Systems, Inc.
700MH , LOW JITTER, CRYSTAL-TO-3.3V
Z
D
IFFERENTIAL LVPECL FREQUENCY
SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
X
X
X
X
X
X
Reset. M and N bits are all set HIGH.
Data on M and N inputs passed directly to M divider and
N output divider. TEST mode 000.
L
↑
Data Data
Data Data
X
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider
and N output divider.
X
L
↑
X
↑
L
X
H
H
X
X
X
X
Data
Data
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divide and N output divide values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
0
64
M6
1
32
M5
1
16
M4
1
8
M3
1
4
M2
1
2
M1
0
1
M0
1
VCO Frequency
(MHz)
M Divide
250
252
254
256
•
125
126
127
128
•
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
696
698
700
348
349
350
1
0
1
0
1
1
1
0
0
1
0
1
0
1
1
1
0
1
1
0
1
0
1
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Frequency (MHz)
N Divider Value
N1
N0
0
Minimum
125
Maximum
350
0
0
1
1
2
4
8
1
1
62.5
175
0
31.25
250
87.5
1
700
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
4
ICS84330
Integrated
Circuit
Systems, Inc.
700MH
Z
, LOW
J
ITTER, CRYSTAL
-TO-3.3V
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER
S
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
CC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Inputs, V
-0.5V to VCC + 0.5 V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
32 Lead LQFP
28 Lead PLCC
JA
47.9°C/W (0 lfpm)
37.8°C/W (0 lfpm)
StorageTemperature, T
-65°C to 150°C
STG
TABLE 4A. DC POWER SUPPLY CHARACTERISTICS, VCC = VCCA = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
ICC
Core Supply Voltage
3.465
3.465
130
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
V
mA
mA
ICCA
15
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
-0.3
M0-M8, N0, N1,
OE, nP_LOAD,
XTAL_SEL
S_LOAD, S_CLOCK
FREF_EXT, S_DATA
M0-M8, N0, N1,
OE, nP_LOAD,
XTAL_SEL
S_LOAD, S_CLOCK
FREF_EXT, S_DATA
V
CC = VIN = 3.465V
5
µA
µA
µA
µA
IIH
Input High Current
VCC = VIN = 3.465V
150
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
-150
IIL
Input Low Current
-5
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
2.6
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VCC/2.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.6
Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 1.0
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
5
ICS84330
Integrated
Circuit
Systems, Inc.
700MH , LOW JITTER, CRYSTAL-TO-3.3V
Z
D
IFFERENTIAL LVPECL FREQUENCY
SYNTHESIZER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Fundamental
Units
Mode of Oscillation
Frequency
10
25
70
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
fIN
Test Conditions
Minimum Typical Maximum Units
XTAL; NOTE 1
10
25
50
MHz
MHz
MHz
Input Frequency S_CLOCK
FREF_EXT; NOTE 2
10
NOTE 1: For the crystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency
range of 250MHz to 700MHz. Using the minimum frequency of 10MHz, valid values of M are 200 ≤ M ≤ 511.
Using the maximum frequency of 25MHz, valid values of M are 80 ≤ M ≤ 224.
NOTE 2: Maximum frequency on FREF_EXT is dependent on the internal M counter limitations. See Application
Information Section for recommendations on optimizing the performance using the FREF_EXT input.
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
700
5
MHz
ps
ps
ps
ns
ns
ns
ns
ns
ms
%
tjit(per)
tjit(cc)
tR / tF
Period Jitter, RMS; NOTE 1, 2
Cycle-to-Cycle Jitter; NOTE 1, 2
Output Rise/Fall Time
40
20% to 80%
200
20
20
20
20
20
600
S_DATA to S_CLOCK
tS
Setup Time S_CLOCK to S_LOAD
M, N to nP_LOAD
S_DATA to S_CLOCK
Hold Time
tH
tL
M, N to nP_LOAD
PLL Lock Time
10
55
55
N ≠ 1
45
45
N = 1, fOUT ≤ 250MHz
%
odc
Output Duty Cycle
N = 1,
40
60
%
250MHz < fOUT ≤ 500MHz
See Parameter Measurement Information section.
Characterized using a XTAL input.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65
NOTE 2: See Applications section.
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
6
ICS84330
Integrated
Circuit
Systems, Inc.
700MH , LOW JITTER, CRYSTAL-TO-3.3V
Z
D
IFFERENTIAL LVPECL FREQUENCY
SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
VOH
SCOPE
VREF
VCC,
VCCA
Qx
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
LVPECL
VEE
nQx
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
PERIOD JITTER
nFOUT
FOUT
80%
80%
VSWING
20%
20%
➤
➤
tcycle n+1
tcycle n
➤
➤
Clock Outputs
t
t
F
R
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
OUTPUT RISE/FALL TIME
nFOUT
FOUT
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
7
ICS84330
Integrated
Circuit
Systems, Inc.
700MH
Z
, LOW
J
ITTER, CRYSTAL
-TO-3.3V
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER
S
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84330 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC and VCCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10µF
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
8
ICS84330
Integrated
Circuit
Systems, Inc.
700MH
Z
, LOW
J
ITTER, CRYSTAL
-TO-3.3V
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER
S
LVCMOS TO XTAL INTERFACE
The XTAL1 input can accept single ended LVCMOS signal ance trace may be required. The input can function with half
swing amplitude. Reducing amplitude from full swing of 3.3V
through an AC couple capacitor. A general interface diagram
is shown in Figure 4.The XTAL2 input can be left floating.The to half swing of about 1.65V can prevent signal interfere with
edge rate can be as slow as 10ns. If the incoming signal has power rail and may reduce noise. Please refer to the LVCMOS
driver data sheet and application note for amplitude reduction
sharp edge rate and the signal path is a long trace, proper
termination for the driver and controlled characteristic imped- and termination approach.
VDD
Q1
C1
XTAL1
0.1uF
LVCMOS_Driver
XTAL2
Crystal Input Interface
Figure 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
50
40
30
20
10
0
Spec Limit
N = 1
200
300
400
500
600
700
Output Frequency (MHz)
FIGURE 5. CYCLE-TO-CYCLE JITTER VS. fOUT (using a 16MHz XTAL)
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
9
ICS84330
Integrated
Circuit
Systems, Inc.
700MH
Z
, LOW
J
ITTER, CRYSTAL
-TO-3.3V
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER
S
LAYOUT GUIDELINE
The schematic of the ICS84330 layout example used in line. The layout in the actual system will depend on the
this layout guideline is shown in Figure 6A. The ICS84330 selected component types, the density of the components,
recommended PCB board layout for this example is shown
in Figure 6B. This layout example is used as a general guide-
the density of the traces, and the stack up of the P.C. board.
C1
X1
C2
SP
SP
16MHz, 18pF
VCC
U1
R7
10
M4
12
13
14
15
16
17
18
4
M4
M5
M6
M7
M8
N0
N1
XTAL1
3
M5
M6
M7
M8
N2
N1
VCC=3.3V
XTAL_SEL
2
1
28
27
26
FREF_EXT
VCCA
S_LOAD
S_DATA
S_CLOCK
VCCA
SP = Space (i.e. not intstalled)
C11
0.01u
C16
10u
M[8:0]= 110010000 (400)
N[1:0] =00 (Divide by 2)
ICS84330
C3
VCC
0.1uF
Zo = 50 Ohm
RU0
SP
RU1
SP
RU7
1K
RU8
1K
RU9
SP
RU10
1K
RU11
SP
RU12
1K
Fout = 200 MHz
+
-
C4
0.1u
Zo = 50 Ohm
R2
50
R1
50
RD0
1K
RD1
1K
RD7
SP
RD8
SP
RD9
1K
RD10
SP
RD6
1K
RD12
SP
R3
50
FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
10
ICS84330
Integrated
Circuit
Systems, Inc.
700MH
Z
, LOW
J
ITTER, CRYSTAL
-TO-3.3V
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER
S
• The differential 50Ω output traces should have the
same length.
The following component footprints are used in this layout
example:
• Avoid sharp angles on the clock trace.Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C3 and C4, as close as pos-
sible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Maximize the power and ground pad sizes and number of vias
capacitors.This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
• Make sure no other signal traces are routed between the
clock trace pair.
CLOCK TRACES AND TERMINATION
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location.While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
4 (XTAL1) and 5 (XTAL2).The trace length between the X1 and
U1 should be kept to a minimum to avoid unwanted parasitic in-
ductance and capacitance. Other signal traces should not be
routed near the crystal traces.
X1
C1
C2
U1
GND
VCC
PIN 2
PIN 1
C16
C11
R7
VCCA
VIA
VCCA
Signals
Traces
C3
C4
50 Ohm
Traces
FIGURE 6B. PCB BOARD LAYOUT FOR ICS84330
www.icst.com/products/hiperclocks.html
84330BV
REV. B JULY 26, 2004
11
ICS84330
Integrated
Circuit
Systems, Inc.
700MH
Z
, LOW
J
ITTER, CRYSTAL
-TO-3.3V
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER
S
JITTER REDUCTION FOR FREF_EXT SINGLE END INPUT
If the FREF_EXT input is driven by a 3.3V LVCMOS driver, the
jitter performance can be improved by reducing the amplitude
swing and slowing down the edge rate. Figure 7A shows an
amplitude reduction approach for a long trace. The swing will
be approximately 0.85V for logic low and 2.5V for logic high
(instead of 0V to 3.3V). Figure 7B shows amplitude reduction
approach for a short trace. The circuit shown in Figure 7C
reduces amplitude swing and also slows down the edge rate
by increasing the resistor value.
VDD
R1
VDD
100
Zo = 50 Ohm
Td
Ro ~ 7 Ohm
VDD
GND
RS
43
R2
100
FREF_EXT
Driver_LVCMOS
FIGURE 7A. AMPLITUDE REDUCTION FOR A LONG TRACE
VDD
VDD
R1
200
Ro ~ 7 Ohm
VDD
GND
RS
100
R2
200
FREF_EXT
Driver_LVCMOS
FIGURE 7B. AMPLITUDE REDUCTION FOR A SHORT TRACE
VDD
VDD
R1
400
Ro ~ 7 Ohm
VDD
GND
RS
200
R2
400
FREF_EXT
Driver_LVCMOS
FIGURE 7C. EDGE RATE REDUCTION BY INCREASING THE RESISTOR VALUE
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
12
ICS84330
Integrated
Circuit
Systems, Inc.
700MH
Z
, LOW
J
ITTER, CRYSTAL
-TO-3.3V
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER
S
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84330.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84330 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 145mA = 502.4mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 1 * 30.2mW = 30.2mW
Total Power_MAX (3.465V, with all outputs switching) = 502.4 + 30.2mW = 532.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W perTable 9A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.533W * 31.1°C/W = 86.6°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 9A. THERMAL RESISTANCE θJA FOR 28-PIN PLCC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8°C/W
31.1°C/W
28.3°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 9B. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
13
ICS84330
Integrated
Circuit
Systems, Inc.
700MH
Z
, LOW
J
ITTER, CRYSTAL
-TO-3.3V
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER
S
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in the Figure 8.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 1.0V
OH_MAX
CC_MAX
)
= 1.0V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
L
CC
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
Pd_L = [(V – (V - 2V))/R ] * (V
))
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
14
ICS84330
Integrated
Circuit
Systems, Inc.
700MH
Z
, LOW
J
ITTER, CRYSTAL
-TO-3.3V
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER
S
RELIABILITY INFORMATION
TABLE 10A. θJAVS. AIR FLOW PLCC TABLE FOR 28 LEAD PLCC
θJA by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8°C/W
31.1°C/W
28.3°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 10B. θJAVS. AIR FLOW LQFP TABLE FOR 32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84330 is: 4442
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
15
ICS84330
Integrated
Circuit
Systems, Inc.
700MH
Z
, LOW
J
ITTER, CRYSTAL
-TO-3.3V
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER
S
PACKAGE OUTLINE - V SUFFIX FOR 28 LEAD PLCC
TABLE 11A. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
28
4.19
2.29
4.57
3.05
A1
A2
b
1.57
2.11
0.33
0.53
c
0.19
0.32
D
12.32
11.43
4.85
12.57
11.58
5.56
D1
D2
E
12.32
11.43
4.85
12.57
11.58
5.56
E1
E2
Reference Document: JEDEC Publication 95, MS-018
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
16
ICS84330
Integrated
Circuit
Systems, Inc.
700MH
Z
, LOW
J
ITTER, CRYSTAL
-TO-3.3V
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER
S
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 11B. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
17
ICS84330
Integrated
Circuit
Systems, Inc.
700MH
Z
, LOW
J
ITTER, CRYSTAL
-TO-3.3V
D
IFFERENTIAL LVPECL FREQUENCY YNTHESIZER
S
TABLE 12. ORDERING INFORMATION
Part/Order Number
ICS84330BV
Marking
Package
Count
38 per Tube
500
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS84330BV
ICS84330BV
ICS84330BY
ICS84330BY
ICS84330BYLN
28 Lead PLCC
ICS84330BVT
ICS84330BY
28 Lead PLCC on Tape and Reel
32 Lead LQFP
250 per Tray
1000
ICS84330BYT
ICS84330BYLN
32 Lead LQFP on Tape and Reel
32 Lead "Lead Free/Annealed" LQFP 250 per Tray
32 Lead "Lead Free/Annealed" LQFP
ICS84330BYLNT
ICS84330BYLN
1000
0°C to 70°C
on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
18
ICS84330
Integrated
Circuit
Systems, Inc.
700MH , LOW JITTER, CRYSTAL-TO-3.3V
Z
D
IFFERENTIAL LVPECL FREQUENCY
SYNTHESIZER
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
2
5
Switched S_DATA and S_CLOCK labels in Figure 1, CLK_EN Timing Diagram.
DC Power Supply table - changed ICC Parameter to read Power.. from Core...
Added "LVCMOS to XTAL Interface" section.
T4A
A
1/23/03
3/24/03
9
10
Figure 7A Schematic Layout - revised, changed N[1:0]-01 to N[1:0}=00.
Added C1 value (18p) and C2 value (22p).
Block Diagram, replaced N with values.
Deleted Crystal Input Interface section; external tune up capacitor not required.
Revised Figure 6A, Schematic of Recommended Layout diagram.
General Description & Features - changed VCO min. from 200MHz to 250MHz
and replaced throughout the datasheet in (Functional Description pg2,
T3C Program. Output Divider Func. Table pg4, and T6 Input Freq Charac. pg6).
1
8
10
1
A
T2
3
4
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
B
B
5/5/03
T3B
Prog. VCO Freq. Func. Table - replaced VCO Frequency 200MHz to 206MHz
with 250MHz to 256MHz. Replaced M Divide 100 to 103 to 125 to 128.
Adjusted Logic High and Logic Low data.
5
Absolute Maximum Rating - changed Outputs VO and rating to IO with Continous
and Surge ratings.
Ordering Information Table - added "Lead Free/Annealed" part number.
Updated format throughout data sheet.
T12
18
7/26/04
84330BV
www.icst.com/products/hiperclocks.html
REV. B JULY 26, 2004
19
相关型号：
ICS84330CV
Clock Generator, 700MHz, PQCC28, 11.60 X 11.40 MM, 4.10 MM HEIGHT, PLASTIC, MS-018, LCC-28
IDT
©2020 ICPDF网 联系我们和版权申明