AV9173-15CN08 [ICSI]
Video Genlock PLL; 视频同步锁相PLL
| 型号： | AV9173-15CN08 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Video Genlock PLL |
| 文件： | 总6页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AV9173 -15
Integrated
Circuit
Systems, Inc.
Video Genlock PLL
General Description
Features
The AV9173-15 provides the analog circuit blocks required
for implementing a video genlock dot (pixel) clock
generator. It contains a phase detector, charge pump, loop
filter, and voltage-controlled oscillator (VCO). By grouping
these critical analog blocks into one IC and utilizing
external digital functions, performance and design
flexibility are optimized as are development time and
system cost.
•
•
•
Phase-detector/VCO circuit block
Ideal for genlock system
Reference clock range 12 kHz to 1MHz
(see specification of output clock range)
•
•
Output clock range 0.625 to 37.5 MHz for CLK1,
depending on input conditions (see Table 1) on page 2.
Provides h-sync capability with CLK1 outputs
15 to 37.5 MHz for 15kHz input
•
•
•
•
On-chip loop filter
When used with an external clock divider, the AV9173-15
forms a Phase-Locked Loop configured as a frequency
synthesizer. The AV9173-15 is designed to accept video
horizontal synchronization (h-sync) pulses and produce a
video dot clock. A separated, negative-going sync input
reference pulse is required at pin 2 (IN).
Single 5 volt power supply
Low power CMOS technology
Small 8-pin DIP or SOIC package
The AV9173-15 is also suited for other clock recovery
applications in such areas as data communications.
Block Diagram
AV9173-15RevC051397P
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
AV9173-15
Pin Configuration
8-Pin DIP or SOIC
Pin Descriptions
PIN
NUMBER
PIN NAME
TYPE
DESCRIPTION
1
2
3
4
5
6
7
8
FBIN
IN
GND
FS0
Input
Input
—
Input
Input
Output
—
Feedback Input
Input for reference sync pulse
Ground
Internal VCO divider select input
Output Enable
Clock Output 1
OE
CLK1
VDD
CLK2
Power Supply (+5V)
Clock Output 2 (Divided-by-2 from Clock 1)
Output
Table 1: Allowable Input Frequency to Output Frequency (Outputs in MHz)
f
OUT for FS = 0 (MHz)
fOUT for FS = 1 (MHz)
f
IN (kHz)
CLK1 Output
22.0 to 37.5
15 to 37.5
12.5 to 37.5
7.5 to 37.5
5.0 to 37.5
CLK2 Output
11.0 to 18.75
7.5 to 18.75
6.25 to 18.75
3.75 to 18.75
2.5 to 18.75
CLK1 Output
CLK2 Output
2.75 to 4.6875
1.875 to 4.6875
1.5625 to 4.6875
0.9375 to 4.6875
0.625 to 4.6875
5.5 to 9.375
12 ≤ fIN ≤ 14 kHz
14 < fIN ≤ 17 kHz
17 < fIN ≤ 30 kHz
30 < fIN ≤ 35 kHz
35 < fIN ≤ 1000 kHz
3.75 to 9.375
3.125 to 9.375
1.875 to 9.375
1.25 to 9.375
2
AV9173-15
Using the AV9173-15
Most video sources, such as video cameras, are asynchronous, The output hook-up of the AV9173-15 is dictated by the
free-running devices. To digitize video or synchronize one desired dot clock frequency. The primary consideration is the
video source to another free-running reference video source, a internal VCO which operates over a frequency range of
video “genlock” (generator lock) circuit is required. The 10 MHz to 75 MHz. Because of the selectable VCO output
AV9173-15 integrates the analog blocks which make the task divider and the additional divider on output CLK2, four
much easier.
distinct output frequency ranges can be achieved. The
following Table lists these ranges and the corresponding
device configuration.
In the complete video genlock circuit, the primary function of
the AV9173-15 is to provide the analog circuitry required to
generate the video dot clock within a PLL. This application is
illustrated in Figure 1. The input reference signal for this
circuit is the horizontal synchronization (h-sync) signal. If a
composite video reference source is being used, the h-sync
pulses must be separated from the composite signal. A video
sync separator circuit, such as the National Semiconductor
LM1881, can be used for this purpose.
FS0 State
Output Used
Frequency Range
0
0
1
1
CLK1
CLK2
CLK1
CLK2
5 - 37.5 MHz
2.5 - 18.75 MHz
1.25 - 9.375 MHz
0.625 - 4.6875 MHz
Note that both outputs, CLK1 and CLK2, are available during
operation even though only one is fed back via the external
clock divider.
The clock feedback divider shown in Figure 1 is a digital
divider used within the PLL to multiply the reference
frequency. Its divide ratio establishes how many video dot
clock cycles occur per h-sync pulse. For example, if 880 pixel Pin 5, OE, tristates both CLK1 and CLK2 upon logic low
clocks are desired per h-sync pulse, then the divider ratio is set input. This feature can be used to revert dot clock control to
to 880. Hence, together the h-sync frequency and external the system clock when not in genlock mode (hence, when in
divider ratio establish the dot clock frequency:
OUT = fIN • N where N is external divide ratio
Both AV9173-15 input pins IN and FBIN respond only to
genlock mode the system dot clock must be tristated).
When unused, inputs FS0 and OE must be tied to either GND
(logic low) or VDD (logic high).
f
negative-going clock edges of the input signal. The h-sync For further discussion of VCO/PLL operation as it applies to
signal must be constant frequency in the 12 kHz to 1MHz the AV9173-15, please refer to the AV9170 application note.
range and stable (low clock jitter) for creation of a stable The AV9170 is a similar device with fixed feedback dividers
output clock.
for skew control applications.
Figure 1: Typical Application of AV9173-15 in a Video Genlock System
3
AV9173-15
Absolute Maximum Ratings
VDD (referenced to GND). . . . . . . . . . . . . . . . 7.0V
Operating Temperature under Bias . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . – 65°C to +150°C
Voltage on I/O pins referenced to GND . . . . . GND –0.5V to VDD + 0.5V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . 0.5 watts
Stresses above those listed under Absolute Maximum Ratings above may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Electrical Characteristic
VDD = +5V ±5%, TA = 0°C to 70°C, unless otherwise stated
DC CHARACTERISTICS
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage1
VIL
VIH
IIL
IIH
VOL
VDD = 5V
VDD = 5V
VIN = 0V
VIN = VDD
IOL = 8mA
—
2.0
-5
-5
—
—
—
—
—
—
0.8
—
—
5
V
V
µA
µA
V
0.4
IOH = -1mA,
VDD = 5.0V
Output High Voltage1
VOH1
VDD -.4V
—
—
V
IOH = -4mA,
VDD = 5.0V
IOH = -8mA
Output High Voltage1
Output High Voltage1
Supply Current
VOH2
VDD -.8V
—
—
V
VOH3
IDD
2.4
—
—
20
—
50
V
mA
Unloaded, 50 MHZ
Notes:
1. Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
AV9173-15
Electrical Characteristics
VDD = +5V ±5%, TA = 0°C to 70°C, unless otherwise stated
AC CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
Input Clock Rise Time1
Input Clock Fall Time1
Output Rise Time1
Rise time1
Output Fall time1
Fall time1
ICLK
ICLK
—
—
—
—
—
0.6
10
10
1.5
ns
ns
ns
r
f
tr1
tr2
tf1
tf2
15pF load; 0.8 to 2.0V
15pF load;
20% to 80% VDD
15pF load; 2.0 to 0.8V
15pF load;
80% to 20% VDD
15pF load, VT H =1.4V
CLK1 freq.≥ 12.5 MHz
CLK1 freq.≥12.5 MHz
CLK1 freq.< 12.5 MHz
CLK1 freq.< 12.5 MHz
—
—
—
1.3
0.6
0.7
3.0
1.5
2.0
ns
ns
ns
Output Duty Cycle1
dt
40
—
—
-400
—
—
12.0
22.0
15.0
12.5
7.5
47
120
—
±250
—
±4
—
—
—
55
250
1
400
2
%
ps
%
ps
%
Jitter,1 1 sigma
T1s1
T1s2
Tabs1
Tabs2
TLabs
fi1
Jitter,1 1 sigma
Jitter,1 1 absolute
Jitter,1 1 absolute
Line-to-line jitter,1 absolute2
Input Frequency,1 IN or FBIN
—
ns
fVCO
1000
37.5
37.5
37.5
37.5
37.5
kHz
MHz
MHz
MHz
MHz
MHz
10 to 75 MHz
12 ≤ fi ≤ 14 kHz
14 < fi ≤ 17 kHz
17 < fi ≤ 30 kHz
30 < fi ≤ 35 kHz
35 < fi ≤ 1000 kHz
CLK1 Frequency3
fCLK1
—
—
—
5.0
Notes:
1. Parameter is guaranteed by design and characterization. Not 100% tested in production.
2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical pixels.
3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4.
5
AV9173-15
8-Pin DIP PACKAGE
8-Pin SOIC PACKAGE
Ordering Information
AV9173-15CN08 - or - AV9173-15CS08
Example:
XXX XXXX - PPP M X#W
Lead Count & Package Width
Lead Count = 1, 2 or 3 digits
W = 0.3" SOIC or 0.6" DIP; None = Standard Width
Package Type
N = DIP (Plastic)
S = SOIC
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
PRODUCT PREVIEW documents contain information on products in the formative or
design phase development. Charactersitic data and other specifications are design goals.
ICS reserves the right to change or discontinue these procucts without notice.
6
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