MK2069-01 [ICSI]
VCXO-Based Line Card Clock Synchronizer; VCXO ，基于线卡时钟同步
| 型号： | MK2069-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | VCXO-Based Line Card Clock Synchronizer |
| 文件： | 总19页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MK2069-01
VCXO-Based Line Card Clock Synchronizer
Description
Features
The MK2069-01 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that offers system
synchronization, jitter attenuation, and frequency
multiplication or translation. It can accept an unstable,
jittery input clock and provide a de-jittered, low phase
noise output clock at a user determined frequency. The
device’s clock multiplication ratios are user selectable
since all major PLL divider blocks can be configured
through device pin settings. External PLL loop filter
components allow tailoring of the VCXO PLL loop
response and therefore the clock jitter attenuation
characteristics.
• Input clock frequency of 1kHz to 170MHz
• Output clock frequency of 500kHz to 160MHz
• Jitter attenuation of input clock provided by VCXO
circuit. Jitter transfer characteristics user configured
through selection of external loop filter components.
• 3:1 Input MUX for input reference clocks
• PLL lock status output
• PLL Clear function allows seamless synchronizing to
an altered input clock phase, virtually eliminating the
generation of wander or extra clock cycles.
• VCXO-based clock generation offers very low jitter
and phase noise generation, even with a low
frequency or jittery input clock.
• 2nd PLL provides translation of VCXO PLL output
(VCLK) to higher or alternate clock frequencies
(TCLK).
The MK2069-01 is ideal for line card applications. Its
three input MUX enables selection of the master or
slave (backup) system clocks, as well as a backup local
line card clock. The lock detector (LD) output serves as
a clock status monitor. The clear (CLR) input enables
rapid synchronization to the phase of a newly selected
input clock, while eliminating the generation of extra
clock cycles and wander caused by memory in the PLL
feedback divider. CLR also serves as a temporary
holdover function when kept low.
• Device will free-run in the absence of an input clock
based on the VCXO crystal frequency.
• 56 pin TSSOP package
• Single 3.3V power supply
• 5V tolerant inputs on ICLK0 and ICLK1
Block Diagram
Pullable
xtal
RV1:0
SV2:0
RT1:0
ST1:0
VDD
2
3
2
2
4
ISET
LF
LFR
X1
X2
VCLK
OEV
Phase
Detector
0X
10
01
ICLK0
ICLK1
ICLK2
SV
RV
Divider
1,2,4,128
RT
Divider
1-4
ST
Divider
2,4,8,16
Divider
1,2,4,6,8,
10,12,16
VCXO
VCO
TCLK
OET
Charge
Pump
FT Divider
1-64
FV Divider
1-4096
2
Translator
PLL
VCXO
PLL
MX1:0
RCLK
Lock Detector
OER
LD
CLR
OEL
12
FV11:0
LDC
LDR
6
4
FT5:0
GND
MDS 2069-01 H
1
Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
VCXO PLL Feedback Divider Selection
Pin Assignment
FV11:0 FV Divider Ratio
Notes
ST0
ST1
RT0
RT1
FT0
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SV2
0...00
0...01
:
1...10
1...11
2
3
2
SV1
For FV addresses 0 to 4094,
FV Divide = Address + 2
3
SV0
:
4096
1
4
RV1
5
MX0
ICLK1
OEL
OET
OEV
OER
VDD
LD
FT1
6
FT2
7
VCXO PLL Scaling Divider Selection Table
SV2 SV1 SV0 SV Divider Ratio
FT3
8
FT4
9
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4
6
8
10
12
2
16
1
FT5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
RV0
VDDT
GNDT
X1
TCLK
VDDP
VCLK
GNDP
RCLK
LDR
VDDV
X2
GNDV
LFR
LF
GND
LDC
Translator PLL Reference Divider Selection
Table
RT1 RT0 RT Divider Ratio
ISET
FV0
FV1
FV2
FV3
FV4
FV5
FV6
FV7
CLR
ICLK0
ICLK2
MX1
FV11
FV10
FV9
0
0
1
1
0
1
0
1
2
3
4
1
Translator PLL Feedback Divider Selection
FV8
FT5:0
FT Divider
Notes
Ratio
2
3
Input Selection Tables
000000
000001
:
111110
111111
For FT addresses 0 to 62,
FT Divide = Address + 2
Input Mux Selection Table
MX1 MX0 Input Selection
:
64
1
0
0
1
1
0
1
0
1
ICLK0
ICLK0
ICLK1
ICLK2
Translator PLL Scaling Divider Selection Table
ST1 ST0 ST Divider Ratio
0
0
1
1
0
1
0
1
2
4
8
16
VCXO PLL Reference Divider Selection Table
RV1 RV0 RV Divider Ratio
0
0
1
1
0
1
0
1
4
128
2
1
MDS 2069-01 H
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Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
Pin Descriptions
Pin
Pin
Pin
Pin Description
Number
Name
Type
1
ST0
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Power
Scaling Divider bit 0 input, Translator PLL (internal pull-up).
Scaling Divider bit 1 input, Translator PLL (internal pull-up).
Reference Divider bit 0 input, Translator PLL (internal pull-up).
Reference Divider bit 1 input, Translator PLL (internal pull-up).
Feedback Divider bit 0 input, Translator PLL (internal pull-up).
Feedback Divider bit 1 input, Translator PLL (internal pull-up).
Feedback Divider bit 2 input, Translator PLL (internal pull-up).
Feedback Divider bit 3 input, Translator PLL (internal pull-up).
Feedback Divider bit 4 input, Translator PLL (internal pull-up).
Feedback Divider bit 5 input, Translator PLL (internal pull-up).
Reference Divider bit 0 input, VCXO PLL (internal pull-up).
Power Supply connection for translator PLL.
2
ST1
3
RT0
4
RT1
5
FT0
6
FT1
7
FT2
8
FT3
9
FT4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
FT5
RV0
VDDT
GNDT
X1
Ground Ground connection for translator PLL.
-
Power
-
Crystal oscillator input. Connect this pin to the external reference crystal.
Power Supply connection for VCXO PLL.
VDDV
X2
Crystal oscillator output. Connect this pin to the external reference crystal.
GNDV
LFR
LF
Ground Ground connection for VCXO PLL.
-
Loop filter connection, reference node. Refer to loop filter circuit on page 6.
Loop filter connection, active node. Refer to loop filter circuit on page 6.
Charge pump current setting input. Refer to loop filter circuit on page 6.
Feedback Divider bit 0 input, VCXO PLL (internal pull-up).
Feedback Divider bit 1 input, VCXO PLL (internal pull-up).
Feedback Divider bit 2 input, VCXO PLL (internal pull-up).
Feedback Divider bit 3 input, VCXO PLL (internal pull-up).
Feedback Divider bit 4 input, VCXO PLL (internal pull-up).
Feedback Divider bit 5 input, VCXO PLL (internal pull-up).
Feedback Divider bit 6 input, VCXO PLL (internal pull-up).
Feedback Divider bit 7 input, VCXO PLL (internal pull-up).
Feedback Divider bit 8 input, VCXO PLL (internal pull-up).
Feedback Divider bit 9 input, VCXO PLL (internal pull-up).
Feedback Divider bit 10 input, VCXO PLL (internal pull-up).
Feedback Divider bit 11 input, VCXO PLL (internal pull-up).
Input MUX selection bit 1 (internal pull-up).
-
ISET
FV0
-
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
-
FV1
FV2
FV3
FV4
FV5
FV6
FV7
FV8
FV9
FV10
FV11
MX1
ICLK2
ICLK0
CLR
LDC
GND
LDR
RCLK
GNDP
Reference clock input 2.
Reference clock input 0. 5V tolerant input.
Clear input, clears VCXO PLL dividers when low (internal pull-up).
Lock detector threshold setting circuit connection. Refer to circuit on page 10.
Ground Digital ground connection.
-
Lock detector threshold setting circuit connection. Refer to circuit on page 10.
Output VCXO PLL phase detector Reference Clock output.
Ground Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR).
MDS 2069-01 H
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Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
Pin
Pin
Pin
Pin Description
Number
Name
Type
42
43
44
45
46
47
48
49
VCLK
VDDP
TCLK
LD
Output Clock output from VCXO PLL
Power
Power Supply connection for output drivers (VCLK, TCLK, RCLK, LD, LDR).
Output Clock output from Translator PLL
Output Lock detector output.
VDD
OER
OEV
OET
Power
Input
Input
Input
Power Supply connection for digital circuitry.
Output enable for RCLK. RCLK is tri-stated when low (internal pull-up).
Output enable for VCLK. VCLK is tri-stated when low (internal pull-up).
Output enable for TCLK. TCLK is tri-stated and the translator PLL is disabled
when low (internal pull-up).
50
51
52
53
54
55
56
OEL
ICLK1
MX0
RV1
Input
Input
Input
Input
Input
Input
Input
Output enable for LD and LDR. Both are tri-stated when low (internal pull-up).
Reference clock input 1. 5V tolerant input.
Input MUX selection bit 0 input (internal pull-up).
Reference Divider bit 1 input, VCXO PLL (internal pull-up).
Scaler Divider bit 0 input, VCXO PLL (internal pull-up).
Scaler Divider bit 1 input, VCXO PLL (internal pull-up).
Scaler Divider bit 2 input, VCXO PLL (internal pull-up).
SV0
SV1
SV2
Functional Description
The MK2069-01 is a PLL (phase locked loop) based
clock generator that generates output clocks
synchronized to an input reference clock. It contains
two cascaded PLL’s with user selectable divider ratios.
The divide values of the divider blocks within both PLLs
are set by device pin configuration. This enables the
system designer to define the following:
• Input clock frequency
• VCXO crystal frequency
• VCLK output frequency
The first PLL is VCXO-based and uses an external
pullable crystal as part of the normal “VCO” (voltage
controlled oscillator) function of the PLL. The use of a
VCXO assures a low phase noise clock source even
when a low PLL loop bandwidth is implemented. A low
loop bandwidth is needed when the input reference
frequency is low, or when jitter attenuation of the input
reference is desired.
• RCLK output frequency, which is also the phase
detector frequency of the VCXO PLL.
• TCLK output frequency
Any unused clock or logic outputs can be tri-stated to
reduce interference (jitter, phase noise) on other clock
outputs. Outputs can also be tri-stated for system
testing purposes.
The second PLL is used to translate or multiply the
frequency of the VCXO PLL which has a maximum
output frequency of 27 MHz. This second PLL, or
Translator PLL, uses an on-chip VCO circuit that can
provide an output clock up to 160 MHz. The Translator
PLL uses a high loop bandwidth (typically greater than
1 MHz) to assure stability of the VCO clock output. It
requires a stable, high frequency input reference which
is provided by the VCXO PLL.
External components are used to configure the VCXO
PLL loop response. This serves to maximize loop
stability and to achieve the desired input clock jitter
attenuation characteristics.
MDS 2069-01 H
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Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
Application Information
The MK2069-01 is a mixed analog / digital integrated
circuit that is sensitive to PCB (printed circuit board)
layout and external component selection. Used
properly, the device will provide the same high
performance expected from a canned VCXO-based
hybrid timing device, but at a lower cost. To help avoid
unexpected problems, the guidance provided in the
sections below should be followed.
Setting TCLK Output Frequency
The clock frequency of TCLK is determined by:
FT Divider
RT Divider
---------------------------
f(TCLK) =
Where:
× f(VCLK)
FT Divider = 1 to 64
RT Divider = 1 to 4
Setting VCLK Output Frequency
The frequency range of TCLK is set by the operational
range of the internal VCO circuit and the output divider
selections:
The frequency of the VCLK output is determined by the
following relationship:
f(VC0)
ST Divider
FV Divider
RV Divider
f(TCLK) = ----------------------
----------------------------
f(VCLK) =
Where:
× f(ICLK)
Where:
f(VCO) = 40 to 320 MHz
ST Divider = 2,4,8 or 16
FV Divider = 1 to 4096
RV Divider = 1,2,4 or 128
A higher VCO frequency will generally produce lower
phase noise and therefore is preferred.
The operational frequency range of VCLK is set by the
allowable frequency range of the external VCXO
crystal and by the internal VCXO divider selections:
MK2069-01 Loop Response and JItter
Attenuation Characteristics
The MK2069-01 will reduce the transfer of phase jitter
existing on the input reference clock to the output clock.
This operation is known as jitter attenuation. The
low-pass frequency response of the VCXO PLL loop is
the mechanism that provides input jitter attenuation.
Clock jitter, more accurately called phase jitter, is the
overall instability of the clock period which can be
measured in the time domain using an oscilloscope, for
instance. Jitter is comprised of phase noise which can
be represented in the frequency domain. The phase
noise of the input reference clock is attenuated
according to the VCXO PLL low-pass frequency
response curve. The response curve, and thus the jitter
attenuation characteristics, can be established through
the selection of external MK2069-01 passive
f(VCXO)
SV Divider
f(VCLK) = -----------------------
Where:
F(VCXO) = F(External Crystal) = 8 to 27 MHz
SV Divider = 1,2,4,6,8,10,12 or 16
A higher crystal frequency will generally produce lower
phase noise and therefore is preferred. A crystal
frequency between 13.5 MHz and 27 MHz is
recommended.
Because VCLK is generated by the external crystal, the
frequency range of VCLK in a given configuration is
limited to the pullable range of the crystal. This is
guaranteed to be +/-115 ppm minimum. This frequency
range in ppm also applies to the input clock and other
clock outputs if the device is to remain frequency
locked to the input, which is required for normal
operation.
components and other device setting as explained in
the following section.
MDS 2069-01 H
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Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
Setting the VCXO PLL Loop Response.
External VCXO PLL Components
The VCXO PLL loop response is determined both by
fixed device characteristics and by other characterizes
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
set by the user. This includes the values of R , C , C
S
S
P
and R
as shown in the External VCXO PLL
SET
Components figure on this page.
DON'T STUFF
Refer to "Crystal Tuning Load
Capacitors" Section
The VCXO PLL loop bandwidth is approximated by:
RS × ICP × KO
NBW(VCXO PLL) = --------------------------------------------------------------------------
2π × SV Divider × FV Divider
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Optional
Crystal Tuning
Capacitors
Where:
CL
R = Value of resistor R in loop filter in Ohms
XTAL
S
S
X1
I
= Charge pump current in amps
CP
(see table on page 7)
X2
K = VCXO Gain in Hz/V
O
CL
LFR
LF
ISET
(see table on page 8)
SV Divider = 1,2,4,6,8,10,12 or 16
FV Divider = 1 to 4096
CS
RS
CP
The above equation calculates the “normalized” loop
bandwidth (denoted as “NBW”) which is approximately
equal to the - 3dB bandwidth. NBW does not take into
account the effects of damping factor or the second
RSET
pole imposed by C . It does, however, provide a useful
P
approximation of filter performance.
To prevent jitter on VCLK due to modulation of the
VCXO PLL by the phase detector frequency, the
following general rule should be observed:
In general, the loop damping factor should be 0.7 or
greater to ensure output stability. A higher damping
factor will create less peaking in the passband and will
further ensure output stability with the presence of
system and power supply noise. A damping factor of 4
will ensure a passband peak less then 0.2dB which
may be required for network clock wander transfer
compliance. A higher damping factor may also increase
output clock jitter when there is excess digital noise in
the system application, due to the reduced ability of the
PLL to respond to and therefore compensate for phase
noise ingress.
f(Phase Detector)
--------------------------------------
NBW(VCO PLL) ≤
.
20
The PLL loop damping factor is determined by:
RS
-----
2
ICP × CS × KO
DF(VCLK) =
×
--------------------------------------------------------------
SV Divider × FV Divider
Where:
C = Value of capacitor C in loop filter in
S
S
Farads
Notes on setting the value of C
P
As another general rule, the following relationship
should be maintained between components C and C
S
P
in the loop filter:
C
S
C = -----
P
20
MDS 2069-01 H
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MK2069-01
Line Card Clock Synchronizer
C establishes a second pole in the VCXO PLL loop
filter. For higher damping factors (> 1), calculate the
hit the supply or ground rail resulting in non-linear loop
response.
P
value of C based on a C value that would be used for
a damping factor of 1. This will minimize baseband
peaking and loop instability that can lead to output jitter.
P
S
The best way to set the value of C is to use the filter
response software available from ICS (please refer to
P
the following section). C should be increased in value
P
C also dampens VCXO input voltage modulation by
until it just starts affecting the passband peak.
P
the charge pump correction pulses. A C value that is
P
too low will result in increased output phase noise at
the phase detector frequency due to this. In extreme
cases where input jitter is high, charge pump current is
Loop Filter Response Software
Online tools to calculate loop filter response can be
found at www.icst.com.
high, and C is too small, the VCXO input voltage can
P
Graph of Charge Pump Current vs. Value of R
(external resistor)
SET
1E-3
100E-6
10E-6
100E+3
1E+6
RSET, ohms
10E+6
Recommended Range
of Operation
problems, output clock cycle slips, or low frequency
phase noise.
Charge Pump Current, Example Settings
from Above Graph
As can be seen in the loop bandwidth and damping
factor equations or by using the filter response software
available from ICS, increasing charge pump current
RSET
Charge Pump Current
(ICP
)
5 MΩ
3 MΩ
25 µA
42 µA
(I ) increases both bandwidth and damping factor.
CP
2 MΩ
65 µA
1 MΩ
125 µA
255 µA
300 µA
480 kΩ
400 kΩ
Notes on Setting Charge Pump Current
The recommended range for the charge pump current
is 25 µA to 300 µA. Below 25 µA, loop filter charge
leakage, due to PCB or capacitor leakage, can become
a problem. This loop filter leakage can cause locking
MDS 2069-01 H
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Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
VCXO Gain (K ) vs. XTAL Frequency
Notes on Setting the RV, FV and SV Divider
Values
O
6000
5000
4000
3000
2000
1000
As shown in the loop bandwidth and damping factor
equations on page 6, or by using the filter response
software available from ICS, increasing FV or SV
decreases both bandwidth and damping factor. Many
applications require that SV = 1. In these cases, one
way to decrease loop bandwidth is to increase the
value of FV, which is accompanied by an increase in
the value of RV to maintain the same PLL frequency
multiplication ratio.
However, the phase detector frequency, F , also
PD
needs to be considered. F is equal to the input
PD
frequency divided by the value of the RV divider. F
PD
should be typically at least 20x the loop bandwidth to
prevent loop modulation (phase noise) by the phase
detector frequency. The phase detector jitter tolerance
limit (use 0.4UI) and input phase noise frequency
aliasing should be considerations as well.
10
15
20
25
30
Crystal Frequency, MHz
Example Loop Filter Component Value
Input
Clock
Xtal
Freq
(MHz)
VCLK RV FV SV RSET
(MHz) Div Div Div
C
Loop Loop
BW Damp.
(-3dB)
Passband
Peaking
Note
R
C
P
S
S
8 kHz
8 kHz
19.44
19.44
19.44
19.44
1
1
1
2430
2430
2796
1
1
1
1
1 MΩ 560 kΩ 1 µF 4.7 nF 22 Hz
1 MΩ 560 kΩ 0.1 µF 4.7 nF 27 Hz
1 MΩ 680 kΩ 1 µF 4.7 nF 20 Hz
4.0
1.4
4.5
0.15dB at 1Hz
1.2dB at 6Hz
0.12dB at 1Hz
1.8dB at 8Hz
1
2
3
4
8 kHz
22.368 22.368
19.44
19.44 MHz
19.44 128 128
1 MΩ 27 kΩ 1 µF 47 nF 25 Hz 0.85
Notes:
1) This filter configuration assures a passband ripple compliant with Bellcore GR-1244 to satisfy wander
transfer requirements (<0.2 dB ripple is required) of a network node. It can be used following a system
synchronizer such as the MT9045 to provide clock jitter attenuation while maintaining Stratum 3 compliance.
A 155.52 MHz TCLK output generated with the VCXO PLL configuration will be OC-3 and OC-12 timing jitter
compliant.
2) This is a reduced cost and size variant of the above filter, due to the decreased size of C . It is useful when
S
GR-1244 compliance is not needed, such as in a network access application.
3) This configuration is used to generate a DS3 clock of 44.768 MHz at the TCLK output. This configuration
is GR-1244 compliant.
4) The MK2069-02 or MK2069-04 may be more suitable for this application since the VCXO feedback divider
can be increased (>128), enabling a lower bandwidth for improved jitter attenuation.
MDS 2069-01 H
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Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
eliminating the generation of extra VCLK clock cycle
that would occur if the loop was to re-lock under normal
means. Lock time is also reduced, as is the generation
of clock wander.
Loop Filter Capacitor Type
Loop filters must use specific types of capacitors.
Recommendations for these capacitors can be found at
www.icst.com.
By using CLR in this fashion VCLK will align to the input
clock phase with only one or two VCLK cycle slips
resulting. When CLR is not used, the number of VCLK
cycle slips can be as high the FV Divider value.
Input MUX
The MK2069-01 incorporates an input clock multiplexer
or ‘mux’ that allows selection between one of three
alternate reference inputs supplied to the device. The
mux input selection pins are asynchronous and
non-latched. Please refer to the Input MUX Selection
Table on page 2. Note that inputs ICLK0 and ICLK1 are
5V tolerant, whereas ICLK2 is not.
TCLK is always locked to VCLK regardless of the state
of the CLR input.
Lock Detection
The MK2069-01 includes a lock detection feature that
indicates lock status of VCLK relative to the selected
input reference clock. When phase lock is achieved
(such as following power-up), the LD output goes high.
When phase lock is lost (such as when the input clock
stops, drifts beyond the pullable range of the crystal, or
suddenly shifts in phase), the LD output goes low.
Input Phase Compensation Circuit
The VCXO PLL includes a special input clock phase
compensation circuit. It is used when selecting a new
reference input that has a clock phase differing from
the previously selected input. The phase compensation
circuit allows the VCXO PLL to quickly lock to the new
input phase without producing extra clock cycles or
clock wander, assuming the new clock is at the same
frequency.
The definition of a “locked” condition is determined by
the user. LD is high when the VCXO PLL phase
detector error is below the user-defined threshold. This
threshold is set by external components RLD and CLD
shown in the Lock Detection Circuit Diagram, below.
Input pin CLR controls the phase compensation circuit.
CLR must remain high for normal operation. When
used in conjunction with the input MUX select pins,
CLR should be brought low prior to MUX reselection,
then returned high after MUX reselection. This
To help guard against false lock indications, the LD pin
will go high only when the phase error is below the set
threshold for 8 consecutive phase detector cycles. The
LD pin will go low when the phase error is above the set
threshold for only 1 phase detector cycle.
prevents the VCXO PLL from attempting to lock to the
new input clock phase associated with the input clock.
The lock detector threshold (phase error) is determined
by the following relationship:
When CLR is high, the VCXO PLL operates normally.
(LD Threshold) = 0.6 x R x C
When CLR is low, the VCXO PLL charge pump output
is inactivated which means that no charge pump
correction pulses are provided to the loop filter. During
this time, the VCXO frequency is held constant by the
residual charge or voltage on the PLL loop filter,
regardless of the input clock condition. However, the
VCXO frequency will drift over time, eventually to the
minimum pull range of the crystal, due to leak-off of the
loop filter charge. This means that CLR can provide a
holdover function, but only for a very short duration,
typically in milliseconds.
Where:
1 kΩ < R < 1 MΩ (to avoid excessive noise or
leakage)
C > 50 pF (to avoid excessive error due to stray
capacitance, which can be as much as 10 pF
including Cin of LDC)
Lock Detector Application example:
The desired maximum allowable loop phase error
for a generated 19.44MHz clock is 100UI which is
5.1 µs.
Upon bringing CLR high, the FV Divider is reset and
begins counting upon with the first positive edge of the
new input clock, and the charge pump is re-activated.
By resetting the FV Divider, the memory of the previous
input clock phase is removed from the feedback divider,
Solution: 5.1 µs = (0.001 µF) x (8.5 kΩ)
MDS 2069-01 H
9
Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
Under ideal conditions, where the VCXO is phase-
locked to a low-jitter reference input, loop phase error is
typically maintained to within a few nanoseconds.
• Clock noise from device VDD pins must not get onto
the PCB power plane or system EMI problems may
result.
This above set of requirements is served by the circuit
illustrated in the Recommended Power Supply
Connection (next page). The main features of this
circuit are as follows:
Lock Detection Circuit Diagram
Lock Detection Circuit
FV
• Only one connection is made to the PCB power
plane.
Lock
Divider
Qualification
Output
• The capacitors and ferrite chip (or ferrite bead) on
the common device supply form a lowpass ‘pi’ filter
that remove noise from the power supply as well as
clock noise back toward the supply. The bulk
capacitor should be a tantalum type, 1 µF minimum.
The other capacitors should be ceramic type.
Counter
LD
(8 up, 1 down)
RESET
VCXO
Phase
Detector
Error
• The power supply traces to the individual VDD pins
should fan out at the common supply filter to reduce
interaction between the device circuit blocks.
Output
OEL
LDR
RLD
LDC
Input Threshold
set to VDD/2
• The decoupling capacitors at the VDD pins should be
ceramic type and should be as close to the VDD pin
as possible. There should be no via’s between the
decoupling capacitor and the supply pin.
CLD
If the lock detection circuit is not used, the LDR output
may remain unconnected, however the LDC input
should be tied high or low. If the PCB was designed to
accommodate the RLD and CLD components but the
LD output will not be used, RLD can remain unstuffed
and CLD can be replaced with a resistor (< 10 kohm).
Power Supply Considerations
As with any integrated clock device, the MK2069-01
has a special set of power supply requirements:
• The feed from the system power supply must be
filtered for noise that can cause output clock jitter.
Power supply noise sources include the system
switching power supply or other system components.
The noise can interfere with device PLL components
such as the VCO or phase detector.
• Each VDD pin must be decoupled individually to
prevent power supply noise generated by one device
circuit block from interfering with another circuit
block.
MDS 2069-01 H
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Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
capacitance is 14pF. To achieve this, the layout should
use short traces between the MK2069-01 and the
crystal.
Recommended Power Supply Connection
VDD
Pin
Recommended Crystal Parameters:
Connection Via to 3.3V
Power Plane
Crystal parameters can be found in application note
MAN05 on www.icst.com. Approved crystals can be
found at www.icst.com (search “crystal”).
VDD
Pin
Ferrite
Chip
Crystal Tuning Load Capacitors
The crystal traces should include pads for small
capacitors from X1 and X2 to ground, shown as C in
VDD
Pin
L
the External VCXO PLL Components diagram on page
6. These capacitors are used to center the total load
capacitor adjustment range imposed on the crystal.
The load adjustment range includes stray PCB
capacitance that varies with board layout. Because the
typical telecom reference frequency is accurate to less
than 32 ppm, the MK2069-01 may operate properly
without these adjustment capacitors. However, ICS
recommends that these capacitors be included to
minimize the effects of variation in individual crystals,
including those induced by temperature and aging. The
value of these capacitors (typically 0-4 pF) is
VDD
Pin
Series Termination Resistor
Output clock PCB traces over 1 inch should use series
termination to maintain clock signal integrity and to
reduce EMI. To series terminate a 50Ω trace, which is a
commonly used PCB trace impedance, place a 33Ω
resistor in series with the clock line as close to the clock
output pin as possible. The nominal impedance of the
clock output is 20Ω.
determined once for a given board layout, using the
procedure described in MAN05.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed. Please refer to the Recommended PCB
Layout drawing on the following page.
Quartz Crystal
1) Each 0.01µF decoupling capacitor (CD) should be
mounted on the component side of the board as close
to the VDD pin as possible. No via’s should be used
between the decoupling capacitor and VDD pin. The
PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite chip and bulk decoupling from
the device is less critical.
The MK2069-01 operates by phase-locking the VCXO
circuit to the input signal at the selected ICLK input.
The VCXO consists of the external crystal and the
integrated VCXO oscillator circuit. To achieve the best
performance and reliability, a crystal device with the
recommended parameters must be used, and the
layout guidelines discussed in the following section
must be followed.
2) The loop filter components must also be placed
The frequency of oscillation of a quartz crystal is
determined by its cut and by the load capacitors
connected to it. The MK2069-01 incorporates variable
load capacitors on-chip which “pull” or change the
frequency of the crystal. The crystals specified for use
with the MK2069-01 are designed to have zero
frequency error when the total of on-chip + stray
close to the CHGP and VIN pins. C should be closest
P
to the device. Coupling of noise from other system
signal traces should be minimized by keeping traces
short and away from active signal traces. Use of vias
should be avoided.
3) The external crystal should be mounted as close to
the device as possible, on the component side of the
MDS 2069-01 H
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Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
board. This will keep the crystal PCB traces short
which will minimize parasitic load capacitance on the
crystal and as well as noise pickup. The crystal traces
should be spaced away from each other and should
use minimum trace width. There should be no signal
traces near the crystal or the traces. Also refer to the
Optional Crystal Shielding section that follows.
evaluation. The crystal is less sensitive to system noise
interference when the case is grounded.
4) Add a ground trace around the crystal circuit to
shield from other active traces on the component layer.
The external crystal is particularly sensitive to other
system clock sources that are at or near the crystal
frequency since it will try to lock to the interfering clock
source. The crystal should be keep away from these
clock sources.
4) To minimize EMI the 33Ω series termination resistor,
if needed, should be placed close to the clock output.
5) All components should be on the same side of the
board, minimizing vias through other signal layers (the
ferrite bead and bulk decoupling capacitor may be
mounted on the back). Other signal traces should be
routed away from the MK2069-01. This includes signal
traces on PCB traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
The ICS Applications Note MAN05 may also be
referenced for additional suggestions on layout of the
crystal section.
6) Because each input selection pin includes an
internal pull-up device, those inputs requiring a logic
high state (“1”) can be left unconnected. The pins
requiring a logic low state (“0”) can be grounded.
Optional Crystal Shielding
The crystal and connection traces to pins X1 and X2
are sensitive to noise pickup. In applications that are
especially sensitive to noise, such as SONET or G-Bit
ethernet transceivers, some or all of the following
crystal shielding techniques should be considered. This
is especially important when the MK2069-01 is placed
near high speed logic or signal traces.
The following techniques are illustrated on the
Recommended PCB Layout drawing.
1) The metal layer underneath the crystal section
should be the ground layer. Remove all other layers
that are above. This ground layer will help shield the
crystal circuit from other system noise sources. As an
alternative, all layers underneath the crystal can be
removed, however this is not recommended if there are
adjacent PCBs that can induce noise into the
unshielded crystal circuit.
2) Cut a channel in the PCB ground plane around the
crystal area as shown. This will eliminate high
frequency ground currents that can couple into to
crystal circuit.
3) Add a through-hole for the optional third lead offered
by the crystal manufacturer (case ground). The
requirement for this third lead can be made at prototype
MDS 2069-01 H
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Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
Recommended PCB Layout Diagram
SUPPLY SOURCE TO DEVICE
(SUCH AS VIA TO SUPPLY PLANE)
OPTIONAL CRYSTAL SHIELDING
THRU HOLE FOR 3RD LEAD (XTAL CASE GROUND)
SHIELD TRACE (TOP LAYER)
CE
603
CBD
A
V
G
CUT CHANNEL IN GROUND PLANE
FC
A
CBB
603
G
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
G
G
2
G
G
3
4
G
G
5
6
7
G
8
G
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CD
603
XTAL
G
G
RT
603
G
MK2069
G
RT
603
G
G
G
RLD
603
G
G
CLD
603
G
RS
603
G
G
RSET
603
G
Components are identified by function (top line) and by typical package type (bottom line) which may vary.
Legend:
CS = External loop capacitor C (film type)
S
G = Via to PCB Ground plane
V = Via to PCB Power Plane
CP = External loop capacitor C (film type)
P
RS = External loop resistor R
S
CE = EMI suppression cap, typical value 0.1 µF
RSET = Resistor R
current
used to set charge pump
SET
(ceramic)
FC = Ferrite chip
RT = Series termination resistor for clock output,
typical value 33 Ω
CBD = Bulk decoupling capacitor for chip power
supply, 1 µF minimum (tantalum)
CBB = Bulk bypass cap for chip power supply, typical
value 1000 nF (ceramic)
RLD* = External resistor for lock detector circuit
CLD* = External capacitor for lock detector circuit
CD = Decoupling capacitor for VDD pin (ceramic)
CL = Optional load capacitor for crystal tuning (do not
stuff)
*Note: If output LD is not used, RLD and CLD may be
omitted. See text on page 10.
MDS 2069-01 H
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Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
2.3) VCLK and TCLK jitter can also be caused by poor
power supply decoupling. Ensure a bulk decoupling
capacitor is in place.
Circuit Troubleshooting
1) IF TCLK or VCLK does not lock to ICLK
2.4) Ensure that the VCXO PLL loop bandwidth is
sufficiently low. It should be at least 1/20th of the phase
detector frequency.
First check VCLK to ICLK. It is best to display and
trigger the scope with RCLK, especially if a non-integer
VCXO PLL multiplication ratio is used.
2.5) Ensure that the VCXO PLL loop damping is
sufficient. If should be at least 0.7, preferably 1.0 or
higher.
If VCLK is not locked to ICLK:
1.1) Ensure the proper ICLK input is selected.
1.2) Check RV, SV, FV Divider settings
2.6) Ensure that the 2nd pole in the VCXO PLL loop
1.3) Ensure ICLK is within lock range (within about 100
ppm of the nominal input frequency, limited by pull
range of the external crystal). If in doubt, tweak the
ICLK frequency up and down to see if VCLK locks.
filter is set sufficiently. In general, C should be equal to
P
CS/20. If C is too high, passband peaking will occur
P
and loop instability may occur. If C is set too low,
P
excessive VCXO modulation by the charge correction
pulses may occur.
1.4) Ensure ICLK jitter is not excessive. If ICLK jitter is
excessive device may not lock. Also see item 2.1
below.
3) If There is Excessive Input to Output Skew
3.1) TCLK should track VCLK. The rising edge of TCLK
should be within a few nanoseconds of VCLK.
1.5) Clean the PCB. The VCXO PLL loop filter is very
sensitive to board leakage, especially when the VCXO
PLL phase detector frequency is in the low kHz. If
organic solder flux is used (most common today) scrub
the PCB board with detergent and water and then blow
and bake dry. Inorganic solder flux (Rosen core)
requires solvent. See also section 3 below.
3.1) VCLK should track RCLK. The rising edge of
VCLK should be within 5-10 nsec of RCLK (VCLK
leads).
3.3) The biggest cause of input to output skew is VCXO
PLL loop filter leakage. Skew is best observed by
comparing ICLK to RCLK. When no leakage is present
the rising edge of RCLK should lag the rising edge of
ICLK by about 10 usec. Loop filter leakage can greatly
increase this lag time or cause the loop to not lock.
Refer to item 1.5, above.
2) If There is Excessive Jitter on VCLK or
TCLK
2.1) The problem may be an unstable input reference
clock. An unstable ICLK will not appear to jitter when
ICLK is used as the oscilloscope trigger source. In this
condition, VCLK and TCLK may appear to be unstable
since the jitter from ICLK (the trigger source) has been
removed by the trigger circuit of the scope.
3.4) Another way to view the loop filter leakage is to
observe LDR pin. Use RCLK as the scope trigger. LDR
will produce a negative pulse equal in length to the
charge pump pulse.
3.5) Filter leakage can also be caused by the use of
improper loop capacitors. Refer to the section titled
‘Loop Filter Capacitor Type’ on page 9.
2.2) The instability may be caused by VCXO PLL loop
filter leakage. Refer to item 1.5 above.
MDS 2069-01 H
14
Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2069-01. These ratings
are stress ratings only. Functional operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed
only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7V
-0.5V to VDD+0.5V
-40 to +85°C
-65 to +150°C
175°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+85
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
-40
+3.15
+3.3
+3.45
V
MDS 2069-01 H
15
Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
Symbol
VDD
Conditions
Min.
3.15
Typ.
3.3
Max. Units
3.45
30
V
Supply Current
IDD
All clock outputs
20
mA
loaded with 15 pF,
VCLK = 19.44 MHz,
TCLK = 155.52 MHz
Input High Voltage, MX1:0,
RV1:0, FV11:0, SV2:0, RT1:0,
FT5:0, ST1:0
V
2
VDD +
0.4
V
V
IH
Input Low Voltage, MX1:0,
RV1:0, FV11:0, SV2:0, RT1:0,
FT5:0, ST1:0
V
-0.4
0.8
IL
Input Pull-Up Resistor (Note 1)
R
200
kΩ
PU
VDD/2+1
Input High Voltage, ICLK2,
CLR
V
VDD +
0.4
V
IH
VDD/2+1
-0.4
Input High Voltage, ICLK1:0
V
5.5
V
V
IH
VDD/2-1
Input Low Voltage, ICLK2:0,
CLR
V
IL
Input High Current (Note 1)
Input Low Current (Note 1)
Input Capacitance, except X1
I
V
= VDD
IH
-10
-10
+10
+10
µA
µA
pF
V
IH
I
V = 0
IL
IL
C
7
IN
Output High Voltage (CMOS
Level)
V
I
= -4 mA
VDD-0.4
2.4
OH
OH
Output High Voltage
Output Low Voltage
V
I
I
= -8 mA
= 4 mA
V
V
OH
OH
V
0.4
OL
OS
OL
Output Short Circuit Current,
TCLK
I
I
50
20
mA
Output Short Circuit Current,
VCLK, RCLK and LD
mA
V
OS
VIN, VCXO Control Voltage
V
0
VDD
XC
Note 1: All logic select inputs (MX1:0, RV1:0, FV11:0, SV2:0, RT1:0, FT5:0, ST1:0, CLR) have an internal
pull-up resistor.
MDS 2069-01 H
16
Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
VCXO Crystal Frequency Range
(Note 1)
f
Using recommended
crystal
13.5
27
MHz
ppm
ppm
XTAL
VCXO Crystal Pull Range
f
Using recommended
crystal
115
150
XP
VCXO Crystal Free-Run
Frequency (Note 2)
f
Input reference = 0 Hz
-300
-150
XF
Input Clock Frequency (Note 2)
Input Clock Pulse Width
f
0.001
10
170
27
MHz
nsec
I
t
Positive or Negative
Pulse
ID
VCXO PLL Phase Detector
Frequency (Note 3)
f
0.001
MHz
UI
PD
VCXO PLL Phase Detector Jitter
Tolerance
t
1 UI = phase detector
period
0.4
JT
Translator PLL VCO Frequency
f
40
320
MHz
ps
V
Timing Jitter, Filtered
500Hz-1.3MHz (OC-3)
t
t
t
t
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
95
85
OJf
Timing Jitter, Filtered
65kHz-5MHz (OC-3)
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
ps
ps
ps
OJf
OJf
OJf
Timing Jitter, Filtered
1kHz-5MHz (OC-12)
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
105
80
Timing Jitter, Filtered
250kHz-5MHz (OC-12)
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
Output Duty Cycle (% high time),
VCLK when SV Divider = 1
t
t
Measured at VDD/2,
40
44
50
50
60
65
%
%
OD
OD
C =15pF
L
Output Duty Cycle (% high time),
VCLK when SV Divider > 1,
TCLK
Measured at VDD/2,
C =15pF
L
Output High Time, RCLK
(Note 4)
t
t
Measured at VDD/2,
0.5
VCLK
Period
OH
OR
C =15pF
L
Output Rise Time, VCLK and
RCLK
0.8 to 2.0V, C =15pF
1.5
2
2
ns
ns
L
Output Fall Time, VCLK and
RCLK
t
2.0 to 0.8V, C =15pF
L
1.5
OF
MDS 2069-01 H
17
Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Output Rise Time, TCLK
Output Fall Time, TCLK
t
0.8 to 2.0V, C =15pF
0.75
0.75
2.5
10
1
ns
ns
ns
ns
ns
Ω
OR
L
t
2.0 to 0.8V, C =15pF
1
OF
L
Skew, ICLK to VCLK (Note 5)
Skew, ICLK to RCLK (Note 5)
Skew, ICLK to TCLK (Note 5)
Nominal Output Impedance
t
Rising edges, C =15pF
-5
+5
-5
+10
+20
+10
IV
IV
L
t
Rising edges, C =15pF
L
t
Rising edges, C =15pF
1.5
20
VT
L
Z
OUT
Note 1: This is the recommended crystal operating range. A crystal as low as 8 MHz can be used, although
this may result in increased output phase noise.
Note 2: The VCXO crystal will be pulled to its minimum frequency when there is no input clock (CLR = 1)
due to the attempt of the PLL to lock to 0 Hz.
Note 3: The minimum practical input frequency is 1 kHz. Through proper loop filter design lower input
frequencies may be possible.
Note 4: The output of RCLK is a positive pulse with a duration equal to VCLK high time, or half the VCLK
period.
Note 5: Referenced to ICLK, the skews of VCLK, RCLK and TCLK increase together when leakage is
present in the external VCXO PLL loop filter.
MDS 2069-01 H
18
Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
MK2069-01
Line Card Clock Synchronizer
Package Outline and Package Dimensions
56 pin TSSOP 6.10 mm (240 mil) body, 0.50 mm. (20 mil) pitch
Package dimensions are kept current with JEDEC Publication No. 95
56
Millimeters
Inches
Max
Symbol
A
Min
--
Max
1.20
0.15
1.05
0.27
0.20
14.10
Min
--
0.047
0.006
0.041
0.011
A1
0.05
0.80
0.17
0.09
13.90
0.002
0.032
0.007
E1
E
A2
b
C
INDEX
AREA
0.0035 0.008
0.547 0.555
0.319 BASIC
D
E
8.10 BASIC
1
2
E1
e
6.00
6.20
0.236
0.244
0.50 Basic
0.020 Basic
D
L
α
0.45
0°
0.75
8°
0.018
0°
0.030
8°
aaa
--
0.10
--
0.004
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa
C
Ordering Information
Part / Order Number
Marking
Shipping
packaging
Package
Temperature
MK2069-01GI
MK2069-01GI
MK2069-01GI
Tubes
56 pin TSSOP
56 pin TSSOP
-40 to +85° C
-40 to +85° C
MK2069-01GITR
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 2069-01 H
19
Revision 050203
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
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