IS61C512-15T [ICSI]
64K x 8 HIGH-SPEED CMOS STATIC RAM; 64K ×8高速CMOS静态RAM
| 型号： | IS61C512-15T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 64K x 8 HIGH-SPEED CMOS STATIC RAM |
| 文件： | 总8页 (文件大小：425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61C512
64K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
DESCRIPTION
The ICSI IS61C512 is a very high-speed, low power, 65,536
word by 8-bit CMOS static RAMs. They are fabricated using
ICSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields higher performance and low power con-
sumption devices.
• Pin compatible with 128K x 8 devices
• High-speed access time: 15, 20, 25, 35 ns
• Low active power: 500 mW (typical)
• Low standby power
— 250 µW (typical) CMOS standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down to 1 mW (typical) with CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS61C512 is available in 32-pin 300mil DIP, SOJ and
8*20mm TSOP-1 packages.
FUNCTIONAL BLOCK DIAGRAM
512 X 1024
MEMORY ARRAY
A0-A15
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE1
CE2
CONTROL
CIRCUIT
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
1
SR011-0B
IS61C512
PIN CONFIGURATION
32-Pin DIP and SOJ
PIN CONFIGURATION
32-Pin TSOP-1
NC
NC
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A11
A9
A8
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
2
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
3
3
4
A13
WE
CE2
A15
VCC
NC
NC
A14
A12
A7
4
5
5
A6
6
6
A5
7
A9
7
A4
8
A11
OE
8
A3
9
9
A2
10
11
12
13
14
15
16
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
10
11
12
13
14
15
16
A1
A0
I/O0
I/O1
I/O2
GND
A6
A5
A4
A1
A2
A3
PIN DESCRIPTIONS
A0-A15
Address Inputs
CE1
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
CE2
OE
WE
I/O0-I/O7
Vcc
GND
Power
Ground
TRUTH TABLE
Mode
WE
CE1
CE2
OE
I/O Operation
Vcc Current
Not Selected
(Power-down)
X
X
H
X
X
L
X
X
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
Output Disabled
Read
Write
H
H
L
L
L
L
H
H
H
H
L
X
High-Z
DOUT
DIN
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
Notes:
ABSOLUTE MAXIMUM RATINGS(1)
1. Stress greater than those listed
under ABSOLUTE MAXIMUM
RATINGS may cause permanent
damage to the device. This is a
stress rating only and functional
operation of the device at these or
any other conditions above those
indicated in the operational sec-
tions of this specification is not
implied. Exposure to absolute
maximum rating conditions for ex-
tended periods may affect reliabil-
ity.
Symbol Parameter
Value
Unit
V
°C
°C
W
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND
–0.5 to +7.0
–10 to +85
–65 to +150
1.5
Temperature Under Bias
Storage Temperature
Power Dissipation
IOUT
DC Output Current (LOW)
20
mA
2
Integrated Circuit Solution Inc.
SR011-0B
IS61C512
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
VCC
5V ± 10%
5V ± 10%
0°C to +70°C
–40°C to +85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
VCC = Min., IOH = –4.0 mA
Min.
2.4
—
Max.
—
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
VCC = Min., IOL = 8.0 mA
0.4
V
2.2
–0.3
–2
VCC + 0.5
V
0.8
2
V
GND ≤ VIN ≤ VCC
µA
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
–2
2
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-15 ns
-20 ns
Min. Max.
-25 ns
-35 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
ICC1
ICC2
ISB1
Vcc Operating
Supply Current
VCC = Max.,
Com.
Ind.
—
—
70
—
—
—
70
90
—
—
70
90
—
—
70
90
mA
IOUT = 0 mA, f = 0
Vcc Dynamic Operating
Supply Current
VCC = Max.,
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
125
—
—
—
115
135
—
—
105
125
—
—
90
115
mA
mA
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
Com.
Ind.
—
—
25
—
—
—
25
30
—
—
25
30
—
—
25
30
CE1
CE2
≥
≤
VIH or
VIL, f = 0
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
Com.
Ind.
—
—
750
—
—
—
750
1
—
—
750
1
—
—
750
1
µA
mA
CE1
≥
≤
VCC – 0.2V,
0.2V,
CE2
VIN
VIN
≥
VCC – 0.2V, or
0.2V, f = 0
≤
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Input Capacitance
Conditions
VIN = 0V
Max.
5
Unit
pF
COUT
Output Capacitance
VOUT = 0V
7
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Circuit Solution Inc.
3
SR011-0B
IS61C512
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-15 ns
Min.
15
—
3
-20 ns
Min.
20
—
3
-25 ns
Max.
-35 ns
Symbol Parameter
Max.
—
15
—
15
15
7
Max.
—
20
—
20
20
8
Min.
25
—
3
Min.
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
—
25
—
25
25
9
35
—
3
tAA
Address Access Time
Output Hold Time
CE1 Access Time
CE2 Access Time
OE Access Time
35
—
tOHA
tACE1
tACE2
tDOE
—
—
—
0
—
—
—
0
—
—
—
0
—
—
—
0
35
35
12
—
(2)
tLZOE
OE to Low-Z Output
OE to High-Z Output
—
6
—
9
—
10
—
—
10
—
20
(2)
tHZOE
0
0
0
0
12
—
tLZCE1(2) CE1 to Low-Z Output
2
—
—
8
3
—
—
9
3
3
tLZCE2(2) CE2 to Low-Z Output
2
3
3
3
—
(2)
tHZCE
CE1 or CE2 to High-Z Output
0
0
0
0
12
—
(3)
tPU
CE1 or CE2 to Power-Up
0
—
12
0
—
18
0
0
(3)
tPD
CE1 or CE2 to Power-Down
—
—
—
—
20
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 3.0V
3 ns
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1a and 1b
AC TEST LOADS
1213 Ω
1213 Ω
3.3V
3.3V
OUTPUT
OUTPUT
1378 Ω
1378 Ω
100 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figure 1a.
Figure 1b.
4
Integrated Circuit Solution Inc.
SR011-0B
IS61C512
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
LZOE
CE1
t
ACE1/tACE2
CE2
t
LZCE1/
tLZCE2
t
HZCE
HIGH-Z
HIGH-Z
DOUT
DATA VALID
t
PU
t
PD
ICC
ISB
50%
50%
SUPPLY
CURRENT
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
Integrated Circuit Solution Inc.
5
SR011-0B
IS61C512
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-15 ns
Min.
-20 ns
-25 ns
Max.
-35 ns
Min.
Symbol Parameter
Max.
—
—
—
—
—
—
—
—
—
7
Min.
Max.
—
Min.
25
20
20
20
0
Max.
—
—
—
—
—
—
—
—
—
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
15
12
12
12
0
20
15
15
15
0
—
—
—
—
—
—
—
—
—
12
—
35
30
30
30
0
tSCE1
tSCE2
tAW
CE1 to Write End
—
CE2 to Write End
—
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
—
tHA
—
tSA
0
0
—
0
0
(4)
tPWE
tSD
WE Pulse Width
10
8
12
10
0
—
15
12
0
20
15
0
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
—
tHD
0
—
(2)
tHZWE
—
2
—
2
10
—
—
2
—
2
(2)
tLZWE
—
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t
WC
ADDRESS
CE1
t
HA
t
SCE1
t
SCE2
CE2
t
AW
t
PWE
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DOUT
DATA UNDEFINED
t
t
HD
DATA-IN VALID
DIN
6
Integrated Circuit Solution Inc.
SR011-0B
IS61C512
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
t
WC
ADDRESS
t
SA
tHA
t
SCE1
CE1
CE2
t
SCE2
t
AW
t
PWE
WE
t
HZWE
tLZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
SD
DIN
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
2. I/O will assume the High-Z state if OE = HIGH.
Integrated Circuit Solution Inc.
7
SR011-0B
IS61C512
ORDERING INFORMATION: IS61C512
Commercial Range: 0°C to + 70°C
ORDERING INFORMATION: IS61C512
Industrial Range: –40°C to + 85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
15
15
15
IS61C512-15J
IS61C512-15N
IS61C512-15T
300mil SOJ
15
15
15
IS61C512-15JI
IS61C512-15NI
IS61C512-15TI
300mil SOJ
300mil DIP
300mil DIP
8*20mm TSOP-1
8*20mm TSOP-1
20
20
20
IS61C512-20J
IS61C512-20N
IS61C512-20T
300mil SOJ
20
20
20
IS61C512-20JI
IS61C512-20NI
IS61C512-20TI
300mil SOJ
300mil DIP
300mil DIP
8*20mm TSOP-1
8*20mm TSOP-1
25
25
25
IS61C512-25J
IS61C512-25N
IS61C512-25T
300mil SOJ
25
25
25
IS61C512-25JI
IS61C512-25NI
IS61C512-25TI
300mil SOJ
300mil DIP
300mil DIP
8*20mm TSOP-1
8*20mm TSOP-1
35
35
35
IS61C512-35J
IS61C512-35N
IS61C512-35T
300mil SOJ
35
35
35
IS61C512-35JI
IS61C512-35NI
IS61C512-35TI
300mil SOJ
300mil DIP
300mil DIP
8*20mm TSOP-1
8*20mm TSOP-1
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
8
Integrated Circuit Solution Inc.
SR011-0B
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