IS42S16400L [ICSI]
2(1)M words x 8(16) bits x 4 banks (64-mbit) synchronous dynamic ram; 2（1） M个字×8 （16）位× 4个存储体（ 64兆位）同步动态随机存取存储器
| 型号： | IS42S16400L |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 2(1)M words x 8(16) bits x 4 banks (64-mbit) synchronous dynamic ram |
| 文件： | 总68页 (文件大小：1495K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
2(1)M Words x 8(16) Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
DESCRIPTION
The IS42S8800 and IS42S16400 are high-speed 67,
108,864-bit synchronous dynamic random-access
moeories, organized as 2,097,152 x 8 x 4 and 1,048,
576 x 16 x 4 (word x bit x bank), respectively.
Single 3.3V (± 0.3V) power supply
High speed clock cycle time -7: 133MHz<3-3-3>,
-8: 100MHz<2-2-2>
Fully synchronous operation referenced to clock
rising edge
The synchronous DRAMs achieved high-speed data
transfer using the pipeline architecture and clock
frequency up to 133MHz for -7. All input and outputs
are synchronized with the postive edge of the clock.
The synchronous DRAMs are compatible with Low
Voltage TTL (LVTTL).These products are pack-aged
in 54-pin TSOP-2.
Possible to assert random column access in
every cycle
Quad internal banks contorlled by A12 & A13
(Bank Select)
Byte control by LDQM and UDQM for
IS42S16400
Programmable Wrap sequence (Sequential /
Interleave)
Programmable burst length (1, 2, 4, 8 and full
page)
Programmable /CAS latency (2 and 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
X8, X16 organization
LVTTL compatible inputs and outputs
4,096 refresh cycles / 64ms
Burst termination by Burst stop and Precharge
command
Package 400mil 54-pin TSOP-2
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR007-0A
1
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
PIN CONFIGURATIONS
54-Pin TSOP-2 (IS42S8800)
54-Pin TSOP-2 (IS42S16400)
VDD
DQ0
VDDQ
NC
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ7
VSSQ
NC
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
2
2
3
3
4
4
DQ1
VSSQ
NC
5
DQ6
VDDQ
NC
5
6
6
7
7
DQ2
VDDQ
NC
8
DQ5
VSSQ
NC
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ3
VSSQ
NC
DQ4
VDDQ
NC
VDD
NC
VSS
NC
WE
DQM
CLK
CKE
NC
DQM
CLK
CKE
NC
CAS
RAS
CS
CAS
RAS
CS
BA0
BA1
A10
A0
A11
A9
BA0
BA1
A10
A11
A9
A8
A8
A7
A0
A7
A1
A6
A1
A6
A2
A5
A2
A5
A3
A4
A3
A4
VDD
VSS
VDD
VSS
PIN DESCRIPTIONS
DQM
A0-11
BA0,1
VDD
DQ Mask Enable
Address Input
Bank Address
Power Supply
CLK
Master Clock
CKE
Clock Enable
Chip Select
CS
RAS
Row Address Strobe
VDDQ
VSS
Power Supply for DQ
Ground
CAS
Column Address Strobe
Write Enable
WE
VSSQ
Ground for DQ
DQ0 ~ DQ15
Data I/O
2
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
Clock
Generator
Bank D
Bank C
Bank B
Address
Row
Address
Buffer
&
Mode
Register
Refresh
Counter
Bank A
Sense Amplifier
DQM
DQ
CS
Column Decoder &
Latch Circuit
Column
Address
Buffer
RAS
CAS
WE
&
Burst
Data Control Circuit
Counter
Integrated Circuit Solution Inc.
DR007-0A
3
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
PIN FUNCTIONS
Symbol
Type
Function (In Detail)
CLK
CKE
Input Pin
Input Pin
Maste Clock: Other inputs signals are referenecd to the CLK rising edge
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal
clock signals,device input buffers and output drivers. Deactivating the clock
provides PRECHARGE POWER-DOWN and SELF REFRESH operation
(all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank).
CS
Input Pin
Chip Select: CS enables (registered LOW) and disables (registered HIGH)
the com-mand decoder. All commands are masked when CS is registered
HIGH. CS provides for external bank selection on systems with multiple
banks. CS is considered part of the command code.
RAS, CAS, WE
Input Pin
Input Pin
Command Inputs: RAS, CAS and WE (along with CS) define the command
being entered.
A0-A11
Address Inputs: Provide the row address for ACTIVE commands, and the
column address and AUTO PRECHARGE bit for READ/WRITE
commands, to select one loca-tion out of the memory array in the respec-
tive bank. The row address is specified by A0-A11. The column address is
specified by A0-A8 (IS42S8800) / A0-A7 (IS42S16400)
BA0,BA1
Input Pin
Input Pin
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
DQM, UDQM ,LDQM
Address Inputs: Provide the row address for ACTIVE commands (row
address A0-A10), and the column address and AUTO PRECHARGE bit for
READ/WRITE com-mands (column address A0-A7 with A10 defining
AUTO PRECHARGE), to select one location out of the memory array in the
respective bank.
DQ0 to DQ15
VDD, VSS
I/O Pin
IData Input / Output: Data bus.
Power Supply Pin
Power Supply Pin
Power Supply for the memory array and peripheral circuitry.
Power Supply are supplied to the output buffers only.
VDDQ, VSSQ
4
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
Rating
Unit
V
DD
Supply Voltage (with respect to VSS)
Supply Voltage for Output (with respect to VSSQ)
Input Voltage (with respect to VSS)
Output Voltage (with respect to VSSQ)
Short circuit output current
0.5 to +4.6
0.5 to +4.6
0.5 to VDD+0.5
1.0 to VDDQ+0.5
50
V
V
VDDQ
VI
V
VO
V
IO
mA
W
°C
°C
PD
Power Dissipation (TA = 25 °C)
Operating Temperature
1
TOPT
TSTG
0 to +70
Storage Temperature
65 to +150
Notes:
1. Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent
damage. The device is not meant to be operated under conditions outside the limits described in the
operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability.
DC RECOMMENDED OPERATING CONDITIONS
(At TA = 0 to +70°C unless otherwise noted)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
VDDQ
VSS
VSSQ
VIH
Supply Voltage
3.0
0
3.3
0
3.6
V
V
V
V
V
V
Supply Voltage for DQ
Ground
0
3.6
3.0
0
3.3
0
Ground for DQ
0
High Level Input Voltage (all Inputs)
Low Level Input Voltage (all Inputs)
2.0
-0.3
VDD + 0.3
+0.8
VIL
CAPACITANCE CHARACTERISTICS
(At TA = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V, VSS = VSSQ = 0V , unless otherwise noted)
Symbol
Parameter
Min.
Max.
Unit
CIN
Input Capacitance, address & control pin
Input Capacitance, CLK pin
2.5
2.5
4.0
3.8
3.5
6.5
pF
pF
pF
CCLK
CI/O
Data Input/Output Capacitance
Integrated Circuit Solution Inc.
DR007-0A
5
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
DC ELECTRICAL CHARACTERISTICS
(At TA = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V, VSS = VSSQ = 0V , unless otherwise noted)
Symbol Parameter
Test Condition
Speed
Min. Max.
Unit
ICC1(1)
Operating Current
One Bank active, CAS latency = 3 -7(42S8800)
75
mA
Burst Length=1
tRC = tRC (min.)
tCLK = tCLK (min.)
-7(42S16400)
-8(42S8800)
-8(42S16400)
70
85
80
mA
mA
mA
ICC2P
Precharge Standby Current
(In Power-Down Mode)
CKE < VIL (MAX)
tCK = 15 ns
-7
-8
2
2
mA
mA
ICC2PS
CKE < VIL (MAX)
CLK < VIL (MAX)
tCK = 15 ns
-7
-8
1
1
mA
mA
ICC2N(2) Precharge Standby Current
(In Non Power-Down Mode)
CS > VCC -0.2V
CKE > VIH (MIN)
-7
-8
20
20
mA
mA
ICC2NS
CS > VCC -0.2V
CKE < VIL (MAX)
-7
15
15
mA
mA
CKE > VIH (MIN) All input signals are stable. -8
ICC3P
Active Standby Current
(In Power-Down Mode)
CKE < VIL (MAX)
CKE < VIL (MAX)
tCK = 10 ns
-7
-8
7
7
mA
mA
ICC3PS
CLK < VIL (MAX)
tCK = 15 ns
-7
-8
5
5
mA
mA
ICC3N(2) Active Standby Current
(In Non Power-Down Mode)
CS > VCC -0.2V
CKE > VIH (MIN)
-7
-8
30
30
mA
mA
ICC3NS
CS > VCC -0.2V
CKE < VIL (MAX)
-7
25
25
mA
mA
CKE > VIH (MIN) All input signals are stable. -8
ICC4
Operating Current
(In Burst Mode)
All Banks active
Burst Length=1
tCK = tCK (MIN)
CAS latency = 3 -7(42S8800)
-7(42S16400)
-8(42S8800)
90
70
100
80
mA
mA
mA
mA
-8(42S16400)
ICC5
Auto-Refresh Current
tRC = tRC (MIN)
-7
-8
130
110
mA
mA
tCLK = tCLK (MIN)
ICC6(3, 4) Self-Refresh Current
CKE < 0.2V
-7
-8
-7L
-8L
1
1
0.5
0.5
mA
mA
mA
mA
IIL
Input Leakage Current
(Inputs)
0V < VIN < VDD (MAX)
Pins not under test = 0V
5
5
µA
IOL
Output Leakage Current
(I/O pins)
Output is disabled DQ# in H - Z.,
0V < VOUT < VDD (MAX)
5
5
µA
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
IOUT = 2 mA
IOUT = +2 mA
2.4
V
V
0.4
Notes:
1. I CC(max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
3. Normal version: IS42S8800/IS42S16400
4. Low power version: IS42S8800L/IS42S16400L
6
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
AC TEST CONDITIONS
(At TA = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V, VSS = VSSQ = 0V , unless otherwise noted)
Parameter
Rating
Unit
AC input Levels (VIH /VIL )
2.0 / 0.8
V
V
Input timing reference level /Output timing reference level
Input rise and fall time
1.4
1
ns
Output load condition
50
pF
Output Load Conditions
VDDQ
V
V
DDQ
OUT
Z = 50
Ω
Device
Under
Test
50PF
Integrated Circuit Solution Inc.
DR007-0A
7
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
AC ELECTRICAL CHARACTERISTICS
(At TA = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V, VSS = VSSQ = 0V , unless otherwise noted)
-7
-8
Symbol Parameter
Min.
Max.
Min.
Max.
Units
tCK3
CLK Cycle Time
CAS Latency = 3
CAS Latency = 2
7.5
10
10
10
ns
ns
tCK2
tAC3
CLK to valid output delay(1)
CAS Latency = 3
CAS Latency = 2
5.4
6
6
6
ns
ns
tAC2
tCH
CLK high pulse width
CLK low pulse width
CKE setup time
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
3
2.5
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCL
tCKE
tCKH
tAS
CKE hold time
1
Address setup time
Address hold time
Command setup time
Command hold time
Data input setup time
Data input hold time
Output data hold time(1)
2
tAH
1
tCMS
tCMH
tDS
2
1
2
tDH
1
tOH3
tOH2
CAS Latency = 3
CAS Latency = 2
2.7
3
3
3
ns
ns
tLZ
CLK to output in low - Z
CLK to output in H - Z
ROW cycle time
0
2.7
67.5
45
20
20
15
15
1
5.4
0
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tHZ
3
tRC
70
50
20
20
20
20
1
tRAS
tRCD
tRP
ROW active time
100,000
100,000
RAS to CAS delay
Row precharge time
Row active to active delay
Data in to precharge
Transition time
tRRD
tDPL
tT
10
10
tRSC
tPDE
tSRX
tREF
Mode reg. set cycle
Power down exit setup time
Self refresh exit time
Refresh Time
10
7.5
7.5
10
10
10
64
64
Notes:
1. if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.
8
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Basic Features and Function Description
Simplified State Diagram
Self
Refresh
y
r
t
n
e
F
L
t
i
E
x
S
e
F
L
E
S
Mode
Register
Set
MRS
AUTO
Refresh
REF
IDLE
CK
E
C
K
E
Power
Down
Active
Power
Down
CKE
Re
ROW
ACTIVE
CKE
T
B
S
T
S
B
e
t
i
A
u
R
a
h
e
e
g
d
t
e
Wr
i
t
r
a
a
Read
Write (Write recovery)
CKE
o
w
d
ry
h
d
P
e
e
t
v
w
i
r
o
r
e
c
r
i
t
e
c
h
W
p
h
r
e
t
i
o
a
r
t
u
Wr
g
e
A
READ
SUSPEND
Read (write recovery)
CKE
CKE
WRITE
READ
WRITE
SUSPEND
CKE
Write
h
c
R
t
i
w
e
e
g
a
e
A
r
d
c
u
e
a
t
w
h
a
t
i
o
r
h
i
r
t
P
h
g
e
W
r
e
Write with
r
Read with
P
o
t
u
Auto Precharge
CKE
Auto Precharge
A
(
w
r
i
t
e
P
r
e
c
o
R
v
e
r
E
y
)
(
)
P
n
r
CKE
READA
o
WRITE A
SUSPEND
e
i
t
WRITE A
c
a
h
a
READ A
n
SUSPEND
i
CKE
CKE
r
g
m
r
e
e
t
t
e
e
r
m
g
r
i
a
n
a
h
c
t
i
e
o
r
n
P
)
(
E
R
P
Precharge
POWER
ON
Precharge
Automatic sequence
Manual input
Note: After the AUTO refresh operation, precharge operation is
performed automatically and enter the IDLE state
Integrated Circuit Solution Inc.
DR007-0A
9
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
COMMAND TRUTH TABLE
CKE
A11
Symbol
Commandn-1
n
CS
RAS CAS
WE
BA
A10 A9-A0
DESL
NOP
Device deselect
No operation
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
X
H
L
X
H
L
X
X
L
X
X
L
X
X
V
V
V
V
V
V
X
X
X
X
X
MRS
Mode register set
Bank activate
ACT
L
H
L
H
H
H
L
V
V
V
V
V
V
X
X
X
X
V
L
READ
READA
WRIT
WRITA
PRE
Read
H
H
H
H
L
Read with auto precharge
Write
L
H
L
L
Write with auto precharge
Precharge select bank
Precharge all banks
Burst stop
L
L
H
L
H
H
H
L
L
PALL
BST
L
L
H
X
X
X
H
L
L
REF
CBR (Auto) refresh
Self refresh
H
H
SELF
L
L
Notes:
H : High level
X : High or Low level (Dont care)
L : Low level
V : Valid Data input
DQM TRUTH TABLE
CKE
Symbol
Commandn-1
n
DQM
ENB
Data Write / Output Enable
Data Mask / Output Disable
H
H
X
X
L
MASK
H
CKE TRUTH TABLE
CKE
Symbol
CommandCurrent
State
n-1
n
CS
RAS CAS
WE
Addreess
Clock suspend mode entry
Clock suspend
Activating
Any
H
L
L
L
X
X
X
L
X
X
X
L
X
X
X
L
X
X
X
H
H
X
X
X
X
X
Clock suspend mode exit
CBR refresh command
Self refresh entry
Clock suspend
Idle
L
H
H
L
REF
SELF
H
H
Idle
L
L
L
Self refresh exit
Self refresh
L
L
H
H
L
H
X
H
X
H
X
X
X
H
Power down entry
Power down exit
Idle
H
L
L
X
X
X
X
X
X
X
X
X
X
Power down
H
10
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
OPERATION COMMAND TABLE(1)
Current
State CommandOperation
CS
RAS CAS
WE
Address
Idle
DESL
NOP or Power-Down(2)
NOP or Power-Down(2)
Illegal(3)
Illegal(3)
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
H
H
H
L
X
H
L
X
X
H
L
X
NOP or BST
READ / READA
WRIT/WRITA
ACT
X
BA, CA, A10
BA, CA, A10
BR, RA
BA, A10
X
L
Row Active
H
H
L
H
L
PRE/PALL
REF/SELF
MRS
NOP
L
Refresh or Self-Refresh(4)
Mode Register Set
NOP
L
H
L
L
L
Op-Code
X
Row Active
DESL
X
H
H
H
L
X
H
L
X
H
H
L
NOP or BST
READ/READA
WRIT/WRITA
ACT
NOP
X
Begin read : Determine AP(5)
Begin write : Determine AP(5)
Illegal(3)
BA, CA, A10
BA, CA, A10
BR, RA
BA, A10
X
L
H
H
L
H
L
PRE/PALL
REF/SELF
MRS
Precharge(6)
L
Illegal
L
H
L
Illegal
L
L
Op-Code
X
Read
DESL
Continue burst to -> end Row active
Continue burst to -> end Row active
Burst stop -> Row active
Term burst, new read : Determine AP(7)
Term burst, start write : Determine AP(7, 8)
Illegal(3)
X
H
H
H
H
L
X
H
H
L
X
H
L
NOP
X
BST
X
READ/READA
WRIT/WRITA
ACT
H
L
BA, CA, A10
BA, CA, A10
BR, RA
BA, A10
X
L
H
H
L
H
L
PRE/PALL
REF/SELF
MRS
Term burst, precharging
Illegal
L
L
H
L
Illegal
L
L
Op-Code
X
Write
DESL
Continue burst to end -> write recovering
Continue burst to end -> write recovering
Burst stop -> Row active
Term burst, start read : Determine AP(7, 8)
Term burst, new write : Determine AP(7)
Illegal(3)
X
H
H
H
H
L
X
H
H
L
X
H
L
NOP
X
BST
X
READ/READA
WRIT/WRITA
ACT
H
L
BA, CA, A10
BA, CA, A10
BR, RA
BA, A10
X
L
H
H
L
H
L
PRE/PALL
REF/SELF
MRS
Term burst, precharging(9)
L
Illegal
L
H
L
Illegal
L
L
Op-Code
Read With
Auto-
DESL
NOP
Continue burst to end -> Precharging
Continue burst to end -> Precharging
H
L
X
H
X
H
X
H
X
X
Precharge
BST
Illegal
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
X
READ/READA
WRIT/WRITA
ACT
Illegal(11)
Illegal(11)
Illegal(3)
Illegal(11)
Illegal
BA, CA, A10
BA, CA, A10
BR, RA
BA, A10
X
L
H
H
L
H
L
PRE/PALL
REF/SELF
MRS
L
L
H
L
Illegal
L
L
Op-Code
Integrated Circuit Solution Inc.
DR007-0A
11
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
OPERATION COMMAND TABLE(continue)
Current
State CommandOperation
CS
RAS CAS
WE
Address
Write with auto DESL
Continue burst to end -> write recovering with auto precharte H
Continue burst to end -> write recovering with auto precharte L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
precharge
NOP
X
BST
Illegal
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
READ / READA
WRIT/WRITA
ACT
Illegal(11)
Illegal(11)
Illegal(3, 11)
Illegal(3, 11)
H
L
BA, CA, A10
BA, CA, A10
BR, RA
BA, A10
X
L
H
H
L
H
L
PRE/PALL
REF/SELF
MRS
L
Illegal
L
H
L
Illegal
L
L
Op-Code
X
Precharging
DESL
Nop -> Enter idle after tRP
X
H
H
H
H
L
X
H
H
L
X
H
L
NOP
Nop -> Enter idle after tRP
X
BST
Nop -> Enter idle after tRP
Illegal(3)
X
READ/READA
WRIT/WRITA
ACT
H
L
BA, CA, A10
BA, CA, A10
BR, RA
BA, A10
X
Illegal(3)
Illegal(3)
L
H
H
L
H
L
PRE/PALL
REF/SELF
MRS
Nop -> Enter idle after tRP
L
Illegal
L
H
L
Illegal
L
L
Op-Code
X
Row activating
DESL
Nop - > Enter row active after tRCD
X
H
H
H
H
L
X
H
H
L
X
H
L
NOP
Nop - > Enter row active after tRCD
X
BST
Nop - > Enter row active after tRCD
X
READ/READA
WRIT/WRITA
ACT
Illegal(3)
Illegal(3)
Illegal(3, 9)
Illegal(3)
Illegal
H
L
BA, CA, A10
BA, CA, A10
BR, RA
BA, A10
X
L
H
H
L
H
L
PRE/PALL
REF/SELF
MRS
L
L
H
L
Illegal
L
L
Op-Code
Write
DESL
NOP
Nop -> Enter row active after tDPL
Nop -> Enter row active after tDPL
H
L
X
H
X
H
X
H
X
X
recovering
BST
Nop -> Enter row active after tDPL
Start read, Determine AP(8)
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
X
READ/READA
WRIT/WRITA
ACT
BA, CA, A10
BA, CA, A10
BR, RA
BA, A10
X
New write, Determine AP
L
Illegal(3)
Illegal(3)
Illegal
H
H
L
H
L
PRE/PALL
REF/SELF
MRS
L
L
H
L
Illegal
L
L
Op-Code
12
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
OPERATION COMMAND TABLE(continue)
Current
State CommandOperation
CS
RAS CAS
WE
Address
Write
DESL
Nop -> Enter precharge after tDPL
H
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
recovering
with auto
precharge
NOP
Nop -> Enter precharge after tDPL
X
BST
Nop -> Enter precharge after tDPL
Illegal(3 ,8, 11)
Illegal(3,11)
Illegal(3, 11)
X
READ/READA
WRIT/WRITA
ACT
H
L
BA, CA, A10
L
BA, CA, A10
H
H
L
H
L
BR, RA
PRE/PALL
REF/SELF
MRS
Illegal(3, 11)
L
BA, A10
Illegal
L
H
L
X
Illegal
L
L
Op-Code
Auto
DESL
Nop Enter idle after tRC
X
H
H
L
X
H
L
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
Refreshing
NOP/BST
READ/WRIT
ACT/PRE/PALL
REF/SELF/MRS
DESL
Nop Enter idle after tRC
Illegal
Illegal
H
L
Illegal
L
Mode
Nop -> Enter idle after 2 Clocks
X
H
H
H
L
X
H
H
L
register
setting
NOP
Nop -> Enter idle after 2 Clocks
BST
Illegal
Illegal
Illegal
READ/WRIT
ACT/PRE/PALL/
REF/SELF/MRS
X
X
X
Notes:
1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode. All input buffers except CKE
will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by BankAddress(BA), depending on the
state of that bank.
4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode. All input buffers except CKE
will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which dont satisfy tDPL .
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks in multi-bank devices.
Integrated Circuit Solution Inc.
DR007-0A
13
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
CKE RELATED COMMAND TRUTH TABLE(1)
CKE
n-1
Current State
Operation
n
CS
RAS CAS
WE
Address
Self-Refresh (S.R.)
INVALID, CLK (n - 1)would exit S.R.
Self-Refresh Recovery(2)
Self-Refresh Recovery(2)
Illegal
H
L
X
H
H
H
H
L
X
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
Illegal
L
L
X
X
X
H
L
Maintain S.R.
L
X
H
L
X
X
H
H
L
Self-Refresh Recovery
Idle After tRC
H
H
H
H
H
H
H
H
L
H
H
H
H
L
Idle After tRC
Illegal
L
Illegal
L
X
X
H
L
Begin clock suspend next cycle(5)
Begin clock suspend next cycle(5)
Illegal
H
L
X
H
H
L
L
L
L
Illegal
L
L
X
X
X
X
Exit clock suspend next cycle(2)
Maintain clock suspend
INVALID, CLK (n - 1) would exit P.D.
H
L
X
X
X
X
X
X
L
Power-Down (P.D.)
Both Banks Idle
H
X
EXIT P.D. -> Idle(2)
L
L
H
L
X
X
X
X
X
X
X
X
X
X
Maintain power down mode
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Auto-Refresh
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
L
X
H
L
X
X
H
L
X
X
X
H
L
L
L
L
X
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Self-Refresh(3)
L
L
L
Op - Code
H
L
X
H
L
X
X
H
L
X
X
X
H
L
L
L
L
L
L
L
X
Refer to operations in Operative Command Table
Power-Down(3)
L
L
L
L
Op - Code
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Any state
Refer to operations in Operative Command Table
Begin clock suspend next cycle(4)
H
H
L
other than
listed above
Exit clock suspend next cycle
H
L
Maintain clock suspend
L
Notes:
1. H : Hight level, L : low level, X : High or low level (Dont care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied
before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if tSREX is not satisfied.
14
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Initiallization
CAS Latency
Before starting normal operation, the following power on
sequence is necessary to prevent SDRAM from damged
or malfunctioning.
CAS latency is the most critical parameter being set. It
tells the device how many clocks must elapse before the
data will be available.
The value is determined by the frequency of the clock and
the speed grade of the device. The value can be pro-
grammed as 2 or 3.
1. Apply power and start clock. Attempt to maintain CKE
high , DQN high and NOP condition at the inputs.
2. Maintain stable power, table clock , and NOP input
conditions for a minimum of 200us.
3. Issue precharge commands for all bank. (PRE or
PREA)
Burst Length
4. After all banks become idle state (after tRP), issue 8
or more auto-refresh commands.
5. Issue a mode register set command to initialize the
mode regiser.
Burst Length is the number of words that will be output or
input in read or write cycle. After a read burst is completed,
the output bus will become high impedance.
The burst length is programmable as 1, 2, 4, 8 or full page.
After these sequence, the SDRAM is in idle state and
ready for normal operation.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data
will be addressed. The order is programmable as either
Sequential or Interleave. The method chosen will
depend on the type of CPU in the system.
Programming the Mode Register
The mode register is programmed by the mode register
set command using address bits A13 through A0 as data
inputs. The register retains data until it is reprogrammed
or the device loses power.
The mode register has four fields;
Options : A13 through A7
CAS latency : A6 through A4
Wrap type : A3
Burst length : A2 through A0
Following mode register programming, no command can
be asserted befor at least two clock cycles have elapsed.
Integrated Circuit Solution Inc.
DR007-0A
15
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
MODE REGISTER
13
0
6
12
0
10
0
7
1
3
11
0
9
0
8
0
4
4
2
2
2
1
5
5
0
0
0
JEDEC Standard Test Set
12
x
1
11 10
x
x
13
x
8
0
3
WT
9
1
7
0
6
6
Burst Read and Single Write (for Write Through Cache)
LTMODE
BL
13
0
1
12 11
0
10
0
8
0
5
3
WT
9
0
7
0
4
Burst Read and Burst Write
X = Don’t care
0
BL
LTMODE
Bits2 - 0
WT = 1
1
WT = 0
1
000
001
010
011
100
101
110
111
2
4
2
4
8
8
Burst length
R
R
R
R
R
R
R
Fullpage
0
1
Sequential
Interleave
Wrap type
Bits 6-4
000
CAS Iatency
R
R
2
001
010
011
100
101
110
111
3
Latency
mode
R
R
R
R
Remark R : Reserved
16
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Burst Length and Sequence
Burst of Two
Starting Address
(column address A0, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing Sequence
(decimal)
0, 1
1, 0
0
1
0, 1
1, 0
Burst of Four
Starting Address
(column address A1 - A0, binary)
Sequential Addressing
Sequence (decimal)
0, 1, 2, 3
Interleave Addressing Sequence
(decimal)
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
00
01
10
11
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
Burst of Eight
Starting Address
(column address A2 - A0, binary)
Sequential Addressing
Sequence (decimal)
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1 ,2
4, 5, 6, 7, 0, 1, 2, 3
5, 6 ,7, 0, 1, 2, 3, 4
6, 7 ,0 ,1 ,2 ,3 ,4 ,5
7, 0, 1, 2, 3, 4, 5, 6
Interleave Addressing Sequence
(decimal)
000
001
010
011
100
101
110
111
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being
512 (for 8M x 8) and 256 (for 4Mx16).
Integrated Circuit Solution Inc.
DR007-0A
17
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Address Bits of Bank-Select and Precharge
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
Row
(Activate command)
A12
0
A13 Result
0
1
0
1
Select Bank A
“Activate “ command
0
1
1
Select Bank B
“Activate” command
Select Bank C
“Activate” command
Select Bank D
“Activate” command
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
Row
A10 A12 A13 Result
(Precharge command)
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Precharge Bank A
Precharge Bank B
Precharge Bank C
Precharge Bank D
Precharge All Banks
X: Don't care
0
1
Disables Auto-Precharge (End of Burst)
Enables Auto - Precharge (End of Burst)
A12
0
A13 Result
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
Co1.
(CAS strobes)
0
1
0
1
Enables Read/Write
commands for Bank A
0
1
1
Enables Read/Write
commands for Bank B
Enables Read/Write
commands for Bank C
Enables Read/Write
commands for Bank D
18
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Precharge
The precharge command can be asserted anytime after tRAS(min.) is satisfied.
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters
the idle state after tRP(min.) is satisfied. The parameter t RP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as
follows.
PrechargeE
Burst lengh=4
T0
T1
T3
T6
T2
T4
T5
T7
CLK
Command
Read
PRE
Q2
CAS latency = 2
Hi - Z
DQ
Q0
Q1
Q3
Command
CAS latency = 3
DQ
Read
PRE
Q1
Hi - Z
Q3
Q2
Q0
(tRAS is satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter tDPL must be satisfied. The tDPL(min.)
specification defines the earliest time that a precharge command can be asserted. The minimum number of clocks can be
calculated by dividing tDPL(min.) with the clock cycle time.
In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
CAS
latency
ReadWrite
+ tDPL((min.)
+ tDPL((min.)
2
3
-1
-2
Integrated Circuit Solution Inc.
DR007-0A
19
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high in the read or write
command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and
begins automatically.
In the write cycle, tDAL(min.) must be satisfied before asserting the next activate command to the bank being precharged.
When using auto precharge in the read cycle, knowing when the precharge starts is important because the next activate
command to the bank being precharged cannot be executed until the precharge cycle ends. Once auto precharge has
started, an activate command to the bank can be asserted after tRP has been satisfied.
A Read or Write command without auto - precharge can be terminated in the midst of a burst operation. However, a Read
or Write command with auto - precharge can not be interrupted by the same bank commands before the entire burst opera-
tion is completed. Therefore use of the same bank Read, Write, Precharge or Burst Stop command is prohibited during a
read or write cycle with auto - precharge. It should be noted that the device will not respond to the Auto - Precharge com-
mand if the device is programmed for full page burst read or write cycles.
The timing when the auto precharge cycle begins depends both on both the CAS Iatency programmed into the mode reg-
ister and whether the cycle is read or write.
Read with Auto Precharge
During a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two clocks earlier (CL = 3) than the last word
output.
READ with AUTO PRECHARGE
Burst lengh = 4
T0
T1
T3
T6
T2
T4
T5
T7
T8
CLK
No New Command to Bank B
Auto precharge starts
Command
READA B
CAS latency = 2
Hi - Z
DQ
QB0
QB1
QB2
QB3
No New Command to Bank B
Auto precharge starts
Command
READA B
CAS latency = 3
Hi - Z
DQ
QB3
QB0
QB2
QB1
Remark READA means READ with AUTO PRECHARGE
20
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of tDPL(min.) after the last data word
input to the device.
WRITE with AUTO PRECHRGE
Burst lengh = 4
T0
T1
T3
T6
T8
T
2
T4
T5
T7
CLK
Command
AUTO PRECHARGE starts
WRITA B
DB0
t
DPL
CAS latency = 2
Hi - Z_
DQ
DB2
DB3
DB1
AUTO PRECHARGE starts
Command
WRITA B
DB0
t
DPL
CAS latency = 3
Hi - Z
DQ
DB2
DB1
DB3
Remark WRITA means WRITE with AUTO Precharge
In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. In the
table below, minus means clocks before the reference; plus means clocks after the reference.
CAS
latency
ReadWrite
+ tDPL((min.)
+ tDPL((min.)
2
3
-1
-2
Integrated Circuit Solution Inc.
DR007-0A
21
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Read / Writw Command Interval
Read to Read Command Interval
During a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previ-ous
read operation has not completed. READ will be interrupted by another READ.
Each read command can be asserted in every clock without any restriction.
READ to READ Command Interval
Burst lengh=4, CAS latency=2
T0
T1
T3
T6
T2
T4
T5
T7
T8
CLK
Read B
Read A
Command
Hi-Z_
DQ
QA0
QB0
QB1
QB2
QB3
1 cycle
Write to Write Command Interval
During a write cycle, when a new Write command is asserted, the previous burst will terminated and the new burst will begin
with a new write command. WRITE will be interrupted by another WRITE.
Each write command can be asserted in every clock without any restriction.
WRITE to WRITE Command Interval
Burst lengh=4, CAS latency=2
T0
T1
T3
T6
T7
T2
T4
T5
T8
CLK
Write B
Write A
Command
Hi-Z_
QA0
QB0
DQ
QB1
QB2
QB3
1 cycle
22
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Write to Read Command Interval
The write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command
will be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT.
WRITE to READ Command Interval
Burst lengh=4
T0
T1
T3
T6
T8
T2
T4
T5
T7
CLK
1 cycle
Read B
Command
WRITE A
CAS latency=2
Hi-Z
DA0
QB0
QB1
QB2
QB3
DQ
Write A
DA0
Command
Read B
CAS latency=3
Hi-Z
QB0
QB1
QB3
QB2
DQ
Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE.
DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data conflict. The data
bus must be Hi-Z using DQM before Write.
Integrated Circuit Solution Inc.
DR007-0A
23
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
READ to WRITE Command Interval
CAS latency=2
T8
T7
T0
T1
T3
T6
T2
T4
T5
CLK
Read
Write
Command
DQM
DQ
Hi-Z
D0
D1
D2
D3
1 cycle
Burst length=8, CAS latency=2
T8 T9
T7
T0
T1
T3
T6
T2
T4
T5
CLK
Command
DQM
Write
Read
Q2
D2
Q0
Q1
D0
D1
DQ
Hi-Z is
necessary
example: Burst length=4, CAS latency=3
T6
T0
T1
T3
T8
T2
T4
T5
T7
CLK
Command
Read
Write
DQM
DQ
Q2
D0
D2
D1
Hi-Z is
necessary
24
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
BURST Termination
There are two methods to terminate a burst operation other than using a read or a write command. One is the burst stop
command and the other is the precharge command.
BURST Stop Command
During a read burst, when the burst stop command is issued, the burst read data are terminated and the data bus goes to
high-impedance after the CAS latency from the burst stop command.
During a write burst, when the burst stop command is issued, the burst write data are termained and data bus goes to Hi-
Z at the same clock with the burst stop command.
Burst Termination
Burst lengh=X, CAS Intency=2,3
T7
T0
T1
T3
T6
T2
T4
T5
CLK
BST
Read
Command
Hi-Z
CAS latency=2
Q0
Q1
Q0
Q2
Q1
DQ
Hi-Z
CAS latency=3
Q2
DQ
Remark BST: Burst stop command
Burst lengh=X, CAS latency=2,3
T7
T0
T1
T3
T6
T2
T4
T5
CLK
BST
Write
Command
CAS latency=2,3
Hi-Z_
Q0
Q0
Q1
Q2
DQ
Remark BST: Burst command
Integrated Circuit Solution Inc.
DR007-0A
25
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
PRECHARGE TERMINATION
PRECHARGE TERMINATION in READ Cycle
During READ cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after t RP from the precharge command.
When CAS latency is 2, the read data will remain valid until one clock after the precharge command.
When CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Precharge Termination in READ Cycle
Burst lengh= X
T8
T7
T0
T1
T3
T6
T2
T4
T5
CLK
Read
PRE
Q2
ACT
Command
tRP
CAS latency=2
Hi-Z
DQ
Q0
Q3
Q1
command
ACT
Read
PRE
tRP
CAS latency=3
Hi-Z
DQ
Q0
Q3
Q2
Q1
26
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Precharge Termination in WRITE Cycle
During WRITE cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command. The DQM must be high to mask
invalid data in.
During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid
data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high
at the same clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
Burst lengh = X
T0
T1
T3
T6
T8
T2
T4
T5
T7
CLK
Write
PRE
ACT
Command
CAS latency = 2
DQM
Hi - Z
DQ
D0
D3
D2
D4
D1
tRP
command
Write
PRE
ACT
CAS latency = 3
DQM
Hi - Z
tRP
DQ
D0
D3
D2
D4
D1
Integrated Circuit Solution Inc.
DR007-0A
27
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Mode Register Set
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
CKE
CS
t
RSC
RAS
CAS
WE
BS0,1
A10
Address Key
ADD
DQM
DQ
t
RP
Hi-Z
Precharge
Command
All Banks
Mode Register
Set
Command
Command
28
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
AC Parameters for Write Timing (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CL
t
CK2
t
CH
t
Begin Auto Precharge
Bank A
Begin Auto Precharge
Bank B
CMS
t
t
CKS
CKH
t
CMH
CS
RAS
CAS
WE
*BS0
A10
t
AH
t
AS
ADD
DQM
DQ
t
RCD
t
t
t
DAL
DS
RRD
t
t
t
RC
DPL
t
RP
DH
QAa0
QAa1
QBa1
QAb0 QAb1 QAb2
QBa2 QBa3 QAb3
QAa2 QAa3 QBa0
Activate
Command
Bank A
Write without
Activate
Command
Bank A
Activate
Command
Bank B
Write with Activate
Auto Precharge Command
Command Bank A
Bank B
Write with
Auto Precharge
Command
Precharge
Command
Bank A
Activate
Command
Bank B
Auto Precharge
Command
Bank A
Bank A
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
29
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
AC Parameters for Write Timing (2 of 2)
Burst Length=4, CAS Latency=3,4
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CLK
t
CL
t
t
CK3
CH
t
Begin Auto Precharge
Bank A
Begin Auto Precharge
Bank B
CMS
t
t
CKE
CS
CKS
CKH
t
CMH
RAS
CAS
WE
*BS0
A10
t
AH
t
AS
ADD
DQM
DQ
t
RCD
t
t
t
DAL
RRD
DS
t
t
RC
DPL
RP
t
DH
QAa0
QAa1
QAa2
QBa2
QAb3
QAb0 QAb1 QAb2
QAa3 QBa0 QBa1
QBa3
Precharge
Command
Bank A
Write without
Auto Precharge
Command
Activate
Command
Bank A
Activate
Command
Bank A
Write with
Activate
Command
Bank B
Write with
Auto Precharge
Command
Activate
Command
Bank A
Auto Precharge
Command
Bank A
Bank A
Bank B
BS1=L, Bank C,D = Idle
30
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
AC Parameters for Read Timing (1 of 2)
Burst Length=2, CAS Latency=2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11 T12 T13
CLK
CKE
CS
t
t
t
CH CL
CK2
t
Begin Auto
Precharge
Bank B
t
CMS
CKH
t
CMH
t
CKS
RAS
CAS
WE
*BS0
A10
t
AH
t
AS
ADD
t
RRD
t
RAS
t
RC
DQM
DQ
t
t
t
t
AC2
AC2
HZ
RP
t
t
t
RCD
t
t
OH
LZ
OH
HZ
Hi-Z
QBa0
QAa0
QBa1
QAa1
Activate
Command
Bank A
Read with
Auto Precharge
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
31
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
AC Parameters for Read Timing (2 of 2)
Burst Length=2, CAS Latency=3
T0
T1 T2
T3
T4 T5
T6
T7 T8
T9 T10 T11 T12 T13 T14 T15
CLK
t
t
t
CH
CL
CK3
Begin Auto
Precharge
Bank B
t
CKE
CS
CMS
t
CKS
t
t
CMH
CKH
RAS
CAS
WE
*BS0
A10
t
AH
AS
t
ADD
t
RRD
t
t
RAS
RP
t
RC
DQM
t
t
t
AC3
HZ
AC3
t
t
t
t
t
OH
OH
RCD
LZ
HZ
Hi-Z
QBa0
QBa1
QAa0
QAa1
DQ
Read with
Auto Precharge
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
BS1=L, Bank C,D = Idle
32
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Power on Sequence and Auto Refresh (CBR)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
High level
is required
RSC
Minimum of 8 Refresh Cycles are required
CS
RAS
CAS
WE
BS0, 1
A10
Address Key
ADD
DQM
High Level is Necessary
t
t
RC
RP
Hi-Z
DQ
2nd Auto
Refresh
Command
Command
Register
Set Command
Precharge
Command
All Banks
Mode
1st Auto
Refresh
Command
Inputs
must
be stable
for 200us
Integrated Circuit Solution Inc.
DR007-0A
33
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Clock Suspension During Burst Read (Using CKE) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
CS
RAS
CAS
WE
*BS0
A10
RAa
RAa
CAa
ADD
DQM
DQ
t
HZ
Hi-Z
QAa0
QAa1
QAa2
QAa3
Clock
Suspended
3 Cycles
Clock
Suspended
2 Cycles
Clock
Suspended
1 Cycle
Read
Command
Bank A
Activate
Command
Bank A
BS1=L, Bank C,D = Idle
34
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Clock Suspension During Burst Read (Using CKE) (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
CS
RAS
CAS
WE
*BS0
A10
RAa
CAa
RAa
ADD
DQM
t
HZ
Hi-Z
QAa1
QAa0
QAa2
QAa3
DQ
Clock
Suspended
1 Cycles
Clock
Suspended
2 Cycles
Clock
Suspended
3 Cycles
Read
Command
Bank A
Activate
Command
Bank A
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
35
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Clock Suspension During Burst Write (Using CKE) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
t
CK2
RAS
CAS
WE
*BS0
A10
RAa
RAa
CAa
ADD
DQM
Hi-Z
DAa0
DAa1
DAa2
DAa3
DQ
Clock
Suspended
1 Cycle
Clock
Suspended
3 Cycles
Clock
Suspended
2 Cycles
Activate
Command
Bank A
Write
Command
Bank A
BS1=L, Bank C,D = Idle
36
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Clock Suspension During Burst Write (Using CKE) (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
CS
RAS
CAS
WE
*BS0
A10
RAa
CAa
RAa
ADD
DQM
Hi-Z
DAa0
DAa1
DAa2
DAa3
DQ
Clock
Suspended
2 Cycles
Clock
Suspended
3 Cycles
Clock
Suspended
1 Cycle
Activate
Command
Bank A
Write
Command
Bank A
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
37
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Power Down Mode and Clock Mask
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
t
t
CK2
CKH
CKS
t
CKS
VALID
CS
RAS
CAS
WE
*BS0
A10
RAa
RAa
CAa
ADD
DQM
Hi-Z
QAa0
QAa1
QAa2
DQ
QAa3
ACTIVE
STANDBY
Precharge
Standby
Power
Down
Mode
Exit
Precharge
Command
Read
Command
Bank A
Activate
Command
Bank A
Power Down
Mode Entry
Command
Clock Mask
Start
Clock Mask
End
Power Down
Mode Exit
Power Down
Mode Entry
BS1=L, Bank C,D = Idle
38
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Auto Refresh (CBR)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
t
CK2
RAS
CAS
WE
*BS0, 1
A10
RAa
CAa
RAa
ADD
DQM
t
t
t
RC
RC
RP
Hi-Z
Q2
Q0
Q1
Q3
DQ
Activate
Command
Read
Command
Precharge
Command
All Banks
CBR Refresh
Command
CBR Refresh
Command
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
39
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Self Refresh (Entry and Exit)
CLK can be Stopped**
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
t
SRX
SRX
t
CKS
t
CKS
CS
RAS
CAS
WE
*BS0
A10
ADD
DQM
t
t
RC
RC
Hi-Z
DQ
All Banks
must be idle
Self refresh
Entry
Self Refresh
Exit
Self Refresh
Entry
Activate
Command
Self Refresh
Exit
BS1=L, Bank C,D = Idle
Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High
40
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Random Column Read (Page With Same Bank) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
RAa
RAd
RAd
CAb
CAc
CAa
CAd
ADD
DQM
Hi-Z
QAa0 QAa1
QAa2 QAa3 QAb0
QAc0 QAc1 QAc2
QAc3
QAb1
QAd2
QAd1
QAd3
QAd0
DQ
Read
Command Command
Bank A
Precharge
Activate
Precharge
Command
Bank A
Read
Read
Command
Bank A
Read
Command
Bank A
Command
Bank A
Command
Bank A
Bank A
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
41
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Random Column Read (Page With Same Bank) (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
t
CK3
RAS
CAS
WE
*BS0
A10
RAa
RAa
RAd
RAd
CAb
CAc
CAa
CAd
ADD
DQM
Hi-Z
QAc2 QAc3
QAa0 QAa1 QAa2
Read
QAb0 QAb1 QAc0
QAc1
QAa3
Read
DQ
Precharge
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank A
Command
Command
Bank A
Bank A
BS1=L, Bank C,D = Idle
42
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Random Column Write (Page With Same Bank) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
Rd
Rd
Cb
Cc
Ca
Cd
ADD
DQM
Hi-Z
Da0
Dc2 Dc3
Dd2 Dd3
Da1 Da2
Db0 Db1 Dc0
Dd0
Da3
Dc1
Dd1
DQ
Precharge
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
43
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Random Column Write (Page With Same Bank) (1 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
Rd
Rd
Cb
Cc
Cd
Ca
ADD
DQM
Hi-Z
Da0
Dc2 Dc3
Da1 Da2
Db0 Db1
Write
Dc0
DQ
Da3
Dc1
Dd0
Dd1
Precharge
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Command
Bank B
BS1=L, Bank C,D = Idle
44
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Random Row Read (Interleaving Banks) (1 of 2)
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
CS
RAS
CAS
WE
*BS0
A10
ADD
t
t
t
AC2
RP
RCD
DQM
Hi-Z
QBb1
QBb0
QBa0
QBa5 QBa6 QBa7
QAa0
QAa1 QAa2
Active
DQ
QBa4
QBa1 QBa2
QAa3 QAa4
QAa6 QAa7
Read
QBa3
QAa5
Activate
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank A
Command
Bank B
Command
Bank B
Read
Command
Bank A
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
45
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Random Row Read (Interleaving Banks) (2 of 2)
Burs tLength=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
CS
RAS
CAS
WE
*BS0
A10
ADD
t
t
t
AC3
RP
RCD
DQM
Hi-Z
QBa5
Read
QBa0
QBa4
QBa6 QBa7 QAa0 QAa1 QAa2
QBb0
QAa7
QBa2
QAa4
QBa1
QAa3
QAa6
QBa3
QAa5
Read
DQ
Read
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Precharge
Command
Bank A
Command
Bank A
Command
Bank B
BS1=L, Bank C,D = Idle
46
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Random Row Write (Interleaving Banks) (1 of 2)
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
CS
RAS
CAS
WE
*BS0
A10
ADD
DQM
t
t
t
RCD
DPL
RP
Hi-Z
QAa5
QAa0
Write
QAa4
QAa6 QAa7 QBa0 QBa1 QBa2
Precharge
QAb2
QAb3 QAb4
QAb0 QAb1
DQ
QAa1 QAa2
QBa3 QBa4
QBa6 QBa7
QBa5
QAa3
Activate
Command
Bank A
Write
Command
Bank A
Active
Command
Bank A
Activate
Command
Bank B
Command
Bank A
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
47
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Random Row Write (Interleaving Banks) (2 of 2)
Burst Length=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK
High
CS
RAS
CAS
WE
*BS0
A10
ADD
t
t
t
DQM
DPL
DPL
RP
Hi-Z
QAa4
QAa3
QAa5 QAa6 QAa7 QBa0 QBa1
QAb1
QAb2 QAb3
QBb7 QAb0
QAa0 QAa1
QBa2 QBa3
QBa5 QBa6
QBa4
QAa2
DQ
Write
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank A
BS1=L, Bank C,D = Idle
48
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Read and Write Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
*BS0
A10
RAa
CAb
RAa
CAa
CAc
ADD
DQM
DQ
Hi-Z
DAb0
Write
QAa3
DAb1
DAb3
QAc0 QAc1
QAa1
QAa0
QAc3
QAa2
Read
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank A
The Write Data
The Read Data
is Masked with
Two Clocks
Latency
Command is Masked with a
Bank A
Zero Clock
latency
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
49
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Read and Write Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
*BS0
RAa
A10
CAa
CAb
RAa
CAc
ADD
DQM
DQ
Hi-Z
DAb0 DAb1
QAc0
QAc1
DAb3
QAa3
QAc3
QAa0 QAa1
QAa2
Write
Command
Bank A
Read
Command
Bank A
The Write Data
Activate
Command
Bank A
Read
Command
Bank A
The Read Data
is Masked with
Two Clock
is Masked with a
Zero Clock
Latency
Latency
BS1=L, Bank C,D = Idle
50
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Interleaved Column Read Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
*BS0
Ra
Ra
Ra
Ra
A10
Ca
Cb
Cc
Cb
Cd
Cb
ADD
t
t
DQM
AC2
RCD
Hi-Z
QBa0
Read
QBc0
QBc1 QAb0 QAb1 QBd0 QBd1
QBd2 QBd3
QAa3
QBa1 QBb0 QBb1
QAa0 QAa1
QAa2
DQ
Activate
Command
Bank A
Read
Read
Read
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank B
Command
Bank A
Command
Bank B
Command
Command
Bank A
Bank B
Precharge
Command
Bank A
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
51
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Interleaved Column Read Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
Ra
Ra
Ca
Cb
Cc
Cb
Ca
ADD
DQM
t
t
RCD
RRD
t
AC3
Hi-Z
QBa0
QBb0
QBc0
QAb0
QBc1 QAb1 QAb2 QAb3
QAa3
QBa1
Read
QBb1
Read
DQ
QAa1
Read
QAa0
QAa2
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Precharge
Command
Bank B
Precharge
Command
Bank A
Command
Bank B
Command
Bank A
Command
Bank B
Bank B
Activate
Command
Bank B
BS1=L, Bank C,D = Idle
52
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Interleaved Column Write Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
Ra
Ra
Ca
Cb
Cc
Cb
Cb
Ca
ADD
t
t
t
RCD
RP
DPL
DQM
t
RRD
Hi-Z
DBa0 DBa1 DBb0
DBc0 DBc1 DAb0 DBd0 DBd1 DBd2 DBd3
DAb1
DAa3
DBb1
DAa0 DAa1
DQ
DAa2
Activate
Command
Bank A
Write
Command
Bank A
Write
Command
Bank B
Write
Write
Precharge
Command
Bank A
Precharge
Command
Bank B
Write
Command
Bank A
Activate
Command
Bank B
Command
Bank B
Command
Bank B
Write
Command
Bank B
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
53
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Interleaved Column Write Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
*BS0
Ra
Ra
Ra
Ra
A10
Ca
Cb
Cc
Cb
Ca
Cd
ADD
t
t
t
t
RCD
DPL
DPL
DQM
t
RRD
RP
Hi-Z
QBa0 QBa1 QBb0
QBc0 QBc1 QAb0
QAb1 QBd0 QBd1 QBd2 QBd3
QAa3
QBb1
DQ
QAa0 QAa1
QAa2
Write
Command
Bank B
Write
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Write
Command
Bank B
Write
Precharge
Command
Bank B
Write
Command
Bank B
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank A
BS1=L, Bank C,D = Idle
54
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Auto Precharge after Read Burst (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
Start Auto Precharge
Bank A
Start Auto Precharge
Bank B
High
Start Auto Precharge
Bank B
CS
RAS
CAS
WE
*BS0
Ra
Ra
Ra
Rb
Rb
Rc
Rc
A10
Ca
Cb
Cb
Ca
Cc
Ra
ADD
DQM
Hi-Z
QBa0
QBa2
QAb0
QAb2
QAc1
QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc2
QAa3
QBa1
QBa3
QAb1
QAa1
DQ
QAa0
QAa2
Activate
Command
Bank A
Read with
Auto Precharge
Command
Read
Command
Bank A
Activate
Command
Bank B
Read with
Activate
Command
Auto Precharge
Command
Bank B
Read with
Bank A
Bank A
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Activate
Command
Bank B
Bank A
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
55
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Auto Precharge after Read Burst (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
t
CK3
Start Auto Precharge
Bank B
High
Start Auto
Precharge
Bank A
Start Auto Precharge
Bank B
RAS
CAS
WE
*BS0
Ra
Ra
Rb
Rb
Ra
A10
Ca
Ca
Cb
Ra
Cb
ADD
DQM
Hi-Z
QBa0
QAb0
DQ
QAa3
QBa1 QBa2 QBa3
QAb1 QAb2 QAb3
QBb0 QBb1 QBb2
QAa0 QAa1
QAa2
Activate
Command
Bank B
Write with
Activate
Command
Bank A
Activate
Command
Bank B
Read with
Read with
Auto Precharge
Command
Bank A
Auto precharge
Command
Bank B
Auto Precharge
Command
Bank B
Read
Command
Bank A
BS1=L, Bank C,D = Idle
56
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Auto Precharge after Write Burst (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
Start Auto Precharge
Bank B
High
Start Auto Precharge
Bank B
Start Auto Precharge
Bank A
CS
RAS
CAS
WE
*BS0
Ra
Ra
Rb
Rb
Rc
Rc
Ra
A10
Ca
Ca
Cb
Cb
Cc
Ra
ADD
DQM
Hi-Z
QBa0 QBa1 QBa2
QAb0 QAb1 QAb2
QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3
QAb3
QAa3
QBa3
QAa0 QAa1
Write
Command
Bank A
QAa2
DQ
Start Auto
Precharge
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Write with
Write with
Auto Precharge
Command
Bank B
Activate
Command
Bank B
Activate
Auto Precharge
Command
Bank A
Command
Bank B
Write with
Auto Precharge
Bank A
Write with
Auto Precharge
Command
Bank B
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
57
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Auto Precharge after Write Burst (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
t
CK3
Start Auto Precharge
Bank B
High
Start Auto
Precharge
Bank A
Start Auto Precharge
Bank B
RAS
CAS
WE
*BS0
Ra
Ra
Rb
Rb
Ra
A10
Ca
Ca
Cb
Ra
Cb
ADD
DQM
Hi-Z
QBb3
QBa0
QAb0
DQ
QAa3
QBa1 QBa2 QBa3
QAb1 QAb2 QAb3
Activate
QBb0 QBb1 QBb2
QAa0 QAa1
Activate
QAa2
Write with
Auto precharge
Command
Activate
Command
Bank A
Read with
Read with
Auto Precharge
Command
Bank A
Command
Bank B
Auto Precharge
Command
Bank B
Command
Bank B
Bank B
Read
Command
Bank A
BS1=L, Bank C,D = Idle
58
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Full Page Read Cycle (1 of 2)
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
t
CK2
High
RAS
CAS
WE
*BS0
A10
Ra
Rb
Rb
Ra
Ra
Ca
Ra
Ca
ADD
t
DQM
RP
Hi-Z
QBa+3
QBa+2
QAa+1 QBa QBa+1
QBa+6
QBa+4 QBa+51
QAa
QAa
QAa+1 QAa+2
QAa-1
QAa-2
DQ
Full page burst operation does not
terminate when the burst length is
satisfied; the burst counter
increments and continues bursting
beginning with the starting address
Read
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank A
Precharge
Command
Bank B
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Burst Stop
Command
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
59
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Full Page Read Cycle (2 of 2)
Burst Length=Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
CS
RAS
CAS
WE
*BS0
A10
Ra
Rb
Rb
Ra
Ra
Ca
Ra
Ca
ADD
DQM
Hi-Z
QBa+3
QBa+4
QBa+5
QAa-2
QAa+1
QBa+1
QBa+2
QAa+2
QAa
QBa0
QAa QAa+1
QAa-1
Read
DQ
Full page burst operation
does not teminate when
Read
Command
Bank A
Activate
Activate
Command
Bank A
Precharge
Command
Bank B
Activate
Command
Bank B
Command
Bank B
Command
Bank B
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Burst Stop
Command
BS1=L, Bank C,D = Idle
60
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Full Page Write Cycle (1 of 2)
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
CS
RAS
CAS
WE
*BS0
A10
Ra
Rb
Rb
Ra
Ra
Ca
Ra
Ca
ADD
DQM
t
BDL
Hi-Z
QAa+1
QBa+1
QBa+2
QAa
QBa
QBa+4
QBa+6
QBa+5
QAa QAa+1
QAa-1
QBa+3
DQ
QAa+2 QAa+3
Activate
Write
Data is ignored
Write
Activate
Command
Bank A
Activate
Command
Bank B
Command
Precharge
Command
Bank B
Bank B
Command
Bank A
Command
Bank B
Full page burst operation
does not terminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Burst Stop
Command
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
61
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Full Page Write Cycle (2 of 2)
Burst Length=Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
CS
RAS
CAS
WE
*BS0
A10
Ra
Rb
Rb
Ra
Ra
Ca
Ra
Ca
ADD
DQM
t
BDL
Data is ignored.
Hi-Z
DAa+1
DAa
DBa+1 DBa+2
DBa+4
DBa+3 DBa+5
DAa
DAa+1
DAa-1
DBa
DAa+2 DAa+3
Activate
DQ
Write
Write
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
Command
Bank B
Precharge
Command
Bank B
Command
Bank B
Full page burst operation
does not terminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Burst Stop
Command
BS1=L, Bank C,D = Idle
62
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Burst Read and Single Write Operation
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
High
CKE
CS
RAS
CAS
WE
*BS0
RAa
A10
CAa
RAa
CAd
CAc
CAe
CAb
ADD
DQM
Hi-Z
DQ
DQs are
Command masked
Bank A
Read
Single Write
Command
Bank A
Read
Activate
Command
Bank A
Single Write
Command
Bank A
Single Write
Command
Bank A
DQs are
masked
Command
Bank A
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
63
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Full Page Random Column Read
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
BS
Ra
Ra
Ra
Ra
Rb
Rb
A10
Ca
Ca
Cc
Cc
Cb
Cb
ADD
t
RP
DQM
DQ
Hi-Z
QBb1 QAc0
QAc2
QAa0 QBa0
QBb0
QAc1
QBc1 QBc2
QAb0 QAb1
Read
QBc0
Read
Precharge
(Bank D)
Read
Read
Activate
Command
Bank A
Activate
Command
Bank B
Command Bank B
(Precharge Termination)
Command
Bank B
Command
Bank B
Command
Bank A
Command
Bank B
Activate
Command
Bank B
Read
Command
Bank A
Read
Command
Bank A
BS1=L, Bank C,D = Idle
64
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Full Page Random Column Write
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
Ra
Ra
Rb
Rb
Ca
Ca
Cc
Cc
Cb
Cb
ADD
DQM
DQ
t
RP
Hi-Z
QAc0
QAa0
QBb0 QBb1
QAc2
QBc2
QBa0 QAb0
QAc1
QBc1
QAb1
QBc0
Write
Command
Bank B
Write
Command
Bank B
Precharge
Command Bank B
(Precharge Termination)
Write
Command
Bank A
Write
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
(Bank D)
Activate
Command
Bank B
Write Data
is masked
Write
Command
Bank A
Write
Command
Bank A
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
65
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Precharge Termination of a Burst (1 of 2)
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
CS
RAS
CAS
WE
*BS0
A10
RAa
RAb
RAb
RAc
RAc
RAa
CAa
CAb
CAc
ADD
DQM
DQ
t
t
t
t
RP
RP
DPL RP
Hi-Z
QAb1
QAa0
QAb0
QAc2
QAa1 QAa2
QAb2
QAc1
QAc0
Da3
Activate
Command
Bank A
Precharge
Command
Bank A
Activate
Read
Command
Bank A
Read
Command
Bank A
Precharge
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Command Command
Bank A
Bank A
Precharge Termination
of a Write Burst. Write
data is masked.
Precharge Termination
of a Read Burst.
BS1=L, Bank C,D = Idle
66
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
Precharge Termination of a Burst (2 of 2)
Burst Length=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
CS
RAS
CAS
WE
*BS0
A10
RAa
RAb
RAb
RAc
RAc
RAa
CAa
CAb
ADD
DQM
t
t
t
t
DPL
RAS
RP
RP
t
RCD
Hi-Z
QAb0 QAb1
QAb2 QAb3
DAa0 DAa1
DQ
Activate
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Precharge Termination
of a Read Burst.
Write Data
is masked
Precharge Termination
of a Write Burst.
BS1=L, Bank C,D = Idle
Integrated Circuit Solution Inc.
DR007-0A
67
IS42S8800/IS42S8800L
IS42S16400/IS42S16400L
ORDERING INFORMATION
Commercial Range: 0οC to 70οC
Speed (ns) Order Part No.
Package
7
8
7
8
IS42S8800-7T
IS42S8800L-7T
400mil TSOP-2
400mil TSOP-2
IS42S8800-8T
IS42S8800L-8T
400mil TSOP-2
400mil TSOP-2
IS42S16400-7T
IS42S16400L-7T
400mil TSOP-2
400mil TSOP-2
IS42S16400-8T
IS42S16400L-8T
400mil TSOP-2
400mil TSOP-2
ORDERING INFORMATION
Industrial Temperature Range: -40οC to 85οC
Speed (ns)
Order Part No.
Package
7
IS42S8800-7TI
IS42S8800L-7TI
400mil TSOP-2
400mil TSOP-2
8
7
8
IS42S8800-8TI
IS42S8800L-8TI
400mil TSOP-2
400mil TSOP-2
IS42S16400-7TI
IS42S16400L-7TI
400mil TSOP-2
400mil TSOP-2
IS42S16400-8TI
IS42S16400L-8TI
400mil TSOP-2
400mil TSOP-2
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
68
Integrated Circuit Solution Inc.
DR007-0A
相关型号：
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