ICS8521 [ICSI]
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER; 低偏移， 1到9差分至LVHSTL扇出缓冲器
| 型号： | ICS8521 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER |
| 文件： | 总13页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8521
LOW SKEW, 1-TO-9
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8521 is a low skew, 1-to-9 3.3V Differ- • 9 LVHSTL outputs
ential-to-LVHSTL Fanout Buffer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS8521 has two
selectable clock inputs. The CLK, nCLK pair can
• Selectable CLK, nCLK or LVPECL clock inputs
HiPerClockS™
• CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
accept most standard differential input levels. The PCLK,
nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The clock enable is internally synchronized to eliminate runt
pulseson the outputs during asynchronous assertion/
deassertion of the clock enable pin.
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency up to 500MHz
• Output skew: 50ps (maximum)
Guaranteed output skew, part-to-part skew and crossover
voltage characteristics make the ICS8521 ideal for today’s
most advanced applications, such as IA64 and static RAMs.
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1.8ns (maximum)
• VOH = 1.2V (maximum)
• 3.3V core, 1.8V output operating supply voltages
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
D
CLK_EN
Q
LE
CLK
nCLK
PCLK
nPCLK
0
1
32 31 30 29 28 27 26 25
Q0
1
2
3
4
5
6
7
8
VDD
CLK
nQ0
24
VDDO
23 Q3
22 nQ3
21 Q4
20 nQ4
19 Q5
18 nQ5
Q1
nQ1
nCLK
CLK_SEL
CLK_SEL
PCLK
Q2
nQ2
ICS8521
9 10 11 12 13 14 15 16
32-Lead LQFP
nPCLK
GND
Q3
nQ3
CLK_EN
17
VDDO
Q4
nQ4
Q5
nQ5
Q6
nQ6
7mm x 7mm x 1.4mm Package Body
Q7
nQ7
Y Package
Top View
Q8
nQ8
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ICS8521
LOW SKEW, 1-TO-9
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDD
Type
Description
1
2
3
Power
Input
Input
Positive supply pin. Connect to 3.3V.
Non-inverting differential clock input.
Inverting differential clock input.
CLK
Pulldown
Pullup
nCLK
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK.
4
CLK_SEL
Input
Pulldown
LVTTL / LVCMOS interface levels.
5
6
7
PCLK
nPCLK
GND
Input
Input
Pulldown
Pullup
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
Power supply ground. Connect to ground.
Power
Synchronizing clock enable. When HIGH, clock outputs follow
clock input. When LOW, Q outputs are forced low, nQ outputs
are forced high. LVCMOS /LVTTL interface levels.
8
CLK_EN
Input
Pullup
9, 16, 17,
24, 25, 32
VDDO
Power
Output supply pins. Connect to 1.8V.
10, 11
12, 13
14, 15
18, 19
20, 21
22, 23
26, 27
28, 29
30, 31
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3 Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Output
Output
Output
Output
Output
Output
Output
Output
Output
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
Differential output pair. LVHSTL interface level.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CLK, nCLK,
PCLK, nPLCK
4
4
pF
CIN
Input Capacitance
CLK_EN, CLK_SEL
pF
KΩ
KΩ
RPULLUP
Input Pullup Resistor
51
51
RPULLDOWN
Input Pulldown Resistor
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ICS8521
LOW SKEW, 1-TO-9
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Sourced
CLK, nCLK
Q0 thru Q8
Disabled; LOW
Disabled; LOW
Enabled
nQ0 thru nQ8
Disabled; HIGH
Disabled; HIGH
Enabled
0
0
1
1
0
1
0
1
PCLK, nPCLK
CLK, nCLK
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described
in Table 3B.
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0 - nQ8
Q0 - Q8
FIGURE 1: CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK or PCLK
nCLK or nPCLK
Q0 thru Q8
LOW
nQ0 thru nQ8
HIGH
0
1
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
HIGH
LOW
0
Biased; NOTE 1
LOW
HIGH
1
Biased; NOTE 1
HIGH
LOW
Biased; NOTE 1
Biased; NOTE 1
0
1
HIGH
LOW
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section on page 8, Figure 9, which discusses wiring the differential
input to accept single ended levels.
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ICS8521
LOW SKEW, 1-TO-9
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
47.9°C/W
Storage Temperature, TSTG
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDO
IDD
Positive Supply Voltage
3.465
2.0
V
V
Output Supply Voltage
Power Supply Current
1.6
1.8
60
80
mA
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
VIH
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK_EN, CLK_SEL
CLK_EN, CLK_SEL
2
3.765
0.8
V
VIL
-0.3
V
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
VIN = VDD = 3.465V
VIN = VDD = 3.465V
5
µA
µA
µA
µA
IIH
Input High Current
Input Low Current
150
VIN = 0V, VDD = 3.465V
VIN = 0V, VDD = 3.465V
-150
-5
IIL
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VDD = 3.465V
VIN = VDD = 3.465V
VIN = 0V, VDD = 3.465V
Minimum
Typical
Maximum Units
CLK
150
5
µA
µA
µA
µA
V
nCLK
CLK
-5
IIL
Input Low Current
nCLK
V
IN = 0V, VDD = 3.465V
-150
0.15
VPP
Peak-to-Peak Input Voltage
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
VDD - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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ICS8521
LOW SKEW, 1-TO-9
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
Minimum
Typical
Maximum Units
PCLK
150
5
µA
µA
µA
µA
V
nPCLK
PCLK
-5
IIL
Input Low Current
nPCLK
-150
0.3
VPP
Peak-to-Peak Input Voltage
1
Common Mode Input Voltage;
NOTE 1, 2
VCMR
1.5
VDD
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
TABLE 4E. LVHSTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Output High Voltage;
NOTE 1
VOH
1.0
1.2
V
Output Low Voltage;
NOTE 1
VOL
0
40% x (VOH - VOL) + VOL
0.6
0.4
60% x (VOH - VOL) + VOL
1.1
V
V
V
VOX
Output Crossover Voltage
Peak-to-Peak
Output Voltage Swing
VSWING
NOTE 1: Outputs terminated with 50Ω to ground.
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
fMAX Maximum Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum Units
500
1.8
50
MHz
ns
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
IJ 250MHz
1
tsk(o)
tsk(pp)
tR
ps
250
700
700
52
ps
20% to 80% @ 50MHz
20% to 80% @ 50MHz
300
300
48
ps
tF
Output Fall Time
ps
odc
Output Duty Cycle
%
All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
Measured from VDD/2 to the output differential crossing point for single ended input levels.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differntial cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the output are measurd
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8521
LOW SKEW, 1-TO-9
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VDDO
VDD
SCOPE
Qx
LVHSTL
VDD = 3.3V ± 5%
V
DDO = 1.8V ± 0.2V
nQx
GND = 0V
FIGURE 2 - OUTPUT LOAD TEST CIRCUIT
VDD
CLK, PCLK
VPP
VCMR
Cross Points
nCLK, nPCLK
GND
FIGURE 3 - DIFFERENTIAL INPUT LEVEL
Qx
nQx
Qy
nQy
tsk(o)
FIGURE 4 - OUTPUT SKEW
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ICS8521
LOW SKEW, 1-TO-9
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Qx
PART 1
nQx
Qy
PART 2
nQy
tsk(pp)
FIGURE 5 - PART-TO-PART SKEW
80%
80%
VSWING
20%
20%
Clock Inputs
and Outputs
tR
tF
FIGURE 6 - INPUT AND OUTPUT RISE AND FALL TIME
CLK, PCLK
nCLK, nPCLK
Q0, Q8
nQ0, nQ8
tPD
FIGURE 7 - PROPAGATION DELAY
CLK, PCLK
nCLK, nPCLK
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
FIGURE 8 - odc & tPERIOD
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ICS8521
LOW SKEW, 1-TO-9
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 9 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 9 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS8521
LOW SKEW, 1-TO-9
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8521.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8521 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 80mA = 277.2mW
Power (outputs)MAX = 32mW/Loaded Output pair
If all outputs are loaded, the total power is 9 * 32mW = 288mW
Total Power_MAX (3ꢀ465V, with all outputs switching) = 277ꢀ2mW + 288mW = 565ꢀ2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.565W * 42.1°C/W = 93.8°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance qJA for 32-pin LQFP, Forced Convection
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS8521
LOW SKEW, 1-TO-9
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in Figure 10.
VDD
Q1
VOUT
RL
Ω
50
FIGURE 10 - LVHSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
DD
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
)
OH_MAX
OH_MAX
L
DD_MAX
/R ) * (V
- V
)
OL_MAX
L
DD_MAX
OL_MAX
•
•
For logic high, V = V
= V
– 1.2V
OUT
OH_MAX
DD_MAX
For logic low, V = V
= V
– 0.4V
OUT
OL_MAX
DD_MAX
Pd_H = (1.2V/50Ω) * (2V - 1.2V) = 19.2mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
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ICS8521
LOW SKEW, 1-TO-9
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
200
0
500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8521 is: 944
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ICS8521
LOW SKEW, 1-TO-9
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 6. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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ICS8521
LOW SKEW, 1-TO-9
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS8521BY
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS8521BY
ICS8521BY
ICS8521BYT
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no
responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or
licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature
range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to
change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical
instruments.
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REV. B JULY 31, 2001
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