ICS8427DK-02 [ICSI]
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER; 500MHZ ，低抖动LVCMOS / CRYSTAL - TO- LVHSTL频率合成器
| 型号： | ICS8427DK-02 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER |
| 文件： | 总21页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS8427-02 is a general purpose, six • Six differential LVHSTL outputs
ICS
HiPerClockS™
LVHSTL output high frequency synthesizer
• Selectable crystal input interface orTEST_CLK input
and a member of the HiPerClockS™ family of
High Performance Clock Solutions from ICS.
The ICS8427-02 can support a very wide
• TEST_CLK accepts the following input types:
LVCMOS, LVTTL
output frequency range of 15.625MHz to 500MHz. The
device powers up at a default output frequency of
200MHz with a 16.6667MHz crystal interface, and the
frequency can then be changed using the serial programm-
ing interface to change the M feedback divider and N
output divider. Frequency steps as small as 125kHz can
be achieved using a 16.6667MHz crystal and the output
divider set for ÷16.The low jitter and frequency range of the
ICS8427-02 make it an ideal clock generator for most
clock tree applications.
• Output frequency range: 15.625MHz to 500MHz
• VCO range: 250MHz to 500MHz
• Serial interface for programming feedback and output dividers
• Supports SSC, -0.5% downspread.Can be enabled through
use of the serial programming interface.
• Output skew: 100ps (maximum)
• Cycle-to-cycle jitter: 50ps (maximum)
• 2.5V core/1.8V output supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
VCO_SEL
XTAL_SEL
PIN ASSIGNMENT
TEST_CLK
0
XTAL_IN
1
OSC
32 31 30 29 28 27 26 25
XTAL_OUT
÷ 16
VDDO
FOUT2
nFOUT2
VDDO
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL_OUT
TEST_CLK
XTAL_SEL
VDDA
PLL
÷ 1,
PHASE DETECTOR
ICS8427-02
FOUT3
nFOUT3
OE
÷ 2,
S_LOAD
S_DATA
S_CLOCK
MR
÷ 4,
0
÷ 8,
VCO
FOUT0
nFOUT0
MR
÷ 16
÷ M
1
GND
FOUT1
÷ 2
nFOUT1
9
10 11 12 13 14 15 16
FOUT2
nFOUT2
FOUT3
nFOUT3
FOUT4
nFOUT4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
FOUT5
nFOUT5
Y Package
TopView
OE
S_LOAD
S_DATA
32-LeadVFQFN
CONFIGURATION
INTERFACE
LOGIC
5mm x 5mm x 0.75mm package body
TEST
S_CLOCK
K Package
TopView
8427DY-02
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REV.A FEBRUARY 17, 2006
1
ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op-
The M value and the required values of M0 through M8 are shown
eration using a 16.6667MHz crystal. Valid PLL loop divider
values for different crystal or input frequencies are defined in inTable 3B, ProgrammableVCO Frequency FunctionTable.Valid
the Input Frequency Characteristics, Table 6 NOTE 1.
M values for which the PLL will achieve lock for a 16.6667MHz
reference are defined as 120 ≤ M ≤ 240. The frequency out is
fVCO fxtal 2M
The ICS8427-02 features a fully integrated PLL and therefore defined as follows:
requires no external components for setting the loop bandwidth.
fout
x
=
=
N
16
N
A parallel-resonant, fundamental crystal is used as the input to
the on-chip oscillator.The output of the oscillator is divided by Serial operation occurs when S_LOAD is LOW. The shift
16 prior to the phase detector.With a 16.6667MHz crystal, this register is loaded by sampling the S_DATA bits with the rising
edge of S_CLOCK. The contents of the shift register are
PLL operates over a range of 250MHz to 500MHz.The output of loaded into the M divider and N output divider when S_LOAD
provides a 1.0417MHz reference frequency. The VCO of the
the M divider is also applied to the phase detector.
transitions from LOW-to-HIGH. The M divide and N output
divide values are latched on the HIGH-to-LOW transition of
The phase detector and the M divider force the VCO output fre- S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input
quency to be 2M times the reference frequency by adjusting is passed directly to the M divider and N outputdivider on each
rising edge of S_CLOCK. The serial mode can be used to
theVCO control voltage.Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the program the M and N bits and test bits T1 and T0.The internal
VCO is scaled by a divider prior to being sent to each of the LVPECL registers T0 and T1 determine the state of the TEST output
as follows:
output buffers.The divider provides a 50% output duty cycle.
T1 T0
TEST Output
The ICS8427-02 powers up by default to 200MHz output fre-
quency, using a 16.6667MHz crystal (M = 192, N = 2). The
output frequency can be changed after power-up by using the
serial interface to program the M feedback divider and the N
output divider.
0
0
1
1
0
LOW
1 (Power-up
Default)
0
S_Data, Shift Register Input
Output of M divider
CMOS Fout
1
The relationship between the VCO frequency, the crystal fre-
quency and the M divider is defined as follows:
fxtal
x 2M
fVCO =
16
S_CLOCK
T1
T0
N2
N1
N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 SSC
S_DATA
S_LOAD
t
t
H
S
t
S
Time
FIGURE 1. SERIAL LOAD OPERATIONS
NOTE:Default Output Frequency, using a 16.6667MHz crystal
on power-up = 200MHz (M = 192, N = 2) SSC off
8427DY-02
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REV.A FEBRUARY 17, 2006
2
ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
M AND N DIVIDERS, SSC AND TEST MODE CONTROL BITS
Test Mode
Control Register
SSC Control
Register
N Divider
M Divider
➤
➤
➤
➤ ➤
➤
➤
➤
T1 T0 N2 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 SSC
➤
Data transfer from shift register
to M and N dividers and SSC and
Test Control Bits on a low-to-high
transition of S_LOAD.
S_DATA
T1 T0 N2 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 SSC
➤
Shift Register
TEST Output
T1:T0 = 01
ICS8427-02 SHIFT REGISTER OPERATION – READ BACK CAPABILITY
1. Device powers up by default in Test Mode 01.
The Test Output in this case is wired to the shift register.
2. Shift in serial data stream and latch into M, N, T1, T0 and SSC Control Bits.
Shift in T1:T0=00, so that the TEST Output will be turned off after the bits are shifted in and latched.
TEST Output
T1 T0 N2 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 SSC
S_CLOCK
T1 T0 N2 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 SSC
S_DATA
S_LOAD
t
t
S
H
t
Time
S
Data transferred to M, N dividers, TEST and SSC Control Bits.
Changes to M, N, SSC and TEST mode bits take affect at this time.
Data latched into M, N Dividers, TEST and SSC control bits.
8427DY-02
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REV.A FEBRUARY 17, 2006
3
ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 4, 13, 30
VDDO
Power
Output supply pins.
FOUT2,
nFOUT2
FOUT3,
nFOUT3
2, 3
5, 6
Output
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Output
Input
Active High output enable. When HIGH, the outputs are enabled.
When LOW, FOUTx = Low, nFOUTx = High.
LVCMOS/LVTTL interface levels.
7
OE
Pullup
8, 16
9
GND
TEST
VDD
FOUT4,
nFOUT4
FOUT5,
nFOUT5
Power
Output
Power
Output
Power supply ground.
Test output which is ACTIVE in the serial mode of operation.
LVCMOS/LVTTL interface levels.
10, 26
11, 12
Core supply pins.
Differential output pair. HSTL interface levels.
14, 15
17
Output
Input
Differential output pair. HSTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inverted
outputs nFOUTx to go high. When logic LOW, the internal dividers
and the outputs are enabled. LVCMOS/LVTTL interface levels.
Input clock to load serial S_DATA into the shift register.
LVCMOS/LVTTL interface levels.
MR
Pulldown
18
19
S_CLOCK
S_DATA
Input
Input
Pullup
Pullup
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
Analog supply pin.
20
21
S_LOAD
VDDA
Input
Pulldown
Power
Selects between XTAL input or test input as the PLL reference
source. Selects XTAL input when HIGH. Selects TEST_CLK
when LOW. LVCMOS/LVTTL interface levels.
22
Input
Pullup
XTAL_SEL
TEST_CLK
XTAL_OUT,
XTAL_IN
23
Input
Input
Pulldown Test clock input. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
24, 25
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
27
VCO_SEL
Input
Output
Output
Pullup
FOUT0,
nFOUT0
FOUT1,
nFOUT1
28, 29
31, 32
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
kΩ
kΩ
RPULLUP
RPULLDOWN
51
51
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REV.A FEBRUARY 17, 2006
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ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
OE
0
XTAL_SEL
Selected Source
TEST_CLK
FOUT0:FOUT5
Disabled; LOW
Disabled; LOW
Enabled
nFOUT0:nFOUT5
Disabled; HIGH
Disabled; HIGH
Enabled
0
1
0
1
0
XTAL_IN, XTAL_OUT
TEST_CLK
1
1
XTAL_IN, XTAL_OUT
Enabled
Enabled
After OE switches, the clock outputs are disabled or enabled following a rising and falling VCO edge
as shown in Figure 2.
Disabled
Enabled
nVCO
VCO
OE
nFOUT0:5
FOUT0:5
FIGURE 2. OE TIMING DIAGRAM
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REV.A FEBRUARY 17, 2006
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ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 3B. PROGRAMMABLEVCO FREQUENCY FUNCTIONT ABLENOTE 1
256
M8
0
128
M7
0
64
M6
1
32
M5
1
16
M4
1
8
M3
1
4
M2
0
2
M1
0
1
M0
0
VCO Frequency
(MHz)
M Divide
250
252.08
254.17
•
120
121
122
•
0
0
1
1
1
1
0
0
1
0
0
1
1
1
1
0
1
0
•
•
•
•
•
•
•
•
•
400
192
•
0
1
1
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
497.92
500
239
240
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
0
0
0
NOTE 1: These M divide values and the resulting frequencies correspond to an input frequency of 16.6667MHz.
TABLE 3C. SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR S_LOAD S_CLOCK S_DATA
H
X
X
X
Reset. Forces outputs differential LOW. FOUTx = Low, nFOUTx = High.
Data is latched into input registers and remains loaded until next LOW transition
or until a serial event occurs.
L
L
X
X
Serial input mode. Shift register is loaded with data on S_DATA on each rising
edge of S_CLOCK.
L
L
↑
Data
L
L
L
L
↑
↓
L
L
L
Data
Data
X
Contents of the shift register are passed to the M divider and N output divider.
M divider and N output divider values are latched.
X
↑
Serial input do not affect shift registers.
H
Data
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
TABLE 3D. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Input
N1
0
Output Frequency (MHz)
N Divider Value
N2
0
N0
0
Minimum
125
Maximum
250
2
4
0
0
1
62.5
125
0
1
0
8
31.25
15.625
250
62.5
0
1
1
16
1
31.25
500
1
0
0
1
0
1
2
125
250
1
1
0
4
62.5
125
1
1
1
8
31.25
62.5
8427DY-02
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REV.A FEBRUARY 17, 2006
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ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
DD
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
for 32 Lead LQFP
for 32 Lead VFQFN
JA
47.9°C/W (0 lfpm)
34.8°C/W (0 lfpm)
StorageTemperature, T
-65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V 5%, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol
VDD
Parameter
Core Supply
Test Conditions
Minimum
2.375
2.375
1.6
Typical
2.5
Maximum
2.625
2.625
2.0
Units
V
VDDA
VDDO
IDD
Analog Voltage
2.5
V
Output Voltage
1.8
V
Power Supply Current
Analog Supply Current
Output Supply Current
175
mA
mA
mA
IDDA
15
IDD0
No Load
0
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 2.5V 5%, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol
VIH
Parameter
Test Conditions
Minimum Typical Maximum Units
Input High Voltage
Input Low Voltage
1.7
VDD + 0.3
0.7
V
V
VIL
-0.3
MR, S_LOAD, TEST_CLK
V
DD = VIN = 2.625V
DD = VIN = 2.625V
150
5
µA
µA
Input
High Current
IIH
XTAL_SEL, VCO_SEL,
S_CLOCK, S_DATA, OE
V
VDD = 2.625V,
VIN = 0V
MR, S_LOAD, TEST_CLK
-5
µA
Input
Low Current
IIL
XTAL_SEL, VCO_SEL,
S_CLOCK, S_DATA, OE
VDD = 2.625V,
VIN = 0V
-150
1.5
µA
V
Output
High Voltage
Output
Low Voltage
VOH
VOL
TEST; NOTE 1
TEST; NOTE 1
0.4
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2.
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REV.A FEBRUARY 17, 2006
7
ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 4C. LVHSTL DC CHARACTERISTICS, VDD = VDDA = 2.5V 5%, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
0.9
0
1.3
0.4
60
V
V
VOL
VOX
40
0.6
%
V
VSWING
1.1
NOTE 1: Outputs terminated with 50Ω to GND. See 2.5V Output Load Test Circuit figure in the
Parameter Measurement Information section.
NOTE 2: Defined with respect to output voltage swing at a given condition.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
12
40
50
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
7
1
pF
mW
TABLE 6. INPUT CHARACTERISTICS, VDD = VDDA = 2.5V 5%, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VCO select = 1
Minimum Typical Maximum Units
12
40
400
40
50
5
MHz
MHz
MHz
MHz
ns
TEST_CLK
VCO select = 0 (bypass mode)
fIN
Input Frequency
XTAL; NOTE 1
S_CLOCK
12
tr_INPUT
Input Rise Time TEST_CLK
NOTE 1: For the crystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency
range of 250MHz or 500MHz. Using the minimum frequency of 12MHz valid values of M are 167 ≤ M ≤ 256. Using the
maximum frequency of 40MHz valid values of M are 50 ≤ M ≤ 100.
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REV.A FEBRUARY 17, 2006
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ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 7. AC CHARACTERISTICS, VDD = VDDA = 2.5V 5%, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
FMAX
Output Frequency
500
50
MHz
ps
F
F
F
F
OUT = 200MHz
OUT = 267MHz
OUT = 333MHz
OUT = 400MHz
30
30
30
30
50
ps
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 3
50
ps
50
ps
FOUT = 200MHz
200
200
200
200
5
ps
F
F
F
OUT = 267MHz
OUT = 333MHz
OUT = 400MHz
ps
tjitt(T50) T50 Cycle Jitter
ps
ps
tjit(per)
tsk(o)
Period Jitter, RMS; NOTE 1
2.5
65
ps
Output Skew; NOTE 2, 3
100
33.33
33.33
33.33
33.33
0.6
ps
F
OUT = 200MHz
30
30
30
30
kHz
kHz
kHz
kHz
%
FOUT = 267MHz
FOUT = 333MHz
FOUT = 400MHz
FM
SSC Modulation Frequency; NOTE 4, 5
F
OUT = 200MHz
0.3
0.4
0.3
0.3
-10
-12
-11
-12
-40
-40
-45
-50
FOUT = 267MHz
FOUT = 333MHz
FOUT = 400MHz
0.6
%
FMF
SSC Modulation Factor; NOTE 4, 5
Spectral Reduction; NOTE 4, 5
0.6
%
0.6
%
F
OUT = 200MHz
-7
-7
-7
-7
dB
dB
dB
dB
dB
dB
dB
dB
ps
FOUT = 267MHz
FOUT = 333MHz
FOUT = 400MHz
SSCred
F
OUT = 200MHz
FOUT = 267MHz
FOUT = 333MHz
FOUT = 400MHz
20% to 80%
Refspur
Reference Spur
tR / tF
tS
Output Rise/Fall Time
333
5
667
S_DATA to S_CLOCK
Setup Time
ns
S_CLOCK to S_LOAD
5
ns
S_DATA to S_CLOCK
Hold Time
5
ns
tH
S_CLOCK to S_LOAD
5
ns
N = 1
N = 2
40
45
60
55
1
%
odc
Output Duty Cycle
PLL Lock Time
%
tLOCK
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Spread Spectrum clocking enabled.
NOTE 5: Using a 16.6667MHz quartz crystal.
8427DY-02
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REV.A FEBRUARY 17, 2006
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ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2.5V 5%
VDDA = 2.5V 5%
1.8V 0.2V
nFOUTx
FOUTx
SCOPE
VDD
Qx
VDDO
nFOUTy
LVHSTL
FOUTy
GND
nQx
tsk(o)
0V
2.5V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
nFOUT0:5
FOUT0:5
nFOUT0:5
FOUT0:5
➤
➤
Period n + 50
Period n
+ 50 + 50
Period n
tcycle n
tcycle n+1
➤
➤
tjit (50) = Period n – Period n +50
Minimum 16,667 consective cycles
334 measurements
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
T50 CYCLE-TO-CYCLE JITTER
CYCLE-TO-CYCLE JITTER
VOH
VREF
Reference Spur
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
Frequency
SPUR REDUCTION
PERIOD JITTER
8427DY-02
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REV.A FEBRUARY 17, 2006
10
ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
nFOUT0:5
VOX
VOH
60%
nFOUT0:5
FOUT0:5
50%
40%
VOL
tPW
tPERIOD
FOUT0:5
tPW
odc =
x 100%
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT CROSSOVER VOLTAGE
80%
tF
80%
VSWING
Clock
20%
20%
Outputs
tR
OUTPUT RISE/FALL TIME
8427DY-02
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REV.A FEBRUARY 17, 2006
11
ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVHSTL OUTPUT
For applications not requiring the use of the crystal oscillator All unused LVHSTL outputs can be left floating.We recommend
input, both XTAL_IN and XTAL_OUT can be left floating. that there is no trace attached. Both sides of the differential
Though not required, but for additional protection, a 1kΩ output pair should either be left floating or terminated.
resistor can be tied from XTAL_IN to ground.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the TEST_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
CRYSTAL INPUT INTERFACE
parallel resonant crystal and were chosen to minimize the
ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
The ICS8427-02 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 3 below were determined using a 16.66MHz, 18pF
XTAL_OUT
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
C2
22p
Figure 3. CRYSTAL INPUt INTERFACE
8427DY-02
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REV.A FEBRUARY 17, 2006
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ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
POWER SUPPLY FILTERINGT ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8427-02 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 4 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin.
2.5V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 4. POWER SUPPLY FILTERING
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation tech- The ICS8427-02 triangle modulation frequency deviation will
nique for EMI reduction.When spread-spectrum is enabled, a not exceed 0.6% down-spread from the nominal clock fre-
32.55kHz triangle waveform is used with 0.5% down-spread quency (+0.0%/-0.5%). An example of the amount of down
(+0.0% / -0.5%) from the nominal 200MHz clock frequency. spread relative to the nominal clock frequency can be seen in
An example of a triangle frequency modulation profile is shown the frequency domain, as shown in Figure 5B. The ratio of this
in Figure 5A below.The ramp profile can be expressed as:
width to the fundamental frequency is typically 0.4%, and will
not exceed 0.6%. The resulting spectral reduction will be
greater than 7dB, as shown in Figure 5B. It is important to
note the ICS8427-02 7dB minimum spectral reduction is the
component-specific EMI reduction, and will not necessarily
be the same as the system EMI reduction.
• Fnom = Nominal Clock Frequency in Spread OFF mode
(200MHz with 16.6667MHz IN)
• Fm = Nominal Modulation Frequency
= Reference Frequency
16 x 32
• δ = Modulation Factor (0.5% down spread)
1
(1 - δ) fnom + 2 fm x δ x fnom x t when 0 < t <
,
2 fm
1
1
fm
(1 - δ) fnom - 2 fm x δ x fnom x t when
< t <
2 fm
Δ − 10 dBm
Fnom
B
A
➤
(1 - δ) Fnom
δ = 0.3%
➤
➤
0.5/fm
1/fm
FIGURE 5A. TRIANGLE FREQUENCY MODULATION
FIGURE 5B. 200MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN
(A) SPREAD-SPECTRUM OFF
(B) SPREAD-SPECTRUM ON
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ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
LAYOUT GUIDELINE
Figure 6 shows an application schematic example of the
ICS8427-02. In this example, a 16.6667MHz, 18 pF parallel
resonant crystal is used. The C1=22pF and C2=22pF are
approximate values for frequency accuracy. The C1 and C2
may be slightly adjusted for optimizing frequency accuracy.
C1
X1
C2
VDDO = 1.8V
VDD = 2.5V
22p
22p
16.6667MHz, 18pF
C10
0.1u
C8
0.1u
U1
VDD = 2.5V
VDDO = 1.8V
1
24
R1
10
VDDO
FOUT2
nFOUT2
VDDO
FOUT3
nFOUT3
OE
XTAL2
TEST CLK
TEST CLK
XTAL_SEL
2
3
4
5
6
7
8
23
22
21
20
19
18
17
XTAL_SEL
VDDA
S_LOAD
S_DATA
S_CLOCK
MR
S_LOAD
S_DATA
S_CLOCK
C3
0.01u
C4
10u
C7
0.1u
C9
0.1uF
GND
ICS8427-02
VDD = 2.5V
Zo = 50
Zo = 50
C5
0.1u
VDDO = 1.8V
R2
50
R3
50
C6
0.1u
FIGURE 6. SCHEMATIC OF RECOMMENDED LAYOUT
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ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8427-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8427-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 175mA = 459.4mW
Power (outputs)MAX = 32.6mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 32.6mW = 195.6mW
Total Power_MAX (3.465V, with all outputs switching) = 459.37mW + 195.6mW = 655mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W perTable 8A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.655W * 42.1°C/W = 97.6°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8A. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 8B. θJAVS. AIR FLOW TABLE FOR A 32 LEAD VFQFN
θJA byVelocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8°C/W
8427DY-02
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ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in Figure 7.
VDDO
Q1
VOUT
RL
50Ω
FIGURE 7. LVHSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
- V
)
)
OH_MIN
L
DD_MAX
OH_MIN
/R ) * (V
OL_MAX
L
DD_MAX
OL_MAX
Pd_H = (0.9V/50Ω) * (2V - 0.9V) = 19.8mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.6mW
8427DY-02
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ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 9A. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 9B. θJAVS. AIR FLOW TABLE FOR A 32 LEAD VFQFN
θJA 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8°C/W
TRANSISTOR COUNT
The transistor count for ICS8427-02 is: 4585
8427DY-02
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REV.A FEBRUARY 17, 2006
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ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 10A. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
D
9.00 BASIC
7.00 BASIC
5.60
D1
D2
E
9.00 BASIC
7.00 BASIC
5.60
E1
E2
e
0.80 BASIC
0.60
L
0.45
0°
0.75
7°
q
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
8427DY-02
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REV.A FEBRUARY 17, 2006
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ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - K SUFFIX FOR A 32 LEAD VFQFN
TABLE 10B. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
VHHD-2
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
0.80
0
1.00
0.05
A1
A3
b
--
0.25 Ref.
0.25
0.18
0.30
8
ND
NE
D
8
5.00 BASIC
2.25
D2
E
1.25
1.25
0.30
3.25
3.25
0.50
5.00 BASIC
2.25
E2
e
0.50 BASIC
0.40
L
Reference Document: JEDEC Publication 95, MO-220
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REV.A FEBRUARY 17, 2006
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ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 11. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS8427DY-02
ICS8427DY-02T
ICS8427DY-02LF
ICS8427DY-02LFT
ICS8427DK-02
ICS8427DY-02
ICS8427DY-02
ICS8427DY02L
ICS8427DY02L
ICS8427DK-02
ICS8427DK-02
TBD
32 Lead LQFP
tray
1000 tape & reel
tray
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
32 Lead LQFP
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQFP
32 Lead VFQFN
1000 tape & reel
tray
ICS8427DK-02T
ICS8427DK-02LF
ICS8427DK-02LFT
32 Lead VFQFN
2500 tape & reel
tray
32 Lead "Lead-Free" VFQFN
32 Lead "Lead-Free" VFQFN
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8427DY-02
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REV.A FEBRUARY 17, 2006
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ICS8427-02
500MHZ, LOW JITTER
LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Rev
Table
T11
Page
10
20
Description of Change
Updated Output Load AC Test Circuit diagram.
Ordering Information Table - added lead-free marking for LQFP package.
Date
A
2/17/06
8427DY-02
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REV.A FEBRUARY 17, 2006
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