ICS8422004I [ICSI]
FEMTOCLOCKS? LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER; FEMTOCLOCKS ？ LVCMOS / CRYSTAL - TO- LVHSTL频率合成器
| 型号： | ICS8422004I |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER |
| 文件： | 总13页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8422004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™LVCMOS/CRYSTAL-TO-
LVHSTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8422004I is a 4 output LVHSTL Synthesizer • Four LVHSTL outputs (VOHmax = 1.2V)
ICS
HiPerClockS™
optimized to generate Fibre Channel reference
clock frequencies and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. Using a 26.5625MHz 18pF
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 156.25, 106.25MHz, 53.125MHz
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 156.25, 106.25MHz and
53.125MHz. The ICS8422004I uses ICS’ 3rd generation low
phase noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS8422004I is packaged in a small
24-pin TSSOP package.
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.59ps (typical)
• Power supply modes:
Core/Output
3.3V/1.8V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
FREQUENCY SELECT FUNCTION TABLE
PIN ASSIGNMENT
nQ1
Q1
1
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Inputs
Input
Frequency
(MHz)
Output
Frequency
(MHz)
2
3
4
Q2
VDDO
Q3
M Divider N Divider
M/N
Divider Value
VDDO
Q0
F_SEL1 F_SEL0
Value
24
Value
3
5
6
7
8
26.5625
26.5625
26.5625
26.5625
26.04166
23.4375
0
0
1
1
0
0
0
1
0
1
1
0
8
6
4
2
6
8
212.5
159.375
106.25
53.125
156.25
187.5
nQ3
GND
nc
nQ0
MR
nPLL_SEL
nc
24
24
24
24
24
4
6
nXTAL_SEL
9
VDDA
TEST_CLK
GND
XTAL_IN
XTAL_OUT
12
4
10
11
12
F_SEL0
VDD
F_SEL1
3
ICS8422004I
24-LeadTSSOP
4.40mm x 7.8mm x 0.92mm
BLOCK DIAGRAM
F_SEL[1:0]
Pulldown
2
package body
G Package
TopView
Pulldown
nPLL_SEL
Q0
F_SEL[1:0]
nQ0
Pulldown
TEST_CLK
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
1
0
1
0
Q1
26.5625MHz
XTAL_IN
nQ1
Phase
Detector
VCO
OSC
XTAL_OUT
Q2
Pulldown
nXTAL_SEL
nQ2
M = 24 (fixed)
Q3
nQ3
Pulldown
MR
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8422004AGI
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REV.B NOVEMBER 14, 2005
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PRELIMINARY
ICS8422004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™LVCMOS/CRYSTAL-TO-
LVHSTL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
nQ1, Q1
VDDO
Type
Output
Description
Differential output pair. LVHSTL interface levels.
Output supply pins.
3, 22
4, 5
Power
Ouput
Q0, nQ0
Differential output pair. LVHSTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
6
MR
Input
Pulldown
Selects between the PLL and TEST_CLK as input to the dividers. When
7
nPLL_SEL
Input
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
8, 18
9
nc
Unused
Power
No connect.
VDDA
Analog supply pin.
F_SEL0,
F_SEL1
10, 12
11
Input
Power
Input
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
VDD
XTAL_OUT,
XTAL_IN
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
13, 14
15, 19
16
GND
Power
Input
Power supply ground.
TEST_CLK
Pulldown LVCMOS/LVTTL clock input.
Selects between crystal or TEST_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
17
nXTAL_SEL
Input
20, 21
23, 24
nQ3, Q3
Q2, nQ2
Output
Output
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
RPULLDOWN Input Pulldown Resistor
51
kΩ
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PRELIMINARY
ICS8422004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™LVCMOS/CRYSTAL-TO-
LVHSTL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
70°C/W (0 mps)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
3.135
1.6
3.3
3.3
1.8
90
10
0
3.465
3.465
2.0
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
No Load
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.375
2.375
1.6
2.5
2.5
1.8
80
10
0
2.625
2.625
2.0
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
No Load
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ OR 2.5V 5ꢀ, VDDO = 1.8V 0.2V,
TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VDD = 3.3V
Minimum Typical Maximum Units
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
VDD = 2.5V
1.7
-0.3
-0.3
V
DD = 3.3V
Input
Low Voltage
VDD = 2.5V
0.7
TEST_CLK, MR,
VDD = VIN = 3.465V
or 2.5V
Input
High Current
IIH
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
150
µA
µA
VDD = 3.465V or 2.5V,
VIN = 0V
Input
Low Current
IIL
-150
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PRELIMINARY
ICS8422004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™LVCMOS/CRYSTAL-TO-
LVHSTL FREQUENCY SYNTHESIZER
TABLE 3D. LVHSTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
1.0
0
1.2
0.4
60
V
V
VOL
Output Low Voltage; NOTE 1
VOX
Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
40
0.6
ꢀ
V
VSWING
1.1
NOTE 1: Outputs terminated with 50Ω to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
TABLE 3E. LVHSTL DC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
1.0
1.2
V
V
VOL
Output Low Voltage; NOTE 1
0.235
0.9
VOX
Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
40
60
ꢀ
V
VSWING
NOTE 1: Outputs terminated with 50Ω to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
26.5625
Mode of Oscillation
Frequency
23.33
28.33
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
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ICS8422004I
Integrated
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FEMTOCLOCKS™LVCMOS/CRYSTAL-TO-
LVHSTL FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
Minimum Typical Maximum Units
186.67
140
226.66
170
MHz
MHz
MHz
MHz
ps
fOUT
Output Frequency
93.33
46.67
113.33
56.66
tsk(o)
Output Skew; NOTE 1, 3
TBD
0.59
0.53
0.56
0.50
0.56
0.66
410
50
212.5MHz, (637kHz - 10MHz)
187.5MHz, (637kHz - 10MHz)
159.375MHz, (637kHz - 10MHz)
156.25MHz, (1.875MHz - 20MHz)
106.25MHz, (1.875MHz - 20MHz)
53.125MHz, (637kHz - 10MHz)
20ꢀ to 80ꢀ
ps
ps
ps
RMS Phase Jitter (Random);
NOTE 2
tjit(Ø)
ps
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
ps
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
Minimum Typical Maximum Units
186.67
140
226.66
170
MHz
MHz
MHz
MHz
ps
fOUT
Output Frequency
93.33
46.67
113.33
56.66
tsk(o)
Output Skew; NOTE 1, 3
TBD
0.60
0.72
0.64
0.50
0.55
0.68
380
50
212.5MHz, (637kHz - 10MHz)
187.5MHz, (637kHz - 10MHz)
159.375MHz, (637kHz - 10MHz)
156.25MHz, (1.875MHz - 20MHz)
106.25MHz, (1.875MHz - 20MHz)
53.125MHz, (637kHz - 10MHz)
20ꢀ to 80ꢀ
ps
ps
ps
RMS Phase Jitter (Random);
NOTE 2
tjit(Ø)
ps
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
ps
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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PRELIMINARY
ICS8422004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™LVCMOS/CRYSTAL-TO-
LVHSTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 212.5MHZ
0
-10
-20
-30
-40
Fibre Channel Jitter Filter
-50
-60
212.5MHz
RMS Phase Jitter (Random)
-70
637kHz to 10MHz = 0.59ps (typical)
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
Fibre Channel Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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ICS8422004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™LVCMOS/CRYSTAL-TO-
LVHSTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2.5V 5ꢀ
1.8V 0.2V
3.3V 5ꢀ
1.8V 0.2V
SCOPE
SCOPE
VDD,
VDD,
Qx
Qx
VDDA VDDO
VDDA VDDO
LVHSTL
LVHSTL
GND
GND
nQx
nQx
0V
0V
LVHSTL 3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT
LVHSTL 2.5V/1.8V OUTPUT LOAD AC TEST CIRCUIT
nQx
Qx
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
Clock
Outputs
20ꢀ
nQy
Qy
tsk(o)
OUTPUT SKEW
OUTPUT RISE/FALL TIME
Phase Noise Plot
nQ0, nQ1
Q0, Q1
tPW
tPERIOD
Phase Noise Mask
tPW
odc =
x 100ꢀ
tPERIOD
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
8422004AGI
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PRELIMINARY
ICS8422004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™LVCMOS/CRYSTAL-TO-
LVHSTL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8422004I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V or 2.5V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
below were determined using a 26.5625MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The ICS8422004I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
ICS8422004I
Figure 2. CRYSTAL INPUt INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs;
additional resistance is not required but can be added for
additional protection. A 1kΩ resistor can be used.
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
OUTPUTS:
TEST_CLK INPUT:
LVHSTL OUTPUT
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the TEST_CLK to
ground.
All unused LVHSTL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
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ICS8422004I
Integrated
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FEMTOCLOCKS™LVCMOS/CRYSTAL-TO-
LVHSTL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8422004I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8422004I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 100mA = 346.5mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 32.8mW = 131.2mW
Total Power_MAX (3.465V, with all outputs switching) = 346.5mW + 131.2mW = 477.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.478W * 65°C/W = 99.85°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
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PRELIMINARY
ICS8422004I
Integrated
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Systems, Inc.
FEMTOCLOCKS™LVCMOS/CRYSTAL-TO-
LVHSTL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 3.
VDDO
Q1
VOUT
RL
50Ω
FIGURE 3. HSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
- V
)
)
OH_MIN
L
DD_MAX
OH_MIN
/R ) * (V
OL_MAX
L
DD_MAX
OL_MAX
Pd_H = (1V/50Ω) * (2V - 1V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
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PRELIMINARY
ICS8422004I
Integrated
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Systems, Inc.
FEMTOCLOCKS™LVCMOS/CRYSTAL-TO-
LVHSTL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS8422004I is: 2951
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Systems, Inc.
FEMTOCLOCKS™LVCMOS/CRYSTAL-TO-
LVHSTL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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Circuit
Systems, Inc.
FEMTOCLOCKS™LVCMOS/CRYSTAL-TO-
LVHSTL FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS8422004AGI
ICS8422004AGIT
ICS8422004AGILF
ICS8422004AGILFT
ICS8422004AGI
ICS8422004AGI
TBD
20 Lead TSSOP
20 Lead TSSOP
2500 tape & reel
tube
20 Lead "Lead-Free" TSSOP
20 Lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
8422004AGI
www.icst.com/products/hiperclocks.html
REV.B NOVEMBER 14, 2005
13
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