ICS663MI [ICSI]
PLL BUILDING BLOCK; PLL积木
| 型号： | ICS663MI |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | PLL BUILDING BLOCK |
| 文件： | 总7页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS663
PLL BUILDING BLOCK
Description
Features
The ICS663 is a low cost Phase-Locked Loop (PLL)
designed for clock synthesis and synchronization.
Included on the chip are the phase detector, charge
pump, Voltage Controlled Oscillator (VCO) and an
output buffer. Through the use of external reference
and VCO dividers (implemented with the ICS674-01,
for example), the user can easily configure the device
to lock to a wide variety of input frequencies.
• Packaged in 8-pin SOIC
• Output clock range 1 MHz to 100 MHz (3.3 V), 1 MHz
to 120 MHz (5 V)
• External PLL loop filter enables configuration for a
wide range of input frequencies
• Ability to accept an input clock in the kHz range
(video Hsync, for example)
• 25 mA output drive capability at TTL levels
• Lower power CMOS process
The phase detector and VCO functions of the device
can also be used independently. This enables the
configuration of other PLL circuits. For example, the
ICS663 phase detector can be used to control a VCXO
circuit such as the MK3754.
• +3.3 V 5% or +5 V 10% operating voltage
• Used along with the ICS674-01, forms a complete
PLL circuit
• Phase detector and VCO blocks can be used
For applications requiring Power Down or Output
Enable features, please refer to the ICS673-01.
independently for other PLL configurations
• Industrial temperature version available
• For better jitter performance, use the MK1575
Block Diagram
LF
LFR
VDD
Icp
UP
REFIN
Clock Input
Phase/
1
Frequency
Detector
VCO
MUX
0
2
CLK
DOWN
FBIN
4
Icp
SEL
External Feedback Divider
(such as the ICS674-01)
MDS 663 D
1
Revision 062904
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS663
PLL BUILDING BLOCK
VCO Post Divide Select Table
Pin Assignment
SEL
VCO Post
Divide
FBIN
VDD
GND
LF
1
2
3
4
8
7
6
5
REFIN
CLK
0
1
8
2
SEL
0 = connect pin directly to ground
1 = connect pin directly to VDD
LFR
8 Pin (150 mil) SOIC
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
FBIN
Input
Feedback clock input. Connect the output of the feedback divider to
this pin. Falling edge triggered.
2
3
4
VDD
GND
LF
Power VDD. Connect to +3.3 V or +5 V.
Power Connect to ground.
Input
Loop filter connection (refer to Figure 1 on Page 5).
When using the phase detector block only, this pin serves as the
charge pump output.
When using the VCO block only, this pin serves as VCO input control
voltage.
5
6
7
8
LFR
SEL
Input
Input
Loop filter return (refer to Figure 1 on Page 5).
Select pin for VCO post divide, as per above table.
CLK
Output Clock output.
Input Reference clock input. Connect the input clock to this pin. Falling edge
triggered.
REFIN
MDS 663 D
2
Revision 062904
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS663
PLL BUILDING BLOCK
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS663. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7V
-0.5V to VDD+0.5V
0 to +70°C
Ambient Operating Temperature
Industrial Temperature
Storage Temperature
-40 to +85°C
-65 to +150°C
260°C
Soldering Temperature
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+85
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
-40
+3.13
+5.5
V
DC Electrical Characteristics
VDD=3.3 V ±±5 or ±.0 V ±ꢀ05, Ambient temperature -40 to +85°C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
3.13
2
Typ.
Max.
Units
Operating Voltage
VDD
5.5
V
V
Logic Input High Voltage
V
REFIN, FBIN,
SEL
IH
Logic Input Low Voltage
V
REFIN, FBIN,
SEL
0.8
V
IL
LF Input Voltage Range
Output High Voltage
Output Low Voltage
V
0
VDD
V
V
V
I
V
I
I
I
= -25 mA
= 25 mA
= -8 mA
2.4
OH
OH
OL
OH
V
0.4
OL
Output High Voltage, CMOS
level
V
VDD-0.4
OH
Operating Supply Current
IDD
VDD = 5.0 V,
15
mA
No load, 40 MHz
Short Circuit Current
Input Capacitance
I
CLK
SEL
100
5
mA
pF
OS
C
I
MDS 663 D
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Revision 062904
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS663
PLL BUILDING BLOCK
AC Electrical Characteristics
VDD = 3.3 V ±±5, Ambient Temperature -40 to +85° C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
1
Typ. Max. Units
Output Clock Frequency
(from pin CLK)
f
SEL = 1
100
25
8
MHz
MHz
MHz
CLK
SEL = 0
0.25
Note 1
Input Clock Frequency
f
REF
(into pins REFIN or FBIN)
Output Rise Time
t
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
1.2
0.75
50
2
ns
ns
OR
Output Fall Time
t
1.5
60
OF
Output Clock Duty Cycle
Jitter, Absolute peak-to-peak
VCO Gain
t
40
%
DC
t
250
200
2.5
ps
J
K
MHz/V
µA
O
Charge Pump Current
I
cp
VDD = ±.0 V ±ꢀ05, Ambient Temperature -40 to +85° C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
1
Typ. Max. Units
Output Clock Frequency
(from pin CLK)
f
SEL = 1
120
30
8
MHz
MHz
MHz
CLK
SEL = 0
0.25
Note 1
Input Clock Frequency
f
REF
(into pins REFIN or FBIN)
Output Rise Time
t
0.8 to 2.0 V
2.0 to 0.8 V
At VDD/2
0.5
0.5
50
1
1
ns
ns
OR
Output Fall Time
t
OF
Output Clock Duty Cycle
Jitter, Absolute peak-to-peak
VCO Gain
t
45
55
%
DC
t
150
200
2.5
ps
J
K
MHz/V
µA
O
Charge Pump Current
I
cp
Note 1: Minimum input frequency is limited by loop filter design. 1 kHz is a practical minimum limit.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
150
140
120
40
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
MDS 663 D
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Revision 062904
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS663
PLL BUILDING BLOCK
External Components
Avoiding PLL Lockup
The ICS663 requires a minimum number of external
components for proper operation. A decoupling
capacitor of 0.01µF should be connected between VDD
and GND as close to the ICS663 as possible. A series
termination resistor of 33Ω may be used at the clock
output.
In some applications, the ICS663 can “lock up” at the
maximum VCO frequency. The way to avoid this
problem is to use an external divider that always
operates correctly regardless of the CLK output
frequency. The CLK output frequency may be up to 2x
the maximum Output Clock Frequency listed in the AC
Electrical Characteristics above when the device is in
an unlocked condition. Make sure that the external
divider can operate up to this frequency.
Special considerations must be made in choosing loop
components C and C :
1
2
1) The loop capacitors should be a low-leakage type to
avoid leakage-induced phase noise. For this reason,
DO NOT use any type of polarized or electrolytic
capacitors.
Explanation of Operation
The ICS663 is a PLL building block circuit that includes
an integrated VCO with a wide operating range. The
device uses external PLL loop filter components which
through proper configuration allow for low input clock
reference frequencies, such as a 15.7 kHz Hsync input.
2) Microphonics (mechanical board vibration) can also
induce output phase noise when the loop bandwidth is
less than 1 kHz. For this reason, ceramic capacitors
should have C0G or NP0 dielectric. Avoid high-K
dielectrics like Z5U and X7R. These and some other
ceramics have piezoelectric properties that convert
mechanical vibration into voltage noise that interferes
with VCXO operation.
The phase/frequency detector compares the falling
edges of the clocks inputted to FBIN and REFIN. It then
generates an error signal to the charge pump, which
produces a charge proportional to this error. The
external loop filter integrates this charge, producing a
voltage that then controls the frequency of the VCO.
This process continues until the edges of FBIN are
aligned with the edges of the REFIN clock, at which
point the output frequency will be locked to the input
frequency.
For larger loop capacitor values such as 0.1µF or 1µF,
PPS film types made by Panasonic, or metal poly types
made by Murata or Cornell Dubilier are recommended.
For questions or changes regarding loop filter
characteristics, please contact your sales area FAE, or
ICS Applications.
Figure ꢀ. Example Configuration -- Generating a 20 MHz clock from a 200 kHz reference
+3.3 or 5 V
C2
0.01µF
C1
RZ
LFR
VDD
SEL
LF
200 kHz
REFIN
ICS663
CLK
20 MHz
FBIN
GND
200 kHz
100
Digital Divider such as
ICS674-01
MDS 663 D
5
Revision 062904
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS663
PLL BUILDING BLOCK
Choosing a damping factor of 0.7 (a minimal damping
factor than can be used to ensure fast lock time),
damping factor equation becomes:
Determining the Loop Filter Values
The loop filter components consist of C , C , and R .
1
2
Z
Calculating these values is best illustrated by an
example. Using the example in Figure 1, we can
synthesize 20 MHz from a 200 kHz input.
200 ⋅ 2.5 ⋅ C1
--------------------------------
200
25, 000
-----------------
0.7 =
2
The phase locked loop may be approximately
described by the following equations:
and C = 1.25 nF (1.2 nF is the nearest standard
value).
1
(RZ ⋅ KO ⋅ ICP)
Bandwidth = ------------------------------------
2π ⋅ N
The capacitor C is used to damp transients from the
charge pump and should be approximately 1/20th the
2
size of C , i.e.,
1
RZ
------
2
KO ⋅ ICP ⋅ C1
------------------------------
N
C2 ≅ C1 ⁄ 20
Damping factor, ζ=
Therefore, C = 60 pF (56 pF nearest standard value).
2
where:
To summarize, the loop filter components are:
K = VCO gain (MHz/Volt)
O
C = 1.2 nf
1
I
= Charge pump current (µA)
cp
C = 56 pf
2
N = Total feedback divide from VCO,
including the internal VCO post divider
C = Loop filter capacitor (Farads)
R = 25 kΩ
z
1
R = Loop filter resistor (Ohms)
Z
As a general rule, the bandwidth should be at least 20
times less than the reference frequency, i.e.,
BW ≤ (REFIN) ⁄ 20
In this example, using the above equation, bandwidth
should be less than or equal to 10 kHz. By setting the
bandwith to 10kHz and using the first equation, R can
Z
be determined since all other variables are known. In
the example of Figure 1, N = 200, comprising the divide
by 2 on the chip (VCO post divider) and the external
divide by 100. Therefore, the bandwidth equation
becomes:
RZ ⋅ 200 ⋅ 2.5
10,000 = -------------------------------
2π ⋅ 200
and R = 25 kΩ
Z
MDS 663 D
6
Revision 062904
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS663
PLL BUILDING BLOCK
Package Outline and Package Dimensions (8-pin SOIC, ꢀ±0 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
8
Millimeters
Inches
Min
Symbol
Min
Max
1.75
0.25
0.51
0.25
5.00
4.00
Max
.0688
.0098
.020
A
A1
B
C
D
E
e
1.35
0.10
0.33
0.19
4.80
3.80
.0532
.0040
.013
E
H
INDEX
AREA
.0075
.1890
.1497
.0098
.1968
.1574
1.27 BASIC
0.050 BASIC
1
2
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
.2284
.010
.016
0°
.2440
.020
.050
8°
D
L
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.ꢀ0 (.004)
C
Ordering Information
Part / Order Number
ICS663M
Marking
ICS663M
ICS663M
ICS663MI
ICS663MI
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
ICS663MT
ICS663MI
ICS663MIT
Tape and Reel
Tubes
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 663 D
7
Revision 062904
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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