ICS281 [ICSI]
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer; 三重锁相环场PROG 。扩频时钟合成器
| 型号： | ICS281 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Triple PLL Field Prog. Spread Spectrum Clock Synthesizer |
| 文件： | 总8页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
Description
Features
• Packaged as 16-pin TSSOP
The ICS281 field programmable spread spectrum
clock synthesizer generates up to three high-quality,
high-frequency clock outputs including multiple
reference clocks from a low-frequency crystal input. It
is designed to replace crystals, crystal oscillators and
stand alone spread spectrum devices in most
electronic systems.
• Eight addressable registers
• Replaces multiple crystals and oscillators
• Output frequencies up to 200 MHz at 3.3 V
• Configurable Spread Spectrum Modulation
• Input crystal frequency of 5 to 27 MHz
• Input clock frequency of 3 to 166 MHz
• Up to three reference outputs
TM
Using ICS’ VersaClock software to configure PLLs
and outputs, the ICS281 contains a One-Time
Programmable (OTP) ROM for field programmability.
Programming features include input/output
frequencies, spread spectrum amount and eight
selectable configuration registers.
• Operating voltages of 3.3 V
• VDDO output control from 1.8 V to 3.3 V
• Controllable output drive levels
• Advanced, low-power CMOS process
• Available in Pb (lead) free packaging
Using Phase-Locked Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace multiple
crystals and oscillators, saving board space and cost.
The ICS281 is also available in factory programmed
custom versions for high-volume applications.
Block Diagram
3
VDDO
VDD
PLL1 with
Spread
Spectrum
3
S2:S0
OTP
ROM
CLK1
CLK2
CLK3
with PLL
Values
Divide
Logic
and
Output
Enable
Control
PLL2
PLL3
Crystal or
clock input
X1/ICLK
Crystal
Oscillator
X2
3
GND
External capacitors
are required with a crystal input.
PDTS
MDS 281 C
1
Revision 062205
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
Pin Assignment
GND
S0
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
PDTS
GND
CLK3
CLK2
VDD
X2
S1
VDD
VDDO
CLK1
GND
X1/ICLK
16 pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Pin Description
Type
Power
Input
1
2
GND
S0
Connect to ground.
Select pin 0. Internal pull-up resistor.
Select pin 1. Internal pull-up resistor.
Connect to +3.3 V.
3
S1
Input
4
VDD
VDDO
CLK1
GND
X1
Power
Power
5
Power supply for outputs.
6
Output Output clock 1. Weak internal pull-down when tri-state.
7
Power
XI
Connect to ground.
8
Crystal input. Connect this pin to a crystal or external input clock.
Crystal Output. Connect this pin to a crystal. Float for clock input.
Connect to +3.3 V.
9
X2
XO
10
11
12
13
VDD
CLK2
CLK3
GND
Power
Output Output clock 2. Weak internal pull-down when tri-state.
Output Output clock 3. Weak internal pull-down when tri-state.
Power
Connect to ground.
Power-down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resistor.
14
PDTS
Input
Connect to +3.3 V.
15
16
VDD
S2
Power
Input
Select pin 2. Internal pull-up resistor.
MDS 281 C
2
Revision 062205
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
set within the range of M = 1 to 1024 and N = 1 to
32,895.
External Components
The ICS281 requires a minimum number of external
components for proper operation.
The ICS281 also provides separate output divide
values, from 2 through 63, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
Each output frequency can be represented as:
M
N
----
OutputFreq = REFFreq ⋅
Output Drive Control
The ICS281 has two output drive settings. For
VDDO=VDD, low drive should be selected when
outputs are less than 100 MHz. High drive should be
selected when outputs are greater than 100 MHz.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS281 must be isolated from system power supply
noise to perform optimally.
For VDDO<2.8 V, high drive should be selected for all
output frequencies.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. For
optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias on the decoupling circuit.
(Consult the AC Electrical Characteristics for output
rise and fall times for each drive option.)
ICS VersaClock Software
Crystal Load Capacitors
ICS applies years of PLL optimization experience into a
user friendly software that accepts the user’s target
reference clock and output frequencies and generates
the lowest jitter, lowest power configuration, with only a
press of a button. The user does not need to have prior
PLL experience or determine the optimal VCO
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
frequency to support multiple output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and
provides an easy to understand, bar code rating for the
target output frequencies. The user may evaluate
output accuracy, performance trade-off scenarios in
seconds.
The value (in pF) of these crystal caps should equal
(C -6 pF)*2. In this equation, C = crystal load
L
L
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
Spread Spectrum Modulation
The ICS281 utilizes frequency modulation (FM) to
distribute energy over a range of frequencies. By
modulating the output clock frequencies, the device
effectively lowers energy across a broader range of
frequencies; thus, lowering a system’s electromagnetic
interference (EMI). The modulation rate is the time from
transitioning from a minimum frequency to a maximum
frequency and then back to the minimum.
ICS281 Configuration Capabilities
The architecture of the ICS281 allows the user to easily
configure the device to a wide range of output
frequencies, for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
MDS 281 C
3
Revision 062205
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is
equal in the positive and negative directions. The
effective average frequency is equal to the target
frequency. In applications where the clock is driving a
component with a maximum frequency rating, down
spread should be applied. In this case, the maximum
frequency, including modulation, is the target
frequency. The effective average frequency is less than
the target frequency.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates,
if a common VCO frequency can be identified.
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to
the output clock frequency may occur at a variety of
rates. For applications requiring the driving of
“down-circuit” PLLs, Zero Delay Buffers, or those
adhering to PCI standards, the spread spectrum
modulation rate should be set to 30-33 kHz. For other
applications, a 120 kHz modulation option is available.
The ICS281 operates in both center spread and down
spread modes. For center spread, the frequency can
be modulated between 0.125% to 2.0%. For down
spread, the frequency can be modulated between
-0.25% to -4.0%.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS281. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Parameter
Condition
Min.
Typ.
Max.
7
Units
V
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
-0.5
-0.5
-65
VDD+0.5
VDD+0.5
150
V
Clock Outputs
V
Storage Temperature
Soldering Temperature
Junction Temperature
°C
°C
°C
Max 10 seconds
260
125
Recommended Operation Conditions
Parameter
Min.
0
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature (ICS281PG/PGLF)
Ambient Operating Temperature (ICS281PGI/PGILF)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
-40
+85
°C
+3.135
+3.3
+3.465
4
V
ms
MDS 281 C
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Revision 062205
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±±%, Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
VDDO Voltage
Symbol
Conditions
Min.
3.135
1.80
Typ.
Max. Units
VDD
3.465
VDD
V
V
Config. Dependent - See
VersaClock Estimates
mA
TM
Three 33.3333 MHz outs,
VDD=VDDO=3.3V;
PDTS = 1, no load, Note 1
20
mA
Operating Supply Current
Input High Voltage
IDD
PDTS = 0, no load, Note 1
S2:S0
500
µA
V
Input High Voltage
V
VDD/2+1
VDD-0.5
VDD/2+1
VDD-0.4
IH
Input Low Voltage
V
S2:S0
0.4
0.4
V
V
V
V
V
V
IL
Input High Voltage, PDTS
Input Low Voltage, PDTS
Input High Voltage
V
IH
V
IL
V
ICLK
ICLK
IH
Input Low Voltage
V
VDD/2-1
IL
Output High Voltage
(CMOS High)
V
I
= -4 mA
OH
OH
Output High Voltage
Output Low Voltage
Short Circuit Current
V
I
I
= -8 mA (Low Drive);
= -12 mA (High Drive)
2.4
VDDO-0.4
V
V
OH
OH
OH
V
I
I
= 8 mA (Low Drive);
= 12 mA (High Drive)
0.4
OL
OS
OL
OL
I
Low Drive
High Drive
40
70
mA
Nom. Output Impedance
Internal pull-up resistor
Z
20
Ω
O
R
S2:S0, PDTS
CLK outputs
190
120
kΩ
kΩ
PUS
Internal pull-down
resistor
R
PD
Input Capacitance
C
Inputs
4
pF
IN
Note 1: Example with 25 MHz crystal input, three unloaded 33.3 MHz outputs and VDD = VDDO = 3.3 V.
MDS 281 C
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Revision 062205
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±±%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Fundamental crystal
Clock input
Min. Typ. Max. Units
Input Frequency
F
5
27
MHz
MHz
MHz
MHz
ns
IN
3
166
200
150
Output Frequency
VDDO=VDD
0.314
0.314
1.8 V<VDDO<2.8 V
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
t
t
t
80% to 20%, high drive,
Note 1
1.0
2.0
2.0
OF
OF
OF
80% to 20%, low drive,
Note 1
ns
ns
80% to 20%, high drive,
1.8 V<VDDO<2.8
Note 2
Duty Cycle
Note 2
40
49-51
TBD
4
60
%
Output Frequency Synthesis Error
Configuration Dependent
ppm
ms
PLL lock-time from
power-up
10
2
Power-up Time
PDTS goes high until
stable CLK output,
Spread Spectrum Off
0.6
4
ms
ms
PDTS goes high until
stable CLK output,
Spread Spectrum On
7
One Sigma Clock Period Jitter
Maximum Absolute Jitter
Configuration Dependent
50
ps
ps
t
Deviation from Mean.
+200
ja
Configuration Dependent
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
Still air
78
70
68
37
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
θ
MDS 281 C
6
Revision 062205
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
Marking Diagrams
Marking Diagrams (Pb free)
16
9
16
9
281PGL
######
YYWW
281PG
######
YYWW
1
8
9
1
8
9
16
16
281PGIL
######
YYWW
281PGI
######
YYWW
1
8
1
8
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “I” denotes industrial temperature range (if applicable).
4. “L” denotes Pb (lead) free package.
5. Bottom marking: country of origin.
MDS 281 C
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Revision 062205
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
PRELIMINARY INFORMATION
ICS281
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
24
Millimeters
Inches
Symbol
Min
Max
1.20
0.15
1.05
0.30
0.20
5.10
Min
—
Max
.047
A
A1
A2
b
—
E1
0.05
0.80
0.19
0.09
4.90
6.40 BASIC
4.30 4.50
0.65 Basic
0.002
0.032
0.007
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
0.006
0.041
0.012
E
INDEX
AREA
C
D
E
E1
e
1 2
D
L
0.45
0.75
.018
.030
α
0°
8°
0°
8°
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
0 to +70°C
ICS281PG
Tubes
Tubes
Tubes
Tubes
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
See page 7
ICS281PGI
ICS281PGLF
ICS281PGILF
-40 to +85°C
0 to +70°C
-40 to +85°C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
TM
VersaClock
is a trademark of Integrated Circuit Systems, Inc. All rights reserved.
MDS 281 C
8
Revision 062205
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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