ICS271PG [ICSI]
Triple PLL Field Programmable VCXO Clock Synthesizer; 三重PLL现场可编程VCXO时钟合成器
| 型号： | ICS271PG |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Triple PLL Field Programmable VCXO Clock Synthesizer |
| 文件： | 总8页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
Description
Features
The ICS271 field programmable VCXO clock
synthesizer generates up to six high-quality,
high-frequency clock outputs including multiple
reference clocks from a low-frequency crystal input. It
is designed to replace crystals and crystal oscillators in
most electronic systems.
• Packaged as 20-pin TSSOP
• Eight addressable registers
• Replaces multiple crystals and oscillators
• Output frequencies up to 200 MHz at 3.3 V
• Input crystal frequency of 5 to 27 MHz
• Up to six reference outputs
TM
Using ICS’ VersaClock software to configure PLLs
and outputs, the ICS271 contains a One-Time
Programmable (OTP) ROM for field programmability.
Programming features include VCXO, eight selectable
configuration registers and up to two sets of three
low-skew outputs.
• Separate 1.8 to 3.3 V VDDO output level controls for
each bank of 3 outputs
• Up to two sets of three low-skew outputs
• Operating voltages of 3.3 V
• Controllable output drive levels
Each of the two output groups are powered by a
separate VDDO voltage. VDDO may vary from 1.8 V to
VDD.
• Advanced, low-power CMOS process
• Available in Pb (lead) free packaging
Using Phase-Locked Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace VCXOs,
multiple crystals and oscillators, saving board space
and cost.
The ICS271 is also available in factory programmed
custom versions for high-volume applications.
Block Diagram
3
VDDO1
VDD
3
OTP
PLL1
S2:S0
CLK1
CLK2
CLK3
CLK4
CLK5
ROM
with
PLL
Divide
Logic
and
Output
Enable
Control
Values
PLL2
PLL3
VIN
X1
X2
Voltage
Controlled
Crystal
CLK6
Crystal
Oscillator
GND
2
VDDO2
External capacitors
are required.
PDTS
MDS 271 A
1
Revision 040705
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
Pin Assignment
1
20
19
18
17
16
15
14
13
12
11
VIN
S0
S2
2
VDD
PDTS
GND
CLK6
3
S1
4
VDD
5
VDDO1
CLK1
6
CLK5
CLK4
7
CLK2
8
CLK3
GND
VDDO2
VDD
9
10
X1
X2
20 pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
Voltage input to VCXO. Zero to 3.3 V signal which controls the VCXO
frequency
1
VIN
Input
2
3
S0
S1
Input
Input
Select pin 0. Internal pull-up resistor.
Select pin 1. Internal pull-up resistor.
Connect to +3.3 V.
4
VDD
VDDO1
CLK1
CLK2
CLK3
GND
X1
Power
Power
5
Power supply for outputs CLK1-CLK3. Must not exceed VDD.
6
Output Output clock 1. Weak internal pull-down when tri-state.
Output Output clock 2. Weak internal pull-down when tri-state.
Output Output clock 3. Weak internal pull-down when tri-state.
7
8
9
Power
XI
Connect to ground.
10
11
12
13
14
15
16
17
Crystal input. Connect this pin to a crystal.
Crystal Output. Connect this pin to a crystal.
Connect to +3.3 V.
X2
XO
VDD
VDDO2
CLK4
CLK5
CLK6
GND
Power
Power
Power supply for outputs CLK4-CLK6. Must not exceed VDD.
Output Output clock 4. Weak internal pull-down when tri-state.
Output Output clock 5. Weak internal pull-down when tri-state.
Output Output clock 6. Weak internal pull-down when tri-state.
Power
Connect to ground.
Power-down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resistor.
18
PDTS
Input
Connect to +3.3 V.
19
20
VDD
S2
Power
Input
Select pin 2. Internal pull-up resistor.
MDS 271 A
2
Revision 040705
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
Equivalent Series Resistance
35Ω Max
External Components
The ICS271 requires a minimum number of external
components for proper operation.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the ICS271. There should be no via’s between
the crystal pins and the X1 and X2 device pins. There
should be no signal traces underneath or close to the
crystal. See application note MAN05.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS271 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD, VDDO, and the PCB ground plane.
For optimum device performance, the decoupling
capacitor should be mounted on the component side of
the PCB. Avoid the use of vias on the decoupling
circuit.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of
your final layout, a frequency counter capable of about
1 ppm resolution and accuracy, two power supplies,
and some samples of the crystals which you plan to
use in production, along with measured initial accuracy
for each crystal at the specified crystal load
capacitance, CL.
Quartz Crystal
The ICS271 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To
assure the best system performance (frequency pull
range) and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the
following section shown must be followed.
To determine the value of the crystal capacitors:
1. Connect VDD of the ICS271 to 3.3 V. Connect pin 1
of the ICS271 to the second power supply. Adjust the
voltage on pin 1 to 0V. Measure and record the
frequency of the CLK output.
2. Adjust the voltage on pin 1 to 3.3 V. Measure and
record the frequency of the same output.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The ICS271 incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the ICS271 is designed to have zero frequency
error when the total of on-chip + stray capacitance is 14
pF.
To calculate the centering error:
(f3.0V –ftarget)+(f0V–ftarget
)
Error = 106x
–errorxtal
----------------------------------------------------------------------
ftarget
Recommended Crystal Parameters:
Initial Accuracy at 25°C
Temperature Stability
Aging
Load Capacitance
Shunt Capacitance, C0
C0/C1 Ratio
20 ppm
30 ppm
20 ppm
14 pf
7 pF Max
250 Max
Where:
= nominal crystal frequency
f
target
MDS 271 A
3
Revision 040705
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
error
=actual initial accuracy (in ppm) of the crystal
Each output frequency can be represented as:
xtal
being measured
M
N
----
OutputFreq = REFFreq ⋅
If the centering error is less than 25 ppm, no
adjustment is needed. If the centering error is more
than 25 ppm negative, the PC board has excessive
stray capacitance and a new PCB layout should be
considered to reduce stray capacitance. (Alternately,
the crystal may be re-specified to a higher load
capacitance. Contact ICS for details.) If the centering
error is more than 25 ppm positive, add identical fixed
centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
External Capacitor = 2 x (centering error)/(trim
sensitivity)
Each output clock bank has an separate voltage drive
control pin (VDDO1 and VDDO2) that sets the output
clock voltage swing.
Output Drive Control
The ICS271 has two output drive settings. For
VDDO=VDD, low drive should be selected when
outputs are less than 100 MHz. High drive should be
selected when outputs are greater than 100 MHz.
For VDDO<2.8 V, high drive should be selected for all
output frequencies.
Trim sensitivity is a parameter which can be supplied by
your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (typically less than 25 ppm).
(Consult the AC Electrical Characteristics for output
rise and fall times for each drive option.)
ICS VersaClock Software
ICS applies years of PLL optimization experience into a
user friendly software that accepts the user’s target
reference clock and output frequencies and generates
the lowest jitter, lowest power configuration, with only a
press of a button. The user does not need to have prior
PLL experience or determine the optimal VCO
ICS271 Configuration Capabilities
The architecture of the ICS271 allows the user to easily
configure the device to a wide range of output
frequencies, for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
set within the range of M = 1 to 1024 and N = 1 to
32,895.
frequency to support multiple output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and
provides an easy to understand, bar code rating for the
target output frequencies. The user may evaluate
output accuracy, performance trade-off scenarios in
seconds.
The ICS271 also provides separate output divide
values, from 2 through 63, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS271. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Parameter
Condition
Min.
Typ.
Max.
7
Units
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
V
V
V
-0.5
-0.5
VDD+0.5
VDD+0.5
Clock Outputs
MDS 271 A
4
Revision 040705
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
Parameter
Condition
Min.
Typ.
Max.
150
Units
°C
Storage Temperature
Soldering Temperature
Junction Temperature
-65
Max 10 seconds
260
°C
125
°C
Recommended Operation Conditions
Parameter
Min.
0
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature (ICS271PG/PGLF)
Ambient Operating Temperature (ICS271PGI/PGILF)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
-40
+85
°C
+3.135
+3.3
+3.465
4
V
ms
Reference crystal parameters
Refer to page 3
DC Electrical Characteristics
Unless stated otherwise, VDD, VDDO = 3.3 V ±±5, Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
VDDO Voltage
Symbol
Conditions
Min.
3.135
1.80
Typ.
Max. Units
VDD
3.465
VDD
V
V
VDDO1 and VDDO2
Config. Dependent - See
VersaClock Estimates.
mA
TM
Six 33.3333 MHz outs,
VDD=VDDO=3.3 V;
PDTS = 1, no load, Note 1
25
mA
Operating Supply Current
Input High Voltage
IDD
PDTS = 0, no load
S2:S0
500
µA
V
Input High Voltage
V
VDD/2+1
VDD-0.5
VDD/2+1
IH
Input Low Voltage
V
S2:S0
0.4
0.4
V
V
V
V
V
V
IL
Input High Voltage, PDTS
Input Low Voltage, PDTS
Input High Voltage
V
IH
V
IL
V
ICLK
ICLK
IH
Input Low Voltage
V
VDD/2-1
IL
Output High Voltage
(CMOS High)
V
I
= -4 mA
VDD-0.4
2.4
OH
OH
Output High Voltage
Output Low Voltage
Short Circuit Current
V
I
I
= -8 mA (Low Drive);
= -12 mA (High Drive) VDDO-0.4
V
V
OH
OH
OH
V
I
I
= 8 mA (Low Drive);
= 12 mA (High Drive)
0.4
OL
OS
OL
OL
I
Low Drive
High Drive
40
70
20
mA
Nom. Output Impedance
Z
Ω
O
MDS 271 A
5
Revision 040705
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
Parameter
Symbol
Conditions
Min.
Typ.
190
Max. Units
Internal pull-up Resistor
R
S2:S0, PDTS
kΩ
kΩ
PUS
Internal pull-down
Resistor
R
CLK outputs
120
PD
Input Capacitance
C
Inputs
4
pF
IN
Note 1: Example with 25 MHz crystal input with six outputs of 33.3 MHz, no load, and VDD = 3.3 V.
AC Electrical Characteristics
Unless stated otherwise, VDD, VDDO = 3.3 V ±±5, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Fundamental crystal
VDDO=VDD
Min.
5
Typ.
Max. Units
Input Frequency
F
27
MHz
MHz
MHz
ppm
IN
Output Frequency
0.314
0.314
100
200
150
1.8V<VDDO<2.8
Crystal Pullability
VCXO Gain
F
0V< VIN < 3.3 V, Note 1,
Config. Dependent
P
VIN = VDD/2 + 1 V,
Note 1, Config.
Dependent
120
ppm/V
Output Rise/Fall Time
Output Rise/Fall Time
t
t
80% to 20%, high drive,
Note 2
1.0
2.0
ns
ns
OF
80% to 20%, low drive,
Note 2
OF
Output Clock Duty Cycle,
VDDO = 3.3 V
Note 3
40
49-51
4
60
10
2
%
PLL lock-time from
power-up
ms
ms
Power-up time
PDTS goes high until
stable CLK output
0.6
One Sigma Clock Period Jitter
Maximum Absolute Jitter
Configuration Dependent
50
ps
ps
t
Deviation from Mean.
+200
ja
Configuration Dependent
Pin-to-Pin Skew
Low Skew Outputs
-250
250
ps
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
Note 2: Measured with 15 pF load, VDDO = 3.3 V at VDDO/2.
Note 3: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%
MDS 271 A
6
Revision 040705
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
Still air
93
78
65
20
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
θ
Marking Diagrams
Marking Diagrams (Pb free)
20
11
20
11
271PG
######
YYWW
271PGL
######
YYWW
10
1
10
1
20
11
20
11
271PGI
######
YYWW
271PGIL
######
YYWW
10
1
10
1
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “I” denotes industrial temperature range (if applicable).
4. “L” denotes Pb (lead) free package.
5. Bottom marking: country of origin.
MDS 271 A
7
Revision 040705
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
PRELIMINARY INFORMATION
ICS271
Triple PLL Field Programmable VCXO Clock Synthesizer
Package Outline and Package Dimensions (20-pin TSSOP, 173 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
24
Millimeters
Inches
Symbol
Min
Max
1.20
0.15
1.05
0.30
0.20
6.60
Min
—
Max
.047
A
A1
A2
b
—
E1
0.05
0.80
0.19
0.09
6.40
6.40 BASIC
4.30 4.50
0.65 Basic
0.002
0.032
0.007
0.0035 0.008
0.252 0.260
0.252 BASIC
0.169 0.177
0.0256 Basic
0.006
0.041
0.012
E
INDEX
AREA
C
D
E
E1
e
1 2
D
L
0.45
0.75
.018
.030
α
0°
8°
0°
8°
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
0 to +70°C
ICS271PG
Tubes
Tubes
Tubes
Tubes
20-pin TSSOP
20-pin TSSOP
20-pin TSSOP
20-pin TSSOP
See page 7
ICS271PGI
ICS271PGLF
ICS271PGILF
-40 to +85°C
0 to +70°C
-40 to +85°C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
TM
VersaClock
is a trademark of Integrated Circuit Systems, Inc. All rights reserved.
MDS 271 A
8
Revision 040705
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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