IC62LV12816DL-70B [ICSI]
128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM; 128的K× 16位低电压和超低功耗CMOS静态RAM
| 型号： | IC62LV12816DL-70B |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM |
| 文件： | 总12页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IC62LV12816DL
IC62LV12816DLL
Document Title
128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM
Revision History
Revision No
History
Draft Date
June 7,2002
Remark
0A
Initial Draft
Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
1
IC62LV12816DL
IC62LV12816DLL
Preliminary
128K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
DESCRIPTION
The ICSI IC62LV12816DL and IC62LV12816DLL are low-
power,2,097,152 bit static RAMs organized as 131,072 words
by 16 bits. They are fabricated using ICSI's high-performance
CMOS technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-performance
and low power consumption devices.
• High-speed access times: 55, 70, 100 ns
• CMOS low power operation
--60mW (typical)* operating
--3µW (typical)* CMOS standby
• TTL compatible interface levels
• Single 2.7V-3.6V Vcc power supply
When CE1 is HIGH or when CE2 is low (deselected) or both LB
and UB are HIGH, the device assumes a standby mode at
which the power dissipation can be reduced by using CMOS
input levels.
• Fully static operation: no clock or refresh re-
quired
• Three state outputs
Easy memory expansion is provided by using Chip Enable
Output and Enable inputs, CE1, CE2 and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower Byte
(LB) access.
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP-2 and 48-pin
6x8mm TF-BGA
• CE2 pin only for 48-pin TF-BGA.
The IC62LV12816DL and IC62LV12816DLL are packaged in
the JEDEC standare 44-pin TSOP-2 and 48-pin 6*8mm TF-
BGA.
*
Typical values are measured at VCC=3.0V, TA=25°C
FUNCTIONAL BLOCK DIAGRAM
128K x 16
MEMORY ARRAY
A0-A16
DECODER
VCC
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CE1, CE2
OE
WE
CONTROL
CIRCUIT
UB
LB
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
IC62LV12816DL
IC62LV12816DLL
PIN CONFIGURATIONS
48-Pin TF-BGA (TOP View)
44-Pin TSOP-2
A4
A3
A2
A1
A0
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
2
1
2
3
4
5
6
3
4
A0
A3
A1
A4
A2
LB
I/O
OE
UB
CE2
A
B
C
D
E
F
5
CE1
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
6
CE1 I/O
8
0
7
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
8
I/O
I/O
A5
A6
I/O
I/O
9
10
11
12
1
2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
NC
NC
A14
A12
A7
I/O
I/O
I/O
I/O
Vcc
3
4
5
GND
Vcc I/O
A16
A15
A13
A10
I/O
I/O
I/O
I/O
6
14
13
NC
A8
WE
I/O
7
15
G
H
NC
A9
A11
NC
PIN DESCRIPTIONS
A0-A16
I/O0-I/O15
CE1
Address Inputs
LB
Lower-byte Control (l/O0-I/O7)
Upper-byte Control (l/O8-I/O15)
No Connection
Data Input/Output
Chip Enable1 Input
UB
NC
Vcc
GND
CE2
Chip Enable2 Input, BGA only
Output Enable Input
Power
OE
Ground
WE
Write Enable Input
TRUTH TABLE
I/O PIN
I/O8-I/O15
Mode
WE CE1 CE2 OE
LB
UB
I/O0/-I/O7
Vcc Current
Not Selected
X
X
X
H
X
L
X
L
H
X
X
X
X
X
H
X
X
H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Standby
Standby
Standby
Output Disabled H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
X
L
X
L
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
Active
Active
Active
Active
Active
Active
Active
Active
Read
H
H
H
L
H
L
L
H
L
L
L
Write
X
X
X
L
H
L
L
H
L
High-Z
DIN
L
L
DIN
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
3
IC62LV12816DL
IC62LV12816DLL
OPERATING RANGE
Range
Commercial
Ambient Temperature
VCC
2.7V- 3.6V
0°C to +70°C
Industrial
–40°C to +85°C
2.7V - 3.6V
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
VTERM
TBIAS
VCC
Terminal Voltage with Respect to GND
Temperature Under Bias
Vcc related to GND
–0.5 to Vcc + 0.5
–40 to +85
–0.3 to +4.0
–65 to +150
1.0
°C
V
TSTG
PT
Storage Temperature
°C
W
Power Dissipation
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = –1 mA
2.0
—
V
VOL
Output LOW Voltage
IOL = 2.1 mA
—
0.4
V
(1)
VIH
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
2.2
–0.2
–1
VCC + 0.2
V
V
(2)
VIL
ILI
0.4
1
GND ≤ VIN ≤ VCC
GND ≤ VOUT ≤ VCC, OUTPUTS DISABLED
µA
µA
ILO
Output Leakage
–1
1
Notes:
1. VIH(max.) = Vcc + 0.2V for pulse width less than 10ns.
2. VIL(min.) = –2.0V for pulse width less than 10 ns.
CAPACITANCE(1)
Symbol
CIN
Parameter
Input Capacitance
Conditions
VIN = 0V
Max.
6
Unit
pF
COUT
Output Capacitance
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
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Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
IC62LV12816DL
IC62LV12816DLL
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0.4V to 2.2V
5 ns
Input and Output Timing
and Reference Level
1.3V
Output Load
See Figures 1 and 2
AC TEST LOADS
1 TTL
1 TTL
OUTPUT
OUTPUT
100 pF
5 pF
Including
jig and
Including
jig and
scope
scope
Figure 1
Figure 2
IC62LV12816DL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-55
-70
-100
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
ICC
Vcc Dynamic Operating VCC = 3.0V.,
Com.
Ind.
—
—
40
45
—
—
30
35
—
—
20
25
mA
Supply Current
IOUT = 0 mA, f = fMAX
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL, f = 0
CE1 = VIH, CE2 = VIL
Com.
Ind.
—
—
0.5
1.0
—
—
0.5
1.0
—
—
0.5
1.0
mA
µA
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
Com.
Ind.
—
—
35
50
—
—
35
50
—
—
35
50
CE1
or CE2
other input = 0-VCC, f = 0
≥
VCC – 0.2V,
≤
0.2V
OR
ULB Control
VCC = Max., CE1 = VIL, CE2 = VIH
0.2V, f = 0, UB / LB VCC – 0.2V
VIN
≤
=
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
5
IC62LV12816DL
IC62LV12816DLL
IC62LV12816DLL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-55
-70
-100
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
ICC
Vcc Dynamic Operating VCC = Max
Com.
Ind.
—
—
40
45
—
—
30
35
—
—
20
25
mA
Supply Current
IOUT = 0 mA, f = fMAX
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL,
CE1 = VIH, CE2 = VIL
Com.
Ind.
—
—
0.5
1.0
—
—
0.5
1.0
—
—
0.5
1.0
mA
µA
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max., f = 0
Com.
Ind.
—
—
10
15
—
—
10
15
—
—
10
15
CE1
or CE2
other input = 0-VCC, f = 0
≥
VCC – 0.2V,
≤
0.2V
OR
ULB Control
VCC = Max., CE1 = VIL, CE2 = VIH
0.2V, f = 0, UB / LB VCC – 0.2V
VIN
≤
=
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-55
-70
-100
Symbol Parameter
Min.
55
—
10
—
—
—
5
Max.
—
Min.
70
—
10
—
—
—
5
Max.
—
Min.
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
100
—
15
—
—
—
5
tAA
Address Access Time
Output Hold Time
55
—
70
—
100
—
tOHA
tACE
tDOE
tHZOE
CE Access Time
55
30
20
—
70
35
25
—
100
50
OE Access Time
(2)
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB o High-Z Output
LB. UB to Low-Z Output
30
(2)
tLZOE
—
(2)
tHZCE
0
20
—
0
25
—
0
30
(2)
tLZCE
tBA
10
—
0
10
—
0
10
—
0
—
55
25
—
70
25
—
100
35
tHZB
tLZB
0
0
0
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels
of 0.4V to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
6
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
IC62LV12816DL
IC62LV12816DLL
AC TEST LOADS
READ CYCLE NO.1(1,2) (Address Controlled) (CE1 = OE = VIL, CE2 = VIH, UB or LB = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (OE, Controlled)
t
RC
ADDRESS
t
AA
t
OHA
OE
t
HZOE
t
DOE
LZOE
t
CE1
CE2
t
ACE
t
HZCE
t
LZCE
LB, UB
t
BA
t
HZB
t
LZB
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1, UB, or LB = VIL, CE2 = VIH
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
7
IC62LV12816DL
IC62LV12816DLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-55
-70
-100
Min.
100
80
80
0
Symbol Parameter
Min.
55
50
50
0
Max.
—
Min.
70
65
65
0
Max.
—
Max
—
—
—
—
—
—
—
—
—
40
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
tSCE
tAW
Write Cycle Time
CE1 Low and CE2 HIGH to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
—
—
—
—
tHA
—
—
tSA
0
—
0
—
0
tPWB
tPWE
tSD
LB, UB Valid to End of Write
WE Pulse Width
45
45
25
0
—
60
40
30
0
—
80
80
40
0
—
—
Data Setup to Write End
—
—
tHD
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
—
—
(3)
tHZWE
—
5
30
—
—
5
30
—
—
5
(3)
tLZWE
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE1 LOW, and UB or LB, WE LOW, and CE2 HIGH. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE1 or CE2, Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE1
t
SA
t
t
HA
CE2
WE
t
AW
t
PWE
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the WE, CE1 = VIL, CE2 = VIH and at least one of the LB
and UB inputs being in the LOW state.
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Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
IC62LV12816DL
IC62LV12816DLL
WRITE CYCLE NO. 2 (WE Controlled; OE is HIGH During Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
t
SCE
CE1
CE2
WE
t
AW
t
PWE
t
SA
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
WRITE CYCLE NO. 3 (WE Controlled; OE is LOW During Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
OE
t
SCE
CE1
CE2
WE
t
t
AW
t
PWE
t
SA
t
PBW
UB, LB
DOUT
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
t
SD
t
HD
DATAIN VALID
DIN
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
9
IC62LV12816DL
IC62LV12816DLL
WRITE CYCLE NO. 4 (UB / LB Controlled)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
t
SA
CE1
CE2
WE
t
HA
SA
t
HA
t
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Vcc for Data Retention
Test Condition
See Data Retention Waveform
Min.
1.5
Max.
3.6
Unit
V
IDR
Data Retention Current
VCC = 1.5V, CE1
≥
VCC – 0.2V(1) Com. (-L)
Com. (-LL)
—
—
20
5
µA
Ind. (-L)
—
—
25
8
Ind. (-LL)
tSDR
tRDR
Data Retention Setup Time See Data Retention Waveform
Recovery Time See Data Retention Waveform
0
—
—
ns
ns
t
RC
Notes:
1.1) CE1 ≥ VCC -0.2V, CE2 ≥ VCC -0.2V, (CE1 controlled) or
2) 0V ≤ CE2 ≤ 0.2V (CE2 controlled) or
3) LB = UB ≥ VCC -0.2V, CE2 ≥ VCC -0.2V (LB/UB controlled)
10
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
IC62LV12816DL
IC62LV12816DLL
DATA RETENTION WAVEFORM (CE1 Controlled)
t
SDR
Data Retention Mode
tRDR
V
V
CC
DR
2.7V
2.2V
CE1 ≥ VCC - 0.2V
CE1
GND
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
11
IC62LV12816DL
IC62LV12816DLL
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
55
IC62LV12816DL-55TI
TSOP-2
55
IC62LV12816DL-55T
TSOP-2
IC62LV12816DL-55BI
6*8mm TF-BGA
IC62LV12816DL-55B
6*8mm TF-BGA
70
IC62LV12816DL-70TI
IC62LV12816DL-70BI
TSOP-2
6*8mm TF-BGA
70
IC62LV12816DL-70T
IC62LV12816DL-70B
TSOP-2
6*8mm TF-BGA
100
IC62LV12816DL-100TI
IC62LV12816DL-100BI
TSOP-2
6*8mm TF-BGA
100
IC62LV12816DL-100T
IC62LV12816DL-100B 6*8mm TF-BGA
TSOP-2
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
55
IC62LV12816DLL-55TI
TSOP-2
55
IC62LV12816DLL-55T
TSOP-2
IC62LV12816DLL-55BI
6*8mm TF-BGA
IC62LV12816DLL-55B
6*8mm TF-BGA
70
IC62LV12816DLL-70TI
IC62LV12816DLL-70BI
TSOP-2
6*8mm TF-BGA
70
IC62LV12816DLL-70T
IC62LV12816DLL-70B
TSOP-2
6*8mm TF-BGA
100
IC62LV12816DLL-100TI TSOP-2
IC62LV12816DLL-100BI 6*8mm TF-BGA
100
IC62LV12816DLL-100T
IC62LV12816DLL-100B
TSOP-2
6*8mm TF-BGA
Integrated Circuit Solution Inc.
HEADQUARTER:
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TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
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Integrated Circuit Solution Inc.
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