IC62LV1008L-70B [ICSI]
1 M x 8 bit Low Voltage and Ultra Low Power CMOS Static RAM; 1一M× 8位低电压和超低功耗CMOS静态RAM
| 型号： | IC62LV1008L-70B |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 1 M x 8 bit Low Voltage and Ultra Low Power CMOS Static RAM |
| 文件： | 总11页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IC62LV1008L
IC62LV1008LL
Document Title
1 M x 8 bit Low Voltage and Ultra Low Power CMOS Static RAM
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
January 3,2002
Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
1
LPSR015-0A 1/3/2002
IC62LV1008L
IC62LV1008LL
1M x 8 LOW POWER and LOW VCC
CMOS STATIC RAM
Preliminary
FEATURES
DESCRIPTION
The ICSI IC62LV1008L and IC62LV1008LL is a low voltage,
1,048,576 words by 8 bits, CMOS SRAM. It is fabricated using
ICSI's low voltage, six transistor (6T), CMOS technology. The
device is targeted to satisfy the demands of the state-of-the-art
technologies such as cell phones and pagers.
• Access times of 55, 70, 100 ns
• CMOS Low power operation:
ICC=15mA (typical)* operation
ISB2=2µA (typical)* standby
• Low data retention voltage: 1.5V (min.)
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down with CMOS input levels. Additionally, easy
memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable ( WE)
controls both writing and reading of the memory.
• Output Enable (OE) and Two Chip Enables
(CE1, CE2) inputs for ease in applications
• TTL compatible inputs and outputs
• Fully static operation:
— No clock or refresh reguired
• Single 2.7V-3.6V power supply
• Wafer level burn in test mode
The IC62LV1008L and IC62LV1008LL are available in know
good die form and 48-pin 8*10mm TF-BGA.
• Available in the know good die form and
48-pin 8*10mm TF-BGA
*
Typical values are measured at VCC=3.0V, TA=25°C
FUNCTIONAL BLOCK DIAGRAM
1024K x 8
MEMORY ARRAY
A0-A19
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE1
CE2
OE
CONTROL
CIRCUIT
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2001
IC62LV1008L
IC62LV1008LL
PIN CONFIGURATIONS
48-Pin 8*10mm TF-BGA (TOP View)
1
2
3
4
5
6
A0
A3
A1
A4
A6
A2
CE1
NC
NC
NC
I/O
OE
NC
NC
I/O
CE2
NC
A
B
C
D
E
F
A5
I/O
4
0
GND
Vcc
I/O
5
Vcc
A17
A7
A16
A15
1
I/O
6
GND
I/O
Vcc
A14
2
I/O
3
NC
NC
A8
NC
WE
A11
I/O
7
A12
A9
NC
A13
A10
NC
G
H
A18
A19
PIN DESCRIPTIONS
A0-A19
Address Inputs
CE1
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Data Input/Output
No Connection
Power
CE2
OE
WE
I/O0-I/O7
NC
Vcc
GND
Ground
TRUTH TABLE
Mode
WE
CE1
CE2
OE
I/O Operation Vcc Current
Not Selected
X
X
H
X
X
X
X
High-Z
ISB1, ISB2
(POWER-DOWN)
L
High-Z
ISB1, ISB2
Output Disabled
Read
H
H
L
L
L
L
H
H
H
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
Write
X
OPERATING RANGE
Range
Commercial
Ambient Temperature
VCC
2.7V - 3.6V
0°C to +70°C
Industrial
–40°C to +85°C
2.7V - 3.6V
Integrated Circuit Solution Inc.
3
LPSR015-0A 1/3/2002
IC62LV1008L
IC62LV1008LL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5 to Vcc + 0.5
–0.3 to +4.0
–40 to +85
–65 to +150
1
Unit
V
VTERM
Terminal Voltage with Respect to GND
Vcc related to GND
VCC
V
TBIAS
TSTG
PT
Temperature Under Bias
Storage Temperature
°C
°C
W
Power Dissipation
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE(1)(2)
Symbol
CIN
Parameter
Input Capacitance
Conditions
VIN = 0V
Max.
6
Unit
pF
COUT
Output Capacitance
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25oC, f = 1 MHz, VCC = 3.0 V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = –1.0 mA
2.0
—
V
Output LOW Voltage
Input HIGH Voltage(1)
Input LOW Voltage(2)
Input Leakage
VCC = Min., IOL = 2.1 mA
—
0.4
V
2.2
–0.2
–1
VCC + 0.3
V
0.4
1
V
GND ≤ VIN ≤ VCC
GND ≤ VOUT ≤ VCC
µA
µA
ILO
Output Leakage
–1
1
Notes:
1. VIH(max.) = VCC +2.0V for pulse width less than 10 ns.
1. VIL(min.) = –2.0V for pulse width less than 10 ns.
4
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2001
IC62LV1008L
IC62LV1008LL
IC62LV1008L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-55
-70
-100
Symbol Parameter
Test Conditions
Min.
Max. Min.
Max. Min.
Max. Unit
ICC
Vcc Dynamic Operating VCC = 3.0V, CE1 = VIL,CE2=VIH
Com.
Ind.
—
—
30
35
—
—
25
30
—
—
20
25
mA
Supply Current
IOUT = 0 mA, f = fMAX
VCC = Max., f = 0
ISB1
TTL Standby Current
(TTL Inputs)
Com.
Ind.
—
—
0.2
0.3
—
—
0.2
0.3
—
—
0.2
0.3
mA
CE1
≥ VIH or CE2 ≤ VIL,
VIN = VIH or VIL,
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max., f = 0
Com.
Ind.
—
—
35
50
—
—
35
50
—
—
35
50
µA
CE1
or CE2
VCC – 0.2V, VIN ≤ 0.2V
≥
VCC – 0.2V
≤
0.2V,
VIN
≥
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IC62LV1008LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-55
-70
-100
Symbol Parameter
Test Conditions
Min.
Max. Min.
Max. Min.
Max. Unit
ICC
Vcc Dynamic Operating VCC = 3.0V, CE1 = VIL,CE2=VIH
Com.
Ind.
—
—
30
35
—
—
25
30
—
—
20
25
mA
Supply Current
IOUT = 0 mA, f = fMAX
VCC = Max., f = 0
ISB1
TTL Standby Current
(TTL Inputs)
Com.
Ind.
—
—
0.2
0.3
—
—
0.2
0.3
—
—
0.2
0.3
mA
CE1
≥ VIH or CE2 ≤ VIL,
VIN = VIH or VIL,
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max., f = 0
Com.
Ind.
—
—
20
25
—
—
20
25
—
—
20
25
µA
CE1
or CE2
VCC – 0.2V, VIN ≤ 0.2V
≥
VCC – 0.2V
≤
0.2V,
VIN
≥
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution Inc.
5
LPSR015-0A 1/3/2002
IC62LV1008L
IC62LV1008LL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-55
-70
-100
Symbol Parameter
Min.
55
—
10
—
—
—
5
Max.
—
Min.
70
—
10
—
—
—
5
Max.
—
Min.
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
100
—
15
—
—
—
5
tAA
Address Access Time
Output Hold Time
CE1 Access Time
CE2 Access Time
OE Access Time
55
—
70
—
100
—
tOHA
tACE1
tACE2
tDOE
55
55
30
—
70
70
35
—
100
100
50
(2)
tLZOE
OE to Low-Z Output
—
(2)
tHZOE
OE to High-Z Output
—
10
10
0
20
—
0
25
—
0
30
tLZCE1(2) CE1 to Low-Z Output
tLZCE2(2) CE2 to Low-Z Output
10
10
0
10
10
0
—
—
—
—
(2)
tHZCE
CE1 or CE2 to Low-Z Output
20
25
30
Notes:
1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output
loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0.4V to 2.2V
5 ns
Input Reference Level
Output Reference Level
1.3V
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
1 TTL
1 TTL
OUTPUT
OUTPUT
100 pF
5 pF
Including
jig and
Including
jig and
scope
scope
Figure 1
Figure 2
6
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2001
IC62LV1008L
IC62LV1008LL
AC TEST LOADS
READ CYCLE NO.1(1,2) (Address controlled, CE1 = OE = VIL , CE2 = VIH)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CE1, OE, CE2 controlled)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
LZOE
CE1
t
ACE1/tACE2
CE2
tLZCE1/
tLZCE2
t
HZCE
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
Integrated Circuit Solution Inc.
7
LPSR015-0A 1/3/2002
IC62LV1008L
IC62LV1008LL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power)
-55
-70
-100
Min.
Symbol Parameter
Min.
55
50
50
50
0
Max.
—
Min.
70
65
65
65
0
Max.
—
Max
—
—
—
—
—
—
—
—
—
40
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
100
80
80
80
0
tSCE1
tSCE2
tAW
CE1 to Write End
—
—
CE2 to Write End
—
—
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
—
—
tHA
—
—
tSA
0
—
0
—
0
(4)
tPWE
tSD
WE Pulse Width
45
25
0
—
55
30
0
—
80
40
0
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
—
—
tHD
—
—
(3)
tHZWE
—
5
30
—
—
5
30
—
—
5
(3)
tLZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output loading specified in
Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW , CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t
WC
ADDRESS
CE1
t
HA
t
SCE1
t
SCE2
CE2
t
AW
t
PWE
WE
DOUT
DIN
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DATA UNDEFINED
t
t
HD
DATA-IN VALID
8
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2001
IC62LV1008L
IC62LV1008LL
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
t
WC
ADDRESS
t
SA
tHA
t
SCE1
CE1
CE2
t
SCE2
t
AW
PWE
t
WE
DOUT
DIN
t
HZWE
tLZWE
HIGH-Z
DATA UNDEFINED
t
HD
t
SD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the HIGH-z state if OE =VIH.
Integrated Circuit Solution Inc.
9
LPSR015-0A 1/3/2002
IC62LV1008L
IC62LV1008LL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Vcc for Data Retention
Test Condition
See Data Retention Waveform
Min.
1.5
Max.
3.6
Unit
V
IDR
Data Retention Current
Vcc = 1.5V, CE1
≥
Vcc – 0.2V
Com. (-L)
Com. (-LL)
Ind. (-L)
—
—
—
—
15
6
20
9
µA
µA
µA
µA
Ind. (-LL)
tSDR
tRDR
Data Retention Setup Time See Data Retention Waveform
Recovery Time See Data Retention Waveform
0
—
—
ns
ns
10
DATA RETENTION WAVEFORM (CE1 Controlled)
t
SDR
Data Retention Mode
tRDR
V
V
CC
DR
3.0V
2.2V
CE1 ≥ VCC - 0.2V
CE1
GND
10
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2001
IC62LV1008L
IC62LV1008LL
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
55
IC62LV1008L-55BI
8*10mm TF-BGA
55
IC62LV1008L-55B
IC62LV1008L-70B
IC62LV1008L-100B
8*10mm TF-BGA
8*10mm TF-BGA
8*10mm TF-BGA
70
IC62LV1008L-70BI
8*10mm TF-BGA
70
100
IC62LV1008L-100BI 8*10mm TF-BGA
100
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
55
IC62LV1008LL-55BI 8*10mm TF-BGA
55
IC62LV1008LL-55B
8*10mm TF-BGA
IC62LV1008LL-55DI know good die
IC62LV1008LL-55D
know good die
70
IC62LV1008LL-70BI 8*10mm TF-BGA
IC62LV1008LL-70DI know good die
70
IC62LV1008LL-70B
IC62LV1008LL-70D
8*10mm TF-BGA
know good die
100
IC62LV1008LL-100BI 8*10mm TF-BGA
IC62LV1008LL-100DI know good die
100
IC62LV1008LL-100B 8*10mm TF-BGA
IC62LV1008LL-100D know good die
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
Integrated Circuit Solution Inc.
11
LPSR015-0A 1/3/2002
相关型号：
©2020 ICPDF网 联系我们和版权申明