IC62C256-45U [ICSI]
32K X 8 LOW POWER CMOS STATIC RAM; 32K ×8低功耗CMOS静态RAM
| 型号： | IC62C256-45U |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 32K X 8 LOW POWER CMOS STATIC RAM |
| 文件： | 总10页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IC62C256
32K x 8 LOW POWER CMOS STATIC RAM
ꢀEATURES
DESCRIPTION
The ICSI IC62C256 is a low power, 32,768 word by 8-bit
CMOS static RAM. It is fabricated using ICSI's high-
performance, low power CMOS technology.
Access time: 45, 70 ns
Low active power: 200 mW (typical)
Low standby power
When CS is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
250 µW (typical) at CMOS input levels.
250 µW (typical) CMOS standby
28 mW (typical) TTL standby
ꢀully static operation: no clock or refresh
required
Easy memory expansion is provided by using an active LOW
Chip Select (CS) input and an active LOW Output Enable (OE)
input. The active LOW Write Enable (WE) controls both writing
and reading of the memory.
TTL compatible inputs and outputs
Single 5V power supply
The IC62C256 is pin compatible with other 32K x 8 SRAMs in
330mil SOP or 8*13.4mm TSOP-1 package.
ꢀUNCTIONAL BLOCK DIAGRAM
32K X 8
MEMORY ARRAY
A0-A14
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CS
OE
WE
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
ALSR010-0A 05/23/2001
1
IC62C256
PIN CONꢀIGURATION
8x13.4mm TSOP-1
PIN CONꢀIGURATION
28-Pin SOP
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
OE
A11
A9
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
A10
CS
2
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A8
A6
4
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A5
5
A9
A4
6
A11
OE
A3
7
2
A2
8
A10
CS
3
A1
9
4
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
5
6
A1
A2
I/O0
I/O1
I/O2
GND
7
8
PIN DESCRIPTIONS
TRUTH TABLE
Mode
WE
CS
OE I/O Operation Vcc Current
A0-A14
CS
Address Inputs
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
Chip Select Input
Output Enable Input
Write Enable Input
Input/Output
Power
OE
Output Disabled
Read
H
H
L
L
L
L
H
L
High-Z
DOUT
DIN
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
WE
I/O0-I/O7
Vcc
Write
X
GND
Ground
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
0.5 to +7.0
55 to +125
65 to +150
0.5
Unit
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
V
°C
°C
W
Power Dissipation
IOUT
DC Output Current (LOW)
20
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2
Integrated Circuit Solution Inc.
ALSR010-0A 05/23/2001
IC62C256
OPERATING RANGE
Range
Ambient Temperature
VCC
Commercial
Industrial
0°C to +70°C
5V ± 10%
5V ± 10%
40°C to +85°C
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter
Test
Conditions
Min.MaxU. nit
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = 1.0 mA
VCC = Min., IOL = 2.1 mA
2.4
0.4
V
V
Output LOW Voltage
Input HIGH Voltage(1)
Input LOW Voltage(2)
Input Leakage
2.2
0.3
VCC + 0.5
0.8
V
V
GND ≤ VIN ≤ VCC
Com.
Ind.
2
10
2
10
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC,
Outputs Disabled
Com.
Ind.
2
10
2
10
µA
Note:
1. VIH=VCC +3.0V for pulse width less than 10ns.
2. VIL = 3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-45 ns
Min.Max.
-70 ns
Symbol
Parameter
Test Conditions
Min.Max.
Unit
ICC1
Vcc Operating
Supply Current
VCC = Max., CS = VIL
IOUT = 0 mA, f = 0
Com.
Ind.
60
70
60
mA
mA
mA
70
ICC2
ISB1
Vcc Dynamic Operating
Supply Current
VCC = Max., CS = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
70
80
65
75
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
Ind.
5
5
VIN = VIH or VIL
10
10
CS
≥ VIH, f = 0
ISB2
CMOS Standby
VCC = Max.,
Com.
Ind.
0.5
1.0
0.5
1.0
mA
Current (CMOS Inputs)
CS
VIN
VIN
≥
≥
≤
VCC 0.2V,
VCC 0.2V, or
0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.Unit
Input Capacitance
Output Capacitance
8
pꢀ
pꢀ
COUT
VOUT = 0V
10
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Circuit Solution Inc.
ALSR010-0A 05/23/2001
3
IC62C256
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-45 ns
-70 ns
Min. Max.
Symbol Parameter
Min.Max.
Unit
tRC
Read Cycle Time
45
2
70
2
70
70
35
25
25
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
Output Hold Time
CS Access Time
45
45
25
20
20
30
tOHA
tACS
tDOE
tLZOE
0
0
OE Access Time
(2)
(2)
OE to Low-Z Output
OE to High-Z Output
CS to Low-Z Output
CS to High-Z Output
CS to Power-Up
tHZOE
0
0
(2)
tLZCS
tHZCS
3
3
(2)
0
0
(3)
tPU
0
0
(3)
tPD
CS to Power-Down
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in 7igure 1.
2. Tested with the load in 7igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and ꢀall Times
Input and Output Timing
and Reference Levels
1.5V
Output Load
See ꢀigures 1 and 2
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
255 Ω
255 Ω
100 pF
5 pF
Including
jig and
scope
Including
jig and
scope
&igure
1.&igure
2.
4
Integrated Circuit Solution Inc.
ALSR010-0A 05/23/2001
IC62C256
AC WAVEꢀORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACS
CS
t
HZCS
t
LZCS
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS = VIL.
3. Address is valid prior to or coincident with CS LOW transitions.
Integrated Circuit Solution Inc.
ALSR010-0A 05/23/2001
5
IC62C256
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-45 ns
-70ns
Symbol Parameter
Min.Max.
Min. Max.
Unit
tWC
tSCS
tAW
tHA
Write Cycle Time
45
35
25
1
70
60
60
1
ns
ns
ns
ns
ns
ns
ns
ns
CS to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
tSA
0
0
(4)
tPWE
tSD
WE Pulse Width
25
20
0
55
30
0
Data Setup to Write End
Data Hold from Write End
tHD
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in 7igure 1.
2. Tested with the load in 7igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CS LOW and WE LOW. All signals must be in valid states to initiate a
Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
4. Tested with OE HIGH.
AC WAVEꢀORMS
WRITE CYCLE NO. 1(CS Controlled, OE is HIGH or LOW) (1 )
t
WC
VALID ADDRESS
SCS
ADDRESS
CS
t
SA
t
t
HA
t
AW
t
t
PWE1
PWE2
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
6
Integrated Circuit Solution Inc.
ALSR010-0A 05/23/2001
IC62C256
AC WAVEꢀORMS
WRITE CYCLE NO. 2(OE is HIGH During Write Cycle) (1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CS
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
WRITE CYCLE NO. 3(OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CS
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
Notes:
1. The internal write time is defined by the overlap of Cs LOW and WE LOW. All signals must be in valid states to initiate a
Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
2. I/O will assume the High-Z state if OE ≥ VIH.
Integrated Circuit Solution Inc.
ALSR010-0A 05/23/2001
7
IC62C256
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Test
See Data Retention Waveform
Vcc =2.0V, CE Vcc 0.2V
Condition
Min.Max.
Unit
Vcc for Data Retention
Data Retention Current
2.0
5.5
V
IDR
≥
Com.
Ind.
250
500
µA
tSDR
tRDR
Data Retention Setup Time
Recovery Time
See Data Retention Waveform
See Data Retention Waveform
0
ns
ns
5
DATA RETENTION WAVEꢀORM (CE Controlled)
t
SDR
Data Retention Mode
tRDR
V
V
CC
DR
5.0V
3.0V
CE ≥ VCC - 0.2V
CE
GND
8
Integrated Circuit Solution Inc.
ALSR010-0A 05/23/2001
IC62C256
ORDERING INꢀORMATION
ORDERING INꢀORMATION
Commerical Range: 0°C to +70°C
Industrial Range: 40°C to +85°C
Speed
(ns)
Speed
(ns)
Order
Part
No.Package
Order
Part
No.Package
45
IC62C256-45T
IC62C256-45U
8*13.4mm TSOP-1
330mil SOP
45
IC62C256-45TI 8*13.4mm TSOP-1
IC62C256-45UI 330mil SOP
70
IC62C256-70T
IC62C256-70U
8*13.4mm TSOP-1
330mil SOP
70
IC62C256-70TI 8*13.4mm TSOP-1
IC62C256-70UI 330mil SOP
Integrated Circuit Solution Inc.
ALSR010-0A 05/23/2001
9
IC62C256
Integrated Circuit Solution Inc.
HEADQUARTER:
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"ax: 886-3-5783000
BRANCH O""ICE:
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HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
"AX: 886-2-26962252
http://www.icsi.com.tw
10
Integrated Circuit Solution Inc.
ALSR010-0A 05/23/2001
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