IC61LV256-12T [ICSI]
32K x 8 Hight Speed SRAM with 3.3V; 32K ×8海特高速SRAM与3.3V
| 型号： | IC61LV256-12T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 32K x 8 Hight Speed SRAM with 3.3V |
| 文件： | 总9页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IC61LV256
Document Title
32K x 8 Hight Speed SRAM with 3.3V
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
April 19,2002
0B
Add Pb-free parts
November 28,2003
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
1
AHSR027-0B 11/28/2003
IC61LV256
32K x 8 HIGH SPEED
CMOS STATIC RAM
DESCRIPTION
FEATURES
The ICSI IC61LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using ICSI's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 8 ns maximum.
• High-speed access times:
-- 8, 10, 12, 15 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
-- 345 mW (max.) operating
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
600 µW (typical) with CMOS input levels.
-- 7 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
Easy memory expansion is provided by using an active LOW
Chip Enable (CE). The active LOW Write Enable (WE) con-
trols both writing and reading of the memory.
• Fully static operation: no clock or refresh
required
• Three-state outputs
The IC61LV256 is available in the JEDEC standard 28-pin,
300mil SOJ and the 8*13.4mm TSOP-1 package.
FUNCTIONAL BLOCK DIAGRAM
256 X 1024
MEMORY ARRAY
A0-A14
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
CONTROL
CIRCUIT
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
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Integrated Circuit Solution Inc.
AHSR027-0B 11/28/2003
IC61LV256
PIN CONFIGURATION
28-Pin SOJ
PIN CONFIGURATION
8x13.4mm TSOP-1
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
OE
A11
A9
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
A10
CE
2
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A6
4
A8
A5
5
A9
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A4
6
A11
OE
A3
7
A2
8
A10
CE
2
A1
9
3
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
4
I/O0
I/O1
I/O2
GND
5
6
A1
A2
7
8
TRUTH TABLE
PIN DESCRIPTIONS
Mode
WE CE
OE
X
I/O Operation Vcc Current
A0-A14
CE
OE
WE
I/O0-I/O7
Vcc
Address Inputs
Not Selected
X
H
High-Z
ISB1, ISB2
Chip Enable Input
Output Enable Input
Write Enable Input
Input/Output
(Power-down)
Output Disabled
Read
H
H
L
L
L
L
H
L
X
High-Z
DOUT
DIN
ICC
ICC
ICC
Write
Power
GND
Ground
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
VCC
Power Supply Voltage Relative to GND
Terminal Voltage with Respect to GND
Temperature Under Bias
–0.5 to +4.6
–0.5 to +4.6
VTERM
TBIAS
V
Com.
Ind.
–10 to +85
°C
–45 to +90
TSTG
PD
IOUT
Storage Temperature
Power Dissipation
DC Output Current
–65 to +150
°C
W
mA
1
±20
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Integrated Circuit Solution Inc.
3
AHSR027-0B 11/28/2003
IC61LV256
OPERATING RANGE
Range
Ambient Temperature
Speed
VCC
Commercial
0°C to +70°C
8, 10, 12
3.3V, +10%, –5%
15
All
3.3V ± 10%
3.3V + 10%, –5%
Industrial
–40°C to +85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
Min.
2.4
—
2.2
–0.3
–1
–5
Max.
—
0.4
VCC + 0.3
0.8
Unit
V
V
V
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
GND ≤ VIN ≤ VCC
Com.
Ind.
1
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
Com.
Ind.
–1
–5
1
5
µA
Notes:
1. VIL (min.) = –0.3V (DC); VIL (min.) = –2.0V (pulse width ≤ 2.0 ns).
VIH (max.) = VCC + 0.5V (DC); VIH (max.) = Vcc + 2.0V (pulse width ≤ 2.0 ns).
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
-10 ns
-12 ns
-15 ns
Sym. Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
ICC
Vcc Dynamic Operating
Supply Current
V
CC = Max., CE = VIL
Com.
Ind.
—
—
120
130
—
—
110
120
—
—
100
110
—
—
90
mA
I
OUT = 0 mA, f = fMAX
100
I
SB
1
TTL Standby Current
(TTL Inputs)
V
CC = Max.,
Com.
Ind.
—
—
25
30
—
—
25
30
—
—
25
30
—
—
25
30
mA
mA
V
IN = VIH or VIL
CE
≥
VIH, f = 0
ISB
2
CMOS Standby
V
CC = Max.,
Com.
Ind.
—
—
2
5
—
—
2
5
—
—
2
5
—
—
2
5
Current (CMOS Inputs)
CE
≤
≥
≤
V
CC – 0.2V,
VIN
IN
V
CC – 0.2V, or
V
0.2V, f = 0
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
6
5
Unit
pF
pF
COUT
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
4
Integrated Circuit Solution Inc.
AHSR027-0B 11/28/2003
IC61LV256
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 ns
-10 ns
-12 ns
-15 ns
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
8
—
2
—
8
10
—
2
—
10
—
10
5
12
—
2
—
12
—
12
6
15
—
2
—
15
—
15
7
tAA
Address Access Time
Output Hold Time
CE Access Time
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
—
8
—
—
0
—
—
0
—
—
0
—
—
0
OE Access Time
4
(2)
(2)
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE to Power-Up
—
4
—
5
—
5
—
6
—
3
—
3
—
3
—
3
(2)
—
4
—
5
—
6
—
7
(2)
—
0
—
0
—
0
—
0
(3)
tPU
tPD
—
8
—
10
—
12
—
15
(4)
CE to Power-Down
—
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100%
tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
1.5V
and Reference Levels
Output Load
See Figures 1 and 2
AC TEST LOADS
319 Ω
319 Ω
3.3V
3.3V
OUTPUT
OUTPUT
353 Ω
353 Ω
30 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figure 1.
Figure 2.
Integrated Circuit Solution Inc.
5
AHSR027-0B 11/28/2003
IC61LV256
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACE
CE
t
HZCE
t
LZCE
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
6
Integrated Circuit Solution Inc.
AHSR027-0B 11/28/2003
IC61LV256
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-8 ns
-10 ns
-12 ns
-15 ns
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
ns
tWC
tSCE
tAW
Write Cycle Time
8
7
7
—
—
—
10
8
—
—
—
12
8
—
—
—
15
10
10
—
—
—
CE to Write End
ns
Address Setup Time
to Write End
8
8
ns
tHA
Address Hold
0
—
0
—
0
—
0
—
ns
from Write End
tSA
tPWE
tSD
tHD
tHZWE
Address Setup Time
0
7
—
—
—
—
3.5
—
0
10
5
—
—
—
—
4
0
12
6
—
—
—
—
6
0
15
7
—
—
—
—
7
ns
ns
ns
ns
ns
ns
(4)
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
4.5
0
0
0
0
(3)
—
0
—
0
—
0
—
0
(3)
tLZWE
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold
timing are referenced to the rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW) (1 )
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
t
PWE1
PWE2
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
Integrated Circuit Solution Inc.
7
AHSR027-0B 11/28/2003
IC61LV256
WRITE CYCLE NO. 2(WE Controlled, OE is HIGH During Write Cycle) (1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
WRITE CYCLE NO. 3(WE Controlled, OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIH.
8
Integrated Circuit Solution Inc.
AHSR027-0B 11/28/2003
IC61LV256
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
8
IC61LV256-8T
IC61LV256-8J
8*13.4mm TSOP-1
300mil SOJ
8
IC61LV256-8TI
IC61LV256-8JI
8*13.4mm TSOP-1
300mil SOJ
10
12
15
IC61LV256-10T
IC61LV256-10J
IC61LV256-12T
IC61LV256-12J
IC61LV256-15T
IC61LV256-15J
8*13.4mm TSOP-1
300mil SOJ
8*13.4mm TSOP-1
300mil SOJ
8*13.4mm TSOP-1
300mil SOJ
10
12
15
IC61LV256-10TI
IC61LV256-10JI
IC61LV256-12TI
IC61LV256-12JI
IC61LV256-15TI
IC61LV256-15JI
8*13.4mm TSOP-1
300mil SOJ
8*13.4mm TSOP-1
300mil SOJ
8*13.4mm TSOP-1
300mil SOJ
ORDERING INFORMATION (Pb-free)
Commercial Range: 0°C to +70°C
ORDERING INFORMATION (Pb-free)
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
8
IC61LV256-8TG
IC61LV256-8JG
8*13.4mm TSOP-1
300mil SOJ
8
IC61LV256-8TIG
IC61LV256-8JIG
8*13.4mm TSOP-1
300mil SOJ
10
12
15
IC61LV256-10TG
IC61LV256-10JG
IC61LV256-12TG
IC61LV256-12JG
IC61LV256-15TG
IC61LV256-15JG
8*13.4mm TSOP-1
300mil SOJ
8*13.4mm TSOP-1
300mil SOJ
8*13.4mm TSOP-1
300mil SOJ
10
12
15
IC61LV256-10TIG 8*13.4mm TSOP-1
IC61LV256-10JIG 300mil SOJ
IC61LV256-12TIG 8*13.4mm TSOP-1
IC61LV256-12JIG 300mil SOJ
IC61LV256-15TIG 8*13.4mm TSOP-1
IC61LV256-15JIG 300mil SOJ
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
Integrated Circuit Solution Inc.
9
AHSR027-0B 11/28/2003
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