IC41LV82052S-60J [ICSI]
2M x 8 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE; 2M ×8 （ 16兆位）动态RAM具有快速页面模式
| 型号： | IC41LV82052S-60J |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 2M x 8 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
| 文件： | 总18页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IC41C82052S
IC41LV82052S
2M x 8 (16-MBIT) DYNAMIC
RAM
WITH ꢀAST PAGE MODE
ꢀEATURES
DESCRIPTION
ꢀAST Page Mode access cycle
TTL compatible inputs and outputs
Refresh Interval:
The ICSI 82052S Series is a 2,097,152 x 8-bit high-perfor-
mance CMOS Dynamic Random Access Memory. The &ast
Page Mode allows 2,048 random accesses within a single row
with access cycle time as short as 20 ns per 8-bit word.
Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden,
2,048 cycles/32 ms
These features make the 82052S Series ideally suited for high-
bandwidthgraphics, digitalsignalprocessing, high-performance
computing systems, and peripheral applications.
Self refresh Mode 2,048 cycles/128 ms
JEDEC standard pinout
Single power supply:
The 82052S Series is packaged in a 28-pin 300mil SOJ and a
28 pin TSOP-2
5V±10% or 3.3V ± 10%
Byte Write and Byte Read operation via
CAS
PRODUCT SERIES OVERVIEW
KEY TIMING PARAMETERS
Part No.
Refresh
2K
Voltage
5V ± 10%
3.3V ± 10%
Parameter
-50
50
13
25
20
84
-60 Unit
RAS Access Time (tRAC)
CAS Access Time (tCAC)
Column Address Access Time (tAA)
EDO Page Mode Cycle Time (tPC)
Read/Write Cycle Time (tRC)
60
15
30
25
ns
ns
ns
ns
IC41C82052S
IC41LV82052S
2K
104 ns
PIN CONꢀIGURATION
28 Pin SOJ, TSOP-2
PIN DESCRIPTIONS
VCC
I/O0
I/O1
I/O2
I/O3
WE
RAS
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
A0-A10 Address Inputs
2
I/O7
I/O6
I/O5
I/O4
CAS
OE
A9
I/O0-7
WE
Data Inputs/Outputs
Write Enable
3
4
5
OE
Output Enable
Row Address Strobe
Column Address Strobe
Power
6
RAS
CAS
Vcc
7
8
A10
A0
9
A8
10
11
12
13
14
A7
GND
NC
Ground
A1
A6
No Connection
A2
A5
A3
A4
VCC
GND
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
1
IC41C82052S
IC41LV82052S
ꢀUNCTIONAL BLOCK DIAGRAM
OE
WE
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
CAS
CONTROL
LOGIC
CAS
CAS
WE
DATA I/O BUS
RAS
CLOCK
RAS
GENERATOR
COLUMN DECODERS
SENSE AMPLIFIERS
REFRESH
COUNTER
I/O0-I/O7
MEMORY ARRAY
2,097,152 x 8
ADDRESS
BUFFERS
A0-A10
TRUTH TABLE
ꢀunction
Standby
Read
RAS
CAS
WE
X
OE
X
Address tR/tC I/O
H
L
L
L
H
L
L
L
X
High-Z
H
L
ROW/COL
ROW/COL
ROW/COL
DOUT
Write: Word (Early Write)
Read-Write
L
X
DIN
H→L
L→H
DOUT, DIN
Hidden Refresh
Read
Write(1)
L
→
H
H
→
→
L
L
L
L
H
L
L
ROW/COL
ROW/COL
DOUT
DOUT
L→
X
RAS-Only Refresh
L
H
L
X
X
X
X
ROW/NA
X
High-Z
High-Z
CBR Refresh
H→L
Note:
1. EARLY WRITE only.
2
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
ꢀunctional Description
Refresh Cycle
The IC41C82052S and IC41LV82052S are CMOS DRAMs
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 11 address bits. These
are entered 11 bits (A0-A10) at a time for the 2K refresh
device. The row address is latched by the Row Address
Strobe (RAS). The column address is latched by the
Column Address Strobe (CAS). RAS is used to latch the
first nine bits and CAS is used the latter ten bits.
To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms. Any
read, write, read-modify-write or RAS-only cycle re-
freshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 11-bit counter provides the row ad-
dresses and the external address inputs are ignored.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Self Refresh Cycle
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 128 ms.
i.e., 62.5 µs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully static,
low power data retention mode. The optional Self Refresh
feature is initiated by performing a CBR Refresh cycle and
holding RAS LOW for the specified tRAS.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOEA are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
The Self Refresh mode is terminated by driving RAS HIGH
for a minimum time of tRP. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs
last.
However, if the DRAM controller utilizes a RAS-only or
burst refresh sequence, all 2,048 rows must be refreshed
within the average internal refresh rate, prior to the re-
sumption of normal operation.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
3
IC41C82052S
IC41LV82052S
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters
Rating
Relative
0.5 to +4.6
Unit
VT
Voltage
on
Any
Pin
to
GND5V
1.0
to
+7.0
3.3V
VCC
Supply Voltage
5V
3.3V
1.0 to +7.0
0.5 to +4.6
V
IOUT
PD
Output Current
50
1
mA
W
Power Dissipation
TA
Commercial Operation Temperature
Storage Temperature
0 to +70
55 to +125
°C
°C
TSTG
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
5V
3.3V
4.5
3.0
5.0
3.3
5.5
3.6
V
VIH
VIL
TA
Input High Voltage
5V
3.3V
2.4
2.0
VCC + 1.0
VCC + 0.3
V
V
Input Low Voltage
5V
3.3V
1.0
0.3
0.8
0.8
Commercial Ambient Temperature
0
70
°C
CAPACITANCE(1,2)
Symbol
Parameter
Max.
Unit
CIN1
CIN2
CIO
Input Capacitance: A0-A10
5
7
7
p&
p&
p&
Input Capacitance: RAS, CAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O7
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz.
4
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max.
Unit
IIL
Input Leakage Current
Any input 0V < VIN < Vcc
Other inputs not under test = 0V
5
5
2.4
5
µA
IIO
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
Output is disabled (Hi-Z)
0V < VOUT < Vcc
5
µA
V
VOH
VOL
ICC1
ICC2
ICC3
IOH = 5.0 mA with VCC=5V
IOH = 2.0 mA with VCC=3.3V
0.4
IOL = 4.2 mA with VCC=5V
IOL = 2 mA with VCC=3.3V
V
RAS, CAS > VIH
5V
3.3V
2
0.5
mA
mA
mA
Standby Current: CMOS
RAS, CAS > VCC 0.2V
5V
3.3V
1
0.5
Operating Current:
Random Read/Write(2,3,4)
Average Power Supply Current
RAS, CAS,
Address Cycling, tRC = tRC (min.)
-50
-60
120
110
ICC4
ICC5
ICC6
Operating Current:
&ast Page Mode(2,3,4)
Average Power Supply Current
RAS = VIL, CAS,
tRC = tRC (min.)
-50
-60
90
80
mA
mA
mA
Refresh Current:
RAS-Only(2,3)
Average Power Supply Current
RAS Cycling, CAS > VIH
tRC = tRC (min.)
-50
-60
120
110
Refresh Current:
CBR(2,3,5)
Average Power Supply Current
RAS, CAS Cycling
tRC = tRC (min.)
-50
-60
120
110
Iccs
Self Refrsh Current
Self Refresh Mode
5V
400
300
µA
µA
3.3V
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREꢀ refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
5
IC41C82052S
IC41LV82052S
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
Min. Max.
-60
Min. Max.
Symbol
Parameter
Units
tRC
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)
RAS Pulse Width
84
50
30
8
50
13
25
10K
104
60
40
10
9
60
15
30
10K
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRAC
tCAC
tAA
tRAS
tRP
RAS Precharge Time
CAS Pulse Width(23)
CAS Precharge Time(9)
tCAS
tCP
10K
10K
9
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
CAS Hold Time (21)
38
12
0
40
14
0
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
37
45
7
10
0
0
8
10
40
Column-Address Hold Time
(referenced to RAS)
30
tRAD
tRAL
tRPC
tRSH
tRHCP
tCLZ
tCRP
tOD
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time
10
25
5
25
15
12
12
30
5
30
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
10
35
0
RAS Hold Time from CAS Precharge
CAS to Output in Low-Z(15, 24)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 24)
30
0
5
5
3
3
tOE
Output Enable Time(15, 16)
12
5
15
5
tOED
tOEHC
tOEP
tOES
tRCS
tRRH
Output Enable Data Delay (Write)
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
10
5
10
5
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
0
0
Read Command Hold Time
(referenced to RAS)(12)
0
0
tRCH
Read Command Hold Time
(referenced to CAS)(12, 17, 21)
0
0
ns
tWCH
tWCR
Write Command Hold Time(17)
8
10
50
ns
ns
Write Command Hold Time
(referenced to RAS)(17)
40
tWP
Write Command Pulse Width(17)
8
7
10
7
ns
ns
ns
ns
ns
ns
tWPZ
tRWL
tCWL
tWCS
tDHR
WE Pulse Widths to Disable Outputs
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
13
8
15
10
0
0
39
39
6
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
Min. Max.
-60
Min. Max.
Symbol
Parameter
Units
tACH
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
15
15
ns
tOEH
OE Hold Time from WE during
READ-MODI&Y-WRITE cycle(18)
8
10
ns
tDS
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
0
8
0
ns
ns
ns
ns
tDH
10
tRWC
tRWD
READ-MODI&Y-WRITE Cycle Time
108
64
133
77
RAS to WE Delay Time during
READ-MODI&Y-WRITE Cycle(14)
tCWD
tAWD
tPC
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
26
39
20
32
47
25
ns
ns
ns
EDO Page Mode READ or WRITE
Cycle Time
tRASP
tCPA
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
50
56
100K
30
60
68
100K
35
ns
ns
ns
tPRWC
EDO Page Mode READ-WRITE
Cycle Time
tCOH
tOꢀꢀ
Data Output Hold after CAS LOW
5
0
12
5
0
15
ns
ns
Output Buffer Turn-Off Delay from
CAS or RAS(13,15,19, 24)
tWHZ
tCSR
tCHR
tORD
Output Disable Delay from WE
CAS Setup Time (CBR RE&RESH)(20, 25)
CAS Hold Time (CBR RE&RESH)( 21, 25)
3
5
8
0
10
3
5
10
ns
ns
ns
ns
10
0
OE Setup Time prior to RAS during
HIDDEN RE&RESH Cycle
tREꢀ
tREꢀ
tT
Auto Refresh Period
2,048 Cycles
50
32
128
1
50
32
128
ns
ms
ms
Self Refresh Period
2,048 Cycles
1
Transition Time (Rise or &all)(2, 3)
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 p& (Vcc = 5.0V + 10%)
One TTL Load and 50 p& (Vcc = 3.3V + 10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V + 10%)
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V + 10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5.0V + 10%, 3.3V + 10%)
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
7
IC41C82052S
IC41LV82052S
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREꢀ refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pꢀ.
7. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD > tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOꢀꢀ (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIꢀY-WRITE cycle only. If tWCS > tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD > tRWD
(MIN), tAWD > tAWD (MIN) and tCWD > tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a
LATE WRITE or READ-MODIꢀY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIꢀY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOꢀꢀ occur.
20. Determined by falling edge of CAS.
21. Determined by rising edge of CAS.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIꢀY-WRITE cycles.
23. CAS must meet minimum pulse width.
24. The 3 ns minimum is a parameter guaranteed by design.
25. Enables on-chip refresh and address counters.
8
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
READ CYCLE
t
RC
t
RAS
t
RP
RAS
CAS
t
CSH
t
RSH
t
RRH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
t
AR
t
RAD
tRAL
t
t
RAH
t
CAH
t
ASC
ADDRESS
WE
Row
Column
Row
t
RCS
t
RCH
t
AA
t
RAC
(1)
OFF
t
t
CAC
CLC
t
Open
Open
Valid Data
I/O
OE
t
OE
tOD
t
OES
Don’t Care
Note:
1. tOꢀꢀ is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
9
IC41C82052S
IC41LV82052S
READ WRITE CYCLE (LATE WRITE and READ-MODI&Y-WRITE Cycles)
t
t
RWC
RAS
t
RP
RAS
CAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
t
AR
t
RAD
tRAL
t
t
RAH
tCAH
t
ASC
t
ACH
ADDRESS
WE
Row
Column
Row
t
RWD
tCWL
t
RCS
t
CWD
t
RWL
t
AWD
t
WP
t
AA
t
RAC
t
t
CAC
CLZ
t
DS
tDH
Open
Open
Valid DOUT
Valid DIN
I/O
OE
t
OD
tOEH
t
OE
Don’t Care
10
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
EARLY WRITE CYCLE (OE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
CAS
t
AR
t
RAD
t
t
t
RAL
CAH
ACH
t
t
RAH
t
ASC
ADDRESS
Row
Column
Row
t
t
CWL
RWL
t
WCR
t
WCS
tWCH
t
WP
WE
I/O
t
DHR
t
DH
t
DS
Valid Data
Don’t Care
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
11
IC41C82052S
IC41LV82052S
ꢀAST PAGE MODE READ CYCLE
tRASP
tRP
RAS
tCSH
tPRWC
tCAS
tRSH
tCAS
tCAS
tCAH
tCRP
tRCD
tAR
tCRP
tCP
tCP
CAS
tCPWD
tRAL
tCPWD
tRAD
tCAH
tCAH
tRAH
tASR
tASC
tASC
tASC
ADDRESS
Row
Column
Column
Column
tRCS
WE
OE
tAA
tAA
tCAC
tAA
tCAC
tCAC
tOE
tOE
tOE
tRAC
tCLZ
tOED
tOED
tOED
tCLZ
tCLZ
OUT
I/O
OUT
OUT
Don’t Care
12
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
ꢀAST PAGE MODE READ WRITE CYCLE (LATE WRITE and READ-MODI&Y-WRITE Cycles)
tRASP
tRP
RAS
tCSH
tPRWC
tCAS
tRSH
tCAS
tCAS
tCAH
tCRP
tRCD
tAR
tCRP
tCP
tCP
CAS
tCPWD
tRAL
tCPWD
tRAD
tCAH
tCAH
tRAH
tASR
tASC
tASC
tASC
ADDRESS
Row
Column
Column
Column
tCWL
tRWD
tCWL
tRWL
tCWL
tAWD
tCWD
tAWD
tCWD
tAWD
tCWD
tRCS
tWP
tWP
tWP
WE
tAA
tAA
tAA
tCAC
tCAC
tCAC
tOE
tOE
tOE
OE
I/O
tOEZ
tOEZ
tOED
tOEZ
tOED
tRAC
tCLZ
tOED
tDH
tDH
tDH
tDS tCLZ
tDS
tCLZ
OUT
tDS
OUT
IN
IN
IN
OUT
Don’t Care
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
13
IC41C82052S
IC41LV82052S
ꢀAST PAGE MODE EARLY WRITE CYCLE
t
RASP
t
RP
RAS
t
t
RHCP
RSH
CAS
t
CSH
t
PC
t
t
CAS
t
CAS
t
t
CRP
t
RCD
t
CRP
t
CP
t
CP
CAS
t
AR
RAL
t
RAD
t
CAH
t
CAH
tCAH
t
RAH
t
ASC
t
ASC
t
ASC
t
ASR
ADDRESS
Row
Column
Column
Column
t
t
CWL
WCH
t
CWL
WCH
CWL
WCH
t
WCS
t
WCS
t
t
WCS
t
t
t
WP
t
WP
tWP
WE
OE
t
WCR
t
DHR
t
DS
tDS
t
DS
t
DH
t
DH
tDH
Valid DIN
Valid DIN
Valid DIN
I/O
Don’t Care
14
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
AC WAVEꢀORMS
RAS-ONLY REꢀRESH CYCLE (OE, WE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
CAS
t
CRP
t
RPC
t
ASR
tRAH
ADDRESS
I/O
Row
Row
Open
Don’t Care
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
15
IC41C82052S
IC41LV82052S
CBR REꢀRESH CYCLE (Addresses; WE, OE = DON'T CARE)
t
RP
t
RAS
t
RP
tRAS
RAS
t
CHR
t
CHR
t
RPC
CP
tRPC
t
t
CSR
tCSR
CAS
I/O
Open
Don’t Care
HIDDEN REꢀRESH CYCLE (WE = HIGH; OE = LOW)
t
RAS
t
RAS
t
RP
RAS
CAS
t
CRP
t
RCD
t
RSH
tCHR
t
AR
t
RAD
t
RAL
t
ASR
t
RAH
t
CAH
t
ASC
ADDRESS
Row
Column
t
AA
t
RAC
(2)
OFF
t
t
CAC
t
CLZ
Open
Open
Valid Data
I/O
OE
t
OE
tOD
t
ORD
Don’t Care
16
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
IC41C82052S
IC41LV82052S
SELꢀ REꢀRESH CYCLE (Addresses : WE and OE = DON'T CARE)
t
RP
t
RASS
tRPS
V
IH
IL
RAS
V
t
CHD
t
RPC
CP
t
RPC
t
t
CSR
t
CP
V
IH
IL
CAS
DQ
V
VOH
OL
Open
V
TIMING PARAMETERS
-50
Min. Max.
-60
Min. Max.
Symbol
Units
tCHD
tCP
8
9
10
9
ns
ns
ns
µs
ns
ns
ns
tCSR
tRASS
tRP
5
5
50
30
84
5
50
40
104
5
tRPS
tRPC
ORDERING INꢀORMATION
Commercial Range: 0°C to 70°C
Voltage: 5V
Speed (ns) Order Part No. Refresh
Package
50
50
IC41C82052S-50J
IC41C82052S-50T
2K
2K
300mil SOJ
400mil TSOP-2
60
60
IC41C82052S-60J
IC41C82052S-60T
2K
2K
300mil SOJ
400mil TSOP-2
Voltage: 3.3V
Speed (ns) Order Part No.
Refresh
Package
50
50
IC41LV82052S-50J
2K
300mil SOJ
400mil TSOP-2
IC41LV82052S-50T 2K
IC41LV82052S-60J 2K
IC41LV82052S-60T 2K
60
60
300mil SOJ
400mil TSOP-2
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
17
IC41C82052S
IC41LV82052S
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
+ax: 886-3-5783000
BRANCH O++ICE:
7+, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
+AX: 886-2-26962252
http://www.icsi.com.tw
18
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
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