IC41C8512-50T [ICSI]
512K x 8 bit Dynamic RAM with EDO Page Mode; 512K ×8位动态RAM与EDO页面模式
| 型号： | IC41C8512-50T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 512K x 8 bit Dynamic RAM with EDO Page Mode |
| 文件： | 总21页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IC41C8512
IC41LV8512
Document Title
512K x 8 bit Dynamic RAM with EDO Page Mode
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
September 28,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
1
IC41C8512
IC41LV8512
512K x 8 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
DESCRIPTION
FEATURES
The ICSI IC41C8512 and IC41LV8512 is a 524,288 x 8-bit high-
performance CMOS Dynamic Random Access Memories. The
IC41C8512 offer an accelerated cycle access called EDO Page
Mode. EDO Page Mode allows 1024 random accesses within
a single row with access cycle time as short as 12 ns per 8-bit
word.
• Extended Data-Out (EDO) Page Mode access cycle
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval: 1024 cycles /16 ms
• Refresh Mode: RAS-Only, CAS-before-RAS (CBR),
Hidden
• Single power supply:
These features make the IC41C8512and IC41LV8512 ideally
suited for, digital signal processing, high-performance audio
systems, and peripheral applications.
5V ± 10% (IC41C8512)
3.3V ± 10% (IC41LV8512)
• Industrail Temperature Range -40oC to 85oC
The IC41C8512 is packaged in a 28-pin 400mil SOJ and 400mil
TSOP-2.
KEY TIMING PARAMETERS
Parameter
-35
35
10
18
12
60
-50
50
14
25
20
90
-60
60
Unit
ns
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. EDO Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
15
ns
30
ns
25
ns
110
ns
PIN CONFIGURATION
28 Pin SOJ, TSOP-2
PIN DESCRIPTIONS
VCC
I/O0
I/O1
I/O2
I/O3
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
I/O7
I/O6
I/O5
I/O4
CAS
OE
A0-A9
I/O0-7
WE
Address Inputs
2
Data Inputs/Outputs
Write Enable
3
4
OE
Output Enable
Row Address Strobe
Column Address Strobe
Power
5
6
RAS
CAS
Vcc
WE
RAS
A9
7
8
NC
9
A8
A0
10
11
12
13
14
A7
GND
NC
Ground
A1
A6
No Connection
A2
A5
A3
A4
VCC
GND
2
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
IC41C8512
IC41LV8512
FUNCTIONAL BLOCK DIAGRAM
OE
WE
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
CAS
CLOCK
GENERATOR
CAS
CAS
WE
DATA I/O BUS
RAS
CLOCK
RAS
GENERATOR
COLUMN DECODERS
SENSE AMPLIFIERS
REFRESH
COUNTER
I/O0-I/O7
MEMORY ARRAY
524,288 x 8
ADDRESS
BUFFERS
A0-A9
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
3
IC41C8512
IC41LV8512
TRUTH TABLE
Function
RAS
CAS
W E
X
O E Address tR/tC I/O
Standby
H
L
L
L
H
L
L
L
X
X
High-Z
Read:
H
L
ROW/COL
ROW/COL
ROW/COL
DOUT
Write: (Early Write)
Read-Write
L
X
DIN
H→L
L
→
H
DOUT, DIN
EDO Page-Mode Read
1st Cycle:
2nd Cycle:
Any Cycle:
L
L
L
H
→
L
L
H
H
H
L
L
L
ROW/COL
NA/COL
NA/NA
DOUT
DOUT
DOUT
H→
L→
H
EDO Page-Mode Write
1st Cycle:
2nd Cycle:
L
L
H
→
L
L
L
L
X
X
ROW/COL
NA/COL
DIN
DIN
H→
EDO Page-Mode
Read-Write
1st Cycle:
2nd Cycle:
L
L
H
→
L
L
H
→
L
L
L
→
H
H
ROW/COL
NA/COL
DOUT, DIN
DOUT, DIN
H→
H→
L→
Hidden Refresh
Read
Write
L
L
→
H
→
L
L
L
L
H
L
L
X
ROW/COL
ROW/COL
DOUT
DIN
→H→
RAS-Only Refresh
CBR Refresh
L
H
L
X
X
X
X
ROW/NA
X
High-Z
High-Z
H→L
4
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
IC41C8512
IC41LV8512
Functional Description
The IC41C8512 and IC41LV8512 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 10 address bits. These are entered
10 bits (A0-A9) at a time. The row address is latched by the
Row Address Strobe (RAS). The column address is latched
by the Column Address Strobe (CAS) . RAS is used to latch
the first ten bits and CAS is used to latch the latter nine bits.
Refresh Cycle
To retain data, 1024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1024 row addresses (A0 through
A9) with RAS at least once every 16 ms. Any read, write,
read-modify-write or RAS-only cycle refreshes the ad-
dressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 10-bit counter provides the row ad-
dresses and the external address inputs are ignored.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 1024 columns within
a selected row to be randomly accessed at a high data rate.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOE are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. Therefore,
in EDO page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the CAS cycle
time becomes shorter.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs first.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
5
IC41C8512
IC41LV8512
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters
Rating
Unit
VT
Voltage on Any Pin Relative to GND
5V
3.3V
–1.0 to +7.0
–0.5 to +4.6
V
VCC
Supply Voltage
5V
3.3V
–1.0 to +7.0
–0.5 to +4.6
V
IOUT
PD
Output Current
50
1
mA
W
Power Dissipation
TA
Commercial Operation Temperature
Industrial Operationg Temperature
0 to +70
–40 to +85
°C
°C
TSTG
Storage Temperature
–55 to +125
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
5V
3.3V
4.5
3.0
5.0
3.3
5.5
3.6
V
VIH
VIL
TA
Input High Voltage
Input Low Voltage
5V
3.3V
2.4
2.0
—
—
VCC + 1.0
VCC + 0.3
V
V
5V
3.3V
–1.0
–0.3
—
—
0.8
0.8
Commercial Ambient Temperature
Industrial Ambient Temperature
0
–40
—
—
70
85
°C
°C
CAPACITANCE(1,2)
Symbol
Parameter
Max.
Unit
CIN1
CIN2
CIO
Input Capacitance: A0-A9
5
7
7
pF
pF
pF
Input Capacitance: RAS, CAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O7
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz.
6
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
IC41C8512
IC41LV8512
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max.
Unit
IIL
Input Leakage Current
Any input 0V ≤ VIN ≤ Vcc
–10
10
µA
Other inputs not under test = 0V
IIO
Output Leakage Current
Output is disabled (Hi-Z)
–10
10
µA
0V ≤ VOUT ≤ Vcc
VOH
VOL
ICC1
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
IOH = –2.5 mA
IOL =+2.1mA
2.4
—
—
V
V
0.4
RAS, CAS ≥ VIH
5V
3.3V
—
—
2
0.5
mA
ICC2
ICC3
Standby Current: CMOS
RAS, CAS ≥ VCC – 0.2V
5V
3.3V
—
—
1
0.5
mA
mA
OperatingCurrent:
RAS, CAS,
Address Cycling, tRC = tRC (min.)
-35
-50
-60
—
—
—
120
110
100
RandomRead/Write(2,3,4)
Average Power Supply Current
ICC4
ICC5
ICC6
OperatingCurrent:
RAS = VIL, CAS,
-35
-50
-60
—
—
—
100
90
80
mA
mA
mA
EDO Page Mode(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
Refresh Current:
RAS Cycling, CAS ≥ VIH
tRC = tRC (min.)
-35
-50
-60
—
—
—
120
110
100
RAS-Only(2,3)
Average Power Supply Current
Refresh Current:
RAS, CAS Cycling
tRC = tRC (min.)
-35
-50
-60
—
—
—
120
110
100
CBR(2,3,5)
Average Power Supply Current
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
7
IC41C8512
IC41LV8512
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-35
Min. Max.
-50
-60
Symbol
Parameter
Min. Max.
Min. Max.
Units
tRC
Random READ or WRITE Cycle Time
60
—
—
—
—
35
10
18
90
—
—
—
—
50
14
25
110
—
—
60
15
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(6, 7)
tRAC
tCAC
tAA
Access Time from RAS
(6, 8, 15)
Access Time from CAS
—
Access Time from Column-Address(6)
RAS Pulse Width
—
tRAS
tRP
35 10K
50 10K
60 10K
40
10 10K
RAS Precharge Time
20
6
—
10K
—
30
8
—
10K
—
—
tCAS
tCP
CAS Pulse Width(26)
CAS Precharge Time(9, 25)
CAS Hold Time (21)
5
8
10
60
20
0
—
—
45
—
—
—
—
—
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
35
11
0
—
50
19
0
—
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
28
—
36
—
6
—
8
—
10
0
0
—
0
—
6
—
8
—
10
40
Column-Address Hold Time
30
—
40
—
(referenced to RAS)
tRAD
tRAL
tRPC
tRSH
tCLZ
tCRP
tOD
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time(27)
10
18
0
20
—
—
—
—
—
12
10
—
—
—
—
—
14
25
0
25
—
—
—
—
—
12
15
—
—
—
—
—
15
30
0
30
—
—
—
—
—
12
15
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
14
3
15
3
CAS to Output in Low-Z(15, 29)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 28, 29)
3
5
5
5
3
3
3
tOE
Output Enable Time(15, 16)
0
0
—
10
10
5
tOEHC
tOEP
tOES
tRCS
tRRH
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
10
10
5
10
10
5
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
0
0
0
Read Command Hold Time
0
0
0
(referenced to RAS)(12)
tRCH
Read Command Hold Time
0
—
0
—
0
—
ns
(referenced to CAS)(12, 17, 21)
tWCH
tWCR
Write Command Hold Time(17, 27)
5
—
—
8
—
—
10
50
—
—
ns
ns
Write Command Hold Time
30
40
(referenced to RAS)(17)
tWP
Write Command Pulse Width(17)
5
10
8
—
—
—
—
—
—
8
—
—
—
—
—
—
10
10
15
15
0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
tWPZ
tRWL
tCWL
tWCS
tDHR
WE Pulse Widths to Disable Outputs
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
10
14
14
0
8
0
30
40
40
8
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
IC41C8512
IC41LV8512
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
35
Min. Max.
-50
-60
Symbol
Parameter
Min. Max.
Min. Max.
Units
tACH
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
15
—
15
—
15
—
ns
tOEH
OE Hold Time from WE during
8
—
10
—
15
—
ns
READ-MODIFY-WRITE cycle(18)
tDS
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
0
6
—
—
—
—
0
8
—
—
—
—
0
—
—
—
—
ns
ns
ns
ns
tDH
10
tRWC
tRWD
READ-MODIFY-WRITE Cycle Time
80
45
125
70
140
80
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
tCWD
tAWD
tPC
CAS to WE Delay Time(14, 20)
25
30
12
—
—
—
34
42
20
—
—
—
36
49
25
—
—
—
ns
ns
ns
Column-Address to WE Delay Time(14)
EDO Page Mode READ or WRITE
Cycle Time(24)
tRASP
tCPA
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
35 100K
50 100K
50 100K
ns
ns
ns
—
40
21
—
—
47
27
—
—
56
34
—
tPRWC
EDO Page Mode READ-WRITE
Cycle Time(24)
tCOH
tOFF
Data Output Hold after CAS LOW
5
3
—
15
5
3
—
15
5
3
—
15
ns
ns
Output Buffer Turn-Off Delay from
(13,15,19, 29)
CAS or RAS
tWHZ
Output Disable Delay from WE
3
15
—
3
15
—
3
15
—
ns
ns
tCLCH
Last CAS going LOW to First CAS
10
10
10
returning HIGH(23)
tCSR
tCHR
tORD
CAS Setup Time (CBR REFRESH)(30, 20)
8
8
0
—
—
—
10
10
0
—
—
—
10
10
0
—
—
—
ns
ns
ns
CAS Hold Time (CBR REFRESH)(30, 21)
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
tREF
tT
Refresh Period (512 Cycles)
Transition Time (Rise or Fall)(2, 3)
—
1
8
8
1
—
50
8
1
—
50
ms
ns
50
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
9
IC41C8512
IC41LV8512
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD ≥ tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD
(MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless CAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
10
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
IC41C8512
IC41LV8512
READ CYCLE
t
RC
t
RAS
t
RP
RAS
t
CSH
t
RSH
t
RRH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
CAS
t
AR
t
RAD
tRAL
t
t
RAH
t
CAH
t
ASC
ADDRESS
WE
Row
Column
Row
t
RCS
t
RCH
t
AA
t
RAC
(1)
OFF
t
t
CAC
CLZ
t
Open
Open
Valid Data
I/O
OE
t
OE
tOD
t
OES
Undefined
Don’t Care
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
11
IC41C8512
IC41LV8512
EARLY WRITE CYCLE (OE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
CAS
t
AR
t
RAD
t
t
t
RAL
CAH
ACH
t
t
RAH
t
ASC
ADDRESS
Row
Column
Row
t
t
CWL
RWL
t
WCR
t
WCS
tWCH
t
WP
WE
I/O
t
DHR
t
DH
t
DS
Valid Data
Don’t Care
12
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
IC41C8512
IC41LV8512
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
t
RWC
RAS
t
RP
RAS
CAS
t
CSH
t
RSH
t
CRP
ASR
t
CAS CLCH
t
t
RCD
t
AR
t
RAD
tRAL
t
t
RAH
tCAH
t
ASC
t
ACH
ADDRESS
WE
Row
Column
Row
t
RWD
tCWL
t
RCS
t
CWD
t
RWL
t
AWD
t
WP
t
AA
t
RAC
t
t
CAC
CLZ
t
DS
tDH
Open
Open
Valid DOUT
Valid DIN
I/O
OE
t
OD
tOEH
t
OE
Undefined
Don’t Care
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
13
IC41C8512
IC41LV8512
EDO-PAGE-MODE READ CYCLE
t
RASP
t
RP
RAS
(1)
PC
t
CSH
t
t
RSH
t
CRP
t
CAS,
t
CP
t
CAS,
t
CP
t
CAS,
tCP
t
RCD
t
CLCH
t
CLCH
tCLCH
CAS
t
AR
t
RAD
t
RAL
CAH
t
ASR
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
ADDRESS
WE
Row
Column
Column
Column
Row
t
RAH
t
RRH
t
RCS
t
RCH
t
AA
t
AA
t
AA
t
RAC
CAC
CLZ
t
CPA
t
CPA
t
t
t
CAC
t
t
CAC
CLZ
t
COH
t
OFF
Open
Open
Valid Data
Valid Data
Valid Data
I/O
OE
t
OE
t
OEHC
tOE
t
OD
t
OES
t
OD
t
OES
t
OEP
Undefined
Don’t Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
14
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
IC41C8512
IC41LV8512
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
RASP
t
RP
RAS
t
CSH
t
PC
t
RSH
t
CRP
t
CAS,
t
CP
t
CAS,
t
CP
t
CAS,
tCP
t
RCD
t
CLCH
t
CLCH
tCLCH
CAS
t
AR
tACH
t
ACH
t
ACH
CAH
t
RAD
t
RAL
t
ASR
t
ASC
t
CAH
t
ASC
t
t
ASC
t
CAH
ADDRESS
Row
Column
Column
Column
Row
t
RAH
t
CWL
WCS
WCH
t
CWL
tCWL
t
t
WCS
t
WCS
t
t
WCH
tWCH
t
WP
t
WP
t
WP
WE
t
WCR
DHR
tRWL
t
tDS
tDS
tDS
t
DH
t
DH
tDH
I/O
OE
Valid Data
Valid Data
Valid Data
Don’t Care
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
15
IC41C8512
IC41LV8512
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
t
RASP
t
RP
RAS
CAS
(1)
tPC / tPRWC
t
CSH
t
RSH
CLCH
t
CRP
t
RCD
t
CAS,
t
CLCH
t
CP
t
CAS,
t
CLCH
t
CP
t
CAS,
t
tCP
t
AR
t
ASR
t
t
RAD
t
RAL
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
tCAH
RAH
ADDRESS
Row
Column
Column
Column
Row
tRWD
tRCS
t
t
t
RWL
CWL
WP
t
t
CWL
WP
t
t
CWL
WP
t
AWD
t
AWD
t
AWD
t
CWD
t
CWD
t
CWD
WE
t
AA
t
AA
CPA
t
AA
tCPA
t
t
RAC
t
DH
DS
t
DH
DS
t
DH
tDS
t
t
t
CAC
t
CAC
t
CAC
t
CLZ
t
CLZ
t
CLZ
Open
Open
I/O
OE
DOUT
DIN
OD
DOUT
DIN
OD
DOUT
DIN
OD
t
t
t
t
OE
t
OE
tOE
t
OEH
Undefined
Don’t Care
Note:
1. tPC is for LATE write cycles only. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of
CAS to rising edge of CAS. Both measurements must meet the tPC specifications.
16
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
IC41C8512
IC41LV8512
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
t
RASP
t
RP
RAS
CAS
t
CSH
t
PC
tPC
t
RSH
t
CRP
t
RCD
t
CAS
t
CP
t
CAS
t
CP
t
CAS
tCP
t
AR
t
ACH
RAL
CAH
t
ASR
t
t
RAD
t
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
RAH
ADDRESS
WE
Row
Column (A)
Column (B)
Column (N)
Row
t
RCS
t
RCH
t
WCS
tWCH
t
WHZ
t
AA
t
AA
t
CPA
CAC
COH
t
RAC
CAC
t
t
t
t
DS
tDH
Open
Open
I/O
OE
Valid Data (A)
Valid Data (B)
DIN
t
OE
Don’t Care
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
17
IC41C8512
IC41LV8512
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAS
t
CSH
t
CRP
ASR
t
RCD
tCP
t
CAS
CAS
t
AR
t
RAD
t
t
RAH
t
CAH
tASC
t
ASC
ADDRESS
WE
Row
Column
Column
tRCS
t
WPZ
t
RCS
tRCH
t
AA
t
RAC
t
t
CAC
CLZ
t
WHZ
tCLZ
Open
Open
Valid Data
I/O
OE
t
OE
tOD
Undefined
Don’t Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
t
RC
t
RAS
tRP
RAS
CAS
t
CRP
t
RPC
t
ASR
tRAH
ADDRESS
I/O
Row
Row
Open
Don’t Care
18
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
IC41C8512
IC41LV8512
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
t
RP
t
RAS
t
RP
tRAS
RAS
t
CHR
t
CHR
t
RPC
CP
tRPC
t
t
CSR
tCSR
CAS
I/O
Open
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
t
RAS
t
RAS
t
RP
RAS
CAS
t
CRP
t
RCD
t
RSH
tCHR
t
AR
t
RAD
t
RAL
t
ASR
t
RAH
tCAH
t
ASC
ADDRESS
Row
Column
t
AA
t
RAC
(2)
OFF
t
t
CAC
t
CLZ
Open
Open
Valid Data
I/O
OE
t
OE
tOD
t
ORD
Undefined
Don’t Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
19
IC41C8512
IC41LV8512
ORDERING INFORMATION
IC41C8512
Commercial Range: 0°C to 70°C
ORDERING INFORMATION:
IC41LV8512
Commercial Range: 0°C to 70°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
35
50
60
IC41C8512-35K
IC41C8512-35T
400mil SOJ
400mil TSOP-2
35
50
60
IC41LV8512-35K
IC41LV8512-35T
400mil SOJ
400mil TSOP-2
IC41C8512-50K
IC41C8512-50T
400mil SOJ
400mil TSOP-2
IC41LV8512-50K
IC41LV8512-50T
400mil SOJ
400mil TSOP-2
IC41C8512-60K
IC41C8512-60T
400mil SOJ
400mil TSOP-2
IC41LV8512-60K
IC41LV8512-60T
400mil SOJ
400mil TSOP-2
Industrial Range: -40°C to 85°C
Industrial Range: -40°C to 85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
35
50
60
IC41C8512-35KI
IC41C8512-35TI
400mil SOJ
400mil TSOP-2
35
50
60
IC41LV8512-35KI
IC41LV8512-35TI
400mil SOJ
400mil TSOP-2
IC41C8512-50KI
IC41C8512-50TI
400mil SOJ
400mil TSOP-2
IC41LV8512-50KI
IC41LV8512-50TI
400mil SOJ
400mil TSOP-2
IC41C8512-60KI
IC41C8512-60TI
400mil SOJ
400mil TSOP-2
IC41LV8512-60KI
IC41LV8512-60TI
400mil SOJ
400mil TSOP-2
20
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
IC41C8512
IC41LV8512
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
21
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