AV9110-01CN14 [ICSI]
Serially Programmable Frequency Generator; 串行可编程频率发生器
| 型号： | AV9110-01CN14 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Serially Programmable Frequency Generator |
| 文件： | 总10页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AV9110
Integrated
Circuit
Systems, Inc.
Serially Programmable Frequency Generator
General Description
Features
•
Complete user programmability of output frequency
through serial input data port
On-chip Phase-Locked Loop for clock generation
Generates accurate frequencies up to 130 MHz
Tristate CMOS outputs
The AV9110 generates user specified clock frequencies using
an externally generated input reference, such as 14.318 MHz
or 10.00 MHz crystal connected between pins 1 and 14.
Alternately, a TTL input reference clock signal can be used.
The output frequency is determined by a 24-bit digital word
entered through the serial port. The serial port enables the
user to change the output frequency on-the-fly.
•
•
•
•
•
•
•
•
5 volt power supply
Low power CMOS technology
14-pin DIP or 150-mil SOIC
Very low jitter
The clock outputs utilize CMOS level output buffers that
operate up to 130 MHz.
Wide operating range VCO
Applications
Graphics: The AV9110 generates low jitter, high speed pixel
(or dot) clocks. It can be used to replace multiple expensive
high speed crystal oscillators. The flexibility of this device
allows it to generate nonstandard graphics clocks, allowing
the user to program frequencies on-the-fly.
Block Diagram
9110RevF5/30/00
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
AV9110
Clock Reference Implementations:
AV9110-01 vs. AV9110-02
Pin Configuration
The AV9110 requires a stable reference clock (5 to 32 MHz) to
generate a stable, low jitter output clock. The AV9 11 0 -01 is
optimized to use an external quartz crystal as a frequency
reference, without the need of additional external components.
The AV9110-02 is optimized to accept an TTL clock
reference. Either device can be used with an external crystal
or accept a TTL clock reference, although extra components
may be required. The various combinations implied are
summarized in Figure 2 (see page 7).
14 Pin Dip, SOIC
Pin Descriptions
PIN
TYPE
PIN NUMBER
PIN NAME
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X1
Input Crystal input or TTL reference clock.
Power ANALOG power supply. Connect to +5V.
Power ANALOG GROUND.
Power Digital power supply. Connect to +5V.
Power Digital GROUND.
AVDD
AGND
VDD
GND
DATA
SCLK
CE#
CLK/X
GND
VDD
CLK
OE
Input Serial DATA pin.
Input SERIAL CLOCK. Clocks shift register.
Input CHIP ENABLE. Active low, controls data transfer.
Output CMOS CLOCK divided by X output.
Power Digital GROUND.
Power Digital power supply. Connect to +5V.
Output CMOS CLOCK output.
Input OUTPUT ENABLE. Tristates both outputs when low.
Output Crystal input or TTL reference clock.
X2
2
AV9110
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Voltage on I/O pins referenced to GND . . . . . . GND –0.5 V to VDD +0.5 V
Operating Temperature under bias . . . . . . . . . . 0°C to +70°C
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . 0.8 Watts
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics
VDD = +5V±10%, TA = 0 –70°C unless otherwise stated
DC/STATIC
PARAMETER
Input Low Voltage
SYMBOL
TEST CONDITIONS
VDD = 5V
MIN
TYP
MAX
0.8
-
UNITS
V
VIL
-
2.0
-
-
-
VIH
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage1
Output High Voltage1
Input Clock Rise Time1
Input Clock Fall Time1
Supply Current
VDD = 5V
V
IIL
VIN = OV
-
-5
5
µA
µA
V
IIH
VIN = VDD
IOL = 8Ma
-
-
VOL
VOH IOH = 8Ma
ICLKr
-
-
0.4
-
2.4
-
-
V
-
20
20
-
ns
ICLKf
-
-
ns
IDD
No load
-
25
mA
AC/DYNAMIC
fo
tr
Output frequency range
Rise time, 20-80%1
0.78
-
130
3
MHz
ns
25pF load
25pF load
25pF load
-
-
-
-
Fall time, 80-20%1
3
ns
tf
Duty cycle1 @ 50%
40
-
-
60
-
%
dt
Jitter, 1 sigma1
±40
±125
14.318
14.318
-
ps
Jitter, absolute1
-
-
ps
Input reference freq.; AV9110-011
Input reference freq.; AV9110-021
Input DATA or SCLK frequency1
Skew, Output to Output/X1
Crystal input
TTL input
5
32
32
32
-
MHz
MHz
MHz
ps
fREF
fREF
fDATA
tskew
0.6
-
-
400
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
3
AV9110
Serial Programming
the data to internal latches on the rising edge of the 24th
cycle of the SCLK. Any data entered after the 24th cycle is
ignoreduntilCE#mustremainlowforaminimumof24SLCK
clock cycles. If CE# is taken high before 24 clock cycles have
elapsed, the data is ignored (no frequency change occurs)
and the counter is reset. Tables 1 and 2 display the bit location
for generating the output clock frequency and the output
divider circuitry, respectively.
The AV9110 is programmed to generate clock frequencies by
entering data through the shift register. Figure 1 displays the
proper timing sequence. On the negative going edge of CE#,
the shift register is enabled and the data at the DATA pin is
loaded into the shift register on the rising edge of the SCLK.
Bit D0 is loaded first, followed by D1, D2, etc. This data
consists of the 24 bits shown in the Shift Register Bit
Assignment in Table 1, and therefore takes 24 clock cycles to
load. An internal counter then disables the input and transfers
DEFAULT
-01 -02
EQUATION
VARIABLE
BIT
ASSIGNMENT
VCO frequency divider (LSB)
BIT
0
1
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
1
0
0
1
1
1
1
0
1
0
1
VCO frequency divider
N
Integer
2
VCO frequency divider
2
3
VCO frequency divider
3
4
VCO frequency divider
4
5
VCO frequency divider
5
6
VCO frequency divider (MSB)
6
7
Reference frequency divider (LSB)
Reference frequency divider
7
8
8
9
Reference frequency divider
9
M
Integer
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Reference frequency divider
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Reference frequency divider
Reference frequency divider
Reference frequency divider (MSB)
VCO pre-scale divide (0=divide by 1, 1=divide by 8
CLK/X output divide COD0 (see Table 2)
CLK/X output divide COD1 (see Table 2)
VCO output divide VOD0 (see Table 3)
VCO output divide VOD1 (see Table 3)
Outplut enable CLK (0=tristate)
Output enable CLK/X (0=tristate)
Reserved. Should be programmmed high (1)
Reference clock select on CLK (1 = reference frequency)
Reserved. Should be programmed high (1)
V
X
R
4
AV9110
Output Divider Turth Tables
Table 2
Table 3
CLK/X
Output Divide
(X)
VCO
Output Divide
(R)
COD1
COD0
COD1
COD0
0
0
1
1
0
1
0
1
1
2
4
8
0
0
1
1
0
1
0
1
1
2
4
8
Programming the PLL
The AV9110 has a wide operating range but it is recommended that it is operated within the following limits:
2 MHz < fREF < 32 MHz
fREF
fREF = Input reference frequency
M = Reference divide, 3 to 127
fVCO = VCO output frequency
200 kHz <
< 5MHz
M
50 MHz < fVCO <250 MHz
VCO < 250 MHz
f
fCLK = CLK or CLK/X output frequency
The AV9110 is a classical PLL circuit and the VCO output frequency is given by:
N•V• fREF
fVCO
=
Where N = VCO divided, 3 to 127
M =m Reference divide, 3 to 127
V = Perscale, 1 or 8
M
The 2 output drivers then give the following frequencies:
fVCO
N•V• fREF
fCLK
=
=
or fREF (output mixable by bit 17)
MR
R
fVCO
fVCLK
fCLK/X
=
=
Where R, X = output dividers 1, 2, 4 or 8
X
R•X
Notes:
1. Output frequency accuracy will depend solely on input reference frequency accuracy.
2. For output frequencies below 125 MHz, it is recommended that the VCO output divide, R, should be 2 or greater. This will
give improved duty cycle.
3. The minimum output frequency step size is approximately 0.2% due to the divider range provided.
5
AV9110
Figure 1 - Serial Programming
AC Timing
Parameter
Minimum time (ns)
tsu1
tsu2
th1
10
10
10
10
th2
Frequency Acquisition Time
Jitter
Frequency acquisition (or “lock”) time is the time that it
takes to change from one frequency to another, and is a
function of the difference between the old and new
frequencies. The AV9 11 0 can typically lock to within 1% of
a new frequency in less than 200 microseconds. This is also
true with power-on.
For high performance applications, the AV9110 offers ex-
tremely low jitter and excellent power supply rejection. The
one sigma jitter distribution is typically less than ±125ps.
For optimum performance, the device should be decoupled
with both a 2.2mF and a 0.1mF capacitor. Refer to
Recommended Board Layout diagram on page 8.
Power-On Reset
Output Enable
Upon power-up the internal latches are preset to provide the
following output clock frequencies (14.318 MHz reference
assumed):
The AV9110 outputs can be disabled with either the OE pin
orthroughserialprogramming. SettingtheOEpinlowtristates
CLK and CLK/X. Alternatively, setting bits D19 and D20
low in the serial word will tristate the two outputs. Both the
OE pin and D19 or D20 must be high to enable an output.
Device
CLK output
25.175 MHz
25.175 MHz
CLK/X output
6.29 MHz
12.59 MHz
AV9110-01
AV9110-02
Frequency Transition Glitches
These preset default frequencies can be changed with a custom
metal mask, as can other attributes.
The AV9110 starts changing frequency on the rising edge of
the 24th serial clock. If the programming of any output
divider is changed, the output clock may glitch before locking
to the new frequency in less than 200µs with no output
glitches (no partial clock cycles).
The actual numbers of these output clock frequencies
(14.318MHz reference assumed) are:
Device
AV9110-01
AV9110-02
CLK output
25.255 MHz
25.255 MHz
CLK/X output
6.31 MHz
12.63 MHz
and these are within 0.32%.
6
AV9110
AV9110 Quartz Crystal Selection
Toyocom
Part Number
When an external quartz crystal will be used as a frequency
reference for the AV9110, attention needs to be given to
crystal selection if accurate reference frequency and output
frequency is desired. The AV9110 uses a Pierce oscillator
design which operates the quartz crystal in parallel-resonant
mode. It requires a quartz crystal cut for parallel-resonant
operation to ensure an accurate frequency of oscillation (a
less expensive series-reso-nant crystal can be used with the
device but it will oscillate approximately 0.1% too fast). The
AV9110-01 has internal crystal load capacitors which result
in a total crystal load capacitance of approximately
12pF±10%.The AV9110-02 does not have internal load
capacitors, but contributes about 3pFload capacitance to the
crystal.
TN4-30374 ........ 14.318 MHz surface mount crystal
TN4-30375 ........ 20 MHz surface mount crystal
TN4-30376 ........ 14.318 MHz through-hole crystal
TN4-30377 ........ 20 MHz through-hole crystal
Epson
Part Number
MA-505 or ......... Surface mount crystal
MA-506
CA-301 .............. Through-hole crystal
Following is a list of recommended crystal devices for the
AV9110. They have been tested by the crystal manufacturer
to operate suitably with the AV91xx-series crystal oscillator
de-sign, having load capacitance characteristics that are
compatible with the AV9110-01.
Using AV9110-01 with a crystal
Using AV9110-01 with an external clock
Using AV9110-02 with a crystal
Using AV9110-02 with an external clock
Figure 2 - Clock Reference Combinations
7
AV9110
AV9110 Recommended Board Layout
This is the recommended layout for the AV9110 to maximize clock performance. Shown are the power and ground connections,
the ground plane, and the input/output traces.
Use of the isolated ground plane and power connection, as shown, will prevent stray high frequency ground and system noise
from coupling to the AV9110. As when compared to using the system ground and power planes, this technique will lessen
output clock jitter. The isolated ground plane should be connected to the system ground plane at one point near the 2.2mF
decoupling cap. For lowest jitter performance, the isolated ground plane should be kept away from clock output pins and
traces. Keeping the isolated ground plane area as small as possible will minimize EMI radiation. Use a sufficient gap between
the isolated ground plane and system ground plane to prevent AC coupling. The ferrite bead in the VDD line is optional, but
will help reduce EMI.
The traces to distribute the output clocks should be over an unbroken system ground or power supply plane. The trace width
should be about two times the thickness of the PC board between the trace and the underlying plane. These guidelines help
minimize clock jitter and EMI radiation. The traces to distribute power should be as wide as possible.
8
AV9110
AV9110 Typical Duty Cycle
VCO Output Divide, R = 1
Duty Cycle will improve if R > 1
MHz
AV9110 Idd
CL = pF, R = 1
MHz
9
AV9110
14-Pin DIP Package
14-Pin 150 mil SOIC Package
Ordering Information
AV9110-01CN14, AV9110-02CN14
AV9110-01CS14, AV9110-02CS14
Example:
ICS XXXX S-PPP X#W
Lead Count
Lead Count=1,2 or 3 digits
Pattern Number(2 or 3 digit number for parts with ROM code patterns)
Package Type
S=SOIC
N=DIP (plastic)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS=Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
10
相关型号：
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PLL Based Clock Driver, 91 Series, 9 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SSOP-16
IDT
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