3022A [ICSI]
FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR; FEMTOCLOCKS -TM CRYSTAL - TO- 3.3V LVPECL时钟发生器
| 型号： | 3022A |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR |
| 文件： | 总13页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS843022
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
3.3V LVPECL CLOCK
GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS843022 is a Fibre Channel Clock Generator • 1 differential 3.3V LVPECL output
ICS
and a member of the HiPerClocksTM family of high
• Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
HiPerClockS™
performance devices from ICS. The ICS843022
uses a 25MHz crystal to synthesize 125MHz or
62.5MHz. The ICS843022 has excellent phase
• Output frequencies: 125MHz or 62.5MHz (selectable)
jitter performance, over the 12KHz – 20MHz integration range.
The ICS843022 is packaged in a small 8-pin TSSOP, making
it ideal for use in systems with limited board space.
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(12KHz - 20MHz): 0.62ps (typical)
• RMS phase noise at 125MHz (typical)
Offset
Noise Power
100Hz ............... -94.6 dBc/Hz
1KHz ..............-122.8 dBc/Hz
10KHz ..............-132.2 dBc/Hz
100KHz ..............-132.0 dBc/Hz
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
FUNCTION TABLE
Inputs
Output Frequencies
(with a 25MHz crystal)
FREQ_SEL
0
1
125MHz
62.5MHz
BLOCK DIAGRAM
PIN ASSIGNMENT
VCCA
VEE
VCC
1
2
3
4
8
7
6
5
Q0
XTAL_IN
XTAL_OUT
XTAL_IN
nQ0
nQ0
Q0
Output
Divider
OSC
FREQ_SEL
XTAL_OUT
ICS843022
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
TopView
FREQ_SEL
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843022AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
1
PRELIMINARY
ICS843022
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
3.3V LVPECL CLOCK
GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
VCCA
VEE
Type
Description
1
2
Power
Power
Analog supply pin.
Negative supply pin.
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_in is the input,
XTAL_OUT is the output.
3, 4
Input
5
6, 7
8
FREQ_SEL
nQ0, Q0
VCC
Input
Output
Power
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Differential clock outputs. LVPECL interface levels.
Core supply pin.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pulldown Resistor
4
pF
RPULLDOWN
51
KΩ
843022AG
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REV. A NOVEMBER 30, 2004
2
PRELIMINARY
ICS843022
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
3.3V LVPECL CLOCK
GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
101.7°C/W (0 mps)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
IEE
Core Supply Voltage
3.465
3.465
85
V
V
Analog Supply Voltage
Power Supply Current
3.135
3.3
mA
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
-0.3
Input High Current FREQ_SEL
Input Low Current FREQ_SEL
VCC = VIN = 3.465V
150
µA
µA
IIL
VCC = 3.465V, VIN = 0V
-5
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCC - 1.4
VCC - 2.0
0.6
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
25
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
843022AG
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REV. A NOVEMBER 30, 2004
3
PRELIMINARY
ICS843022
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
3.3V LVPECL CLOCK
GENERATOR
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
125
MHz
MHz
fOUT
Output Frequency
62.5
125MHz,
Integration Range: 12KHz - 20MHz
62.5MHz,
Integration Range: 12KHz - 20MHz
0.62
0.63
ps
ps
tjit(Ø)
RMS Phase Jitter; NOTE 1
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
400
50
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plot.
843022AG
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REV. A NOVEMBER 30, 2004
4
PRELIMINARY
ICS843022
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
3.3V LVPECL CLOCK
GENERATOR
TYPICAL PHASE NOISE AT 125MHZ
0
-10
-20
Fibre Channel Filter
125MHz
RMS Phase Jitter (Random)
12KHz to 20MHz = 0.62ps (typical)
-30
-40
-50
-60
-70
-80
-90
-100
-110
Raw Phase Noise Data
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
Fibre Channel Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843022AG
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REV. A NOVEMBER 30, 2004
5
PRELIMINARY
ICS843022
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
3.3V LVPECL CLOCK
GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
SCOPE
VCC
Qx
LVPECL
VEE
Phase Noise Mask
nQx
Offset Frequency
f1
f2
-1.3V 0.165V
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ0
80ꢀ
tF
80ꢀ
tR
Q0
VSWING
20ꢀ
Pulse Width
tPERIOD
Clock
Outputs
20ꢀ
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
843022AG
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REV. A NOVEMBER 30, 2004
6
PRELIMINARY
ICS843022
Integrated
Circuit
Systems, Inc.
FEMTO
CLOCKS™ CRYSTAL- -
TO
3.3V LVPECL CLOCK
GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS843022 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, and VCCA should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10 µF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843022 has been characterized with 18pF parallel resonant crystal and were chosen to minimize the ppm error.
resonant crystals. The capacitor values, C1 and C2, shown in The optimum C1 and C2 values can be slightly adjusted for
Figure 2 below were determined using a 25MHz, 18pF parallel different board layouts.
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
Figure 2. CRYSTAL INPUt INTERFACE
843022AG
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REV. A NOVEMBER 30, 2004
7
PRELIMINARY
ICS843022
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
3.3V LVPECL CLOCK
GENERATOR
APPLICATION SCHEMATIC
Figure 3A shows a schematic example of the ICS843022. An output frequency. The C1 = 27pF and C2 = 33pF are recom-
example of LVEPCL termination is shown in this schematic. mended for frequency accuracy.For different board layout, the
C1 and C2 values may be slightly adjusted for optimizing fre-
Additional LVPECL termination approaches are shown in the
LVPECLTermination Application Note.In this example, an 18pF quency accuracy.
parallel resonant 25MHz crystal is used for generating 125MHz
VCC
VCCA
VCC
VCC
R2
10
C3
10uF
C4
0.1u
R1
R3
R5
1K
133
133
U1
Zo = 50 Ohm
Zo = 50 Ohm
Q
VCC
1
8
7
6
5
VCCA
VEE
VCC
Q0
nQ0
+
-
2
3
4
XTAL_OUT
XTAL_OUT
XTAL_IN
FREQ_SEL
nQ
C2
33pF
X1
25MHz
ICS843022
XTAL_IN
18pF
R4
82.5
R6
82.5
C5
0.1u
C1
27pF
FIGURE 3A. ICS843022 SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of P.C. board layout. The crystal
X1 footprint in this example allows either surface mount (HC49S)
or through hole (HC49) package. C3 is 0805. C1 and C2 are
0402. Other resistors and capacitors are 0603.This layout as-
sumes that the board has clean analog power and ground planes.
FIGURE 3B. ICS843022 PC BOARD LAYOUT EXAMPLE
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843022AG
REV. A NOVEMBER 30, 2004
8
PRELIMINARY
ICS843022
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
3.3V LVPECL CLOCK
GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843022.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843022 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 85mA = 294.5mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 294.5mW + 30mW = 324.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.325W * 90.5°C/W = 99.4°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC StandardTest Boards
101.7°C/W
90.5°C/W
843022AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
9
PRELIMINARY
ICS843022
Integrated
Circuit
Systems, Inc.
FEMTO
CLOCKS™ CRYSTAL- -
TO
3.3V LVPECL CLOCK
GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mWL
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843022AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
10
PRELIMINARY
ICS843022
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
3.3V LVPECL CLOCK
GENERATOR
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TRANSISTOR COUNT
The transistor count for ICS843022 is: 1928
843022AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
11
PRELIMINARY
ICS843022
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
3.3V LVPECL CLOCK
GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843022AG
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REV. A NOVEMBER 30, 2004
12
PRELIMINARY
ICS843022
Integrated
Circuit
Systems, Inc.
FEMTO
CLOCKS™ CRYSTAL- -
TO
3.3V LVPECL CLOCK
GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS843022AG
Marking
Package
Count
Temperature
0°C to 70°C
0°C to 70°C
3022A
3022A
8 lead TSSOP
100 per tube
ICS843022AGT
8 lead TSSOP on Tape and Reel
2500
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
843022AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
13
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