X76F101PI [ICMIC]
Secure SerialFlash; 安全SerialFlash
| 型号： | X76F101PI |
| 厂家： | 
IC MICROSYSTEMS |
| 描述： | Secure SerialFlash |
| 文件： | 总17页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
This X76F101 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
ICmic
128 x 8 bit
IC MICROSYSTEMS
1K
X76F101
Secure SerialFlash
FEATURES
DESCRIPTION
•64-bit Password Security
•One Array (112 Bytes) Two Passwords
The X76F101 is a Password Access Security Supervisor,
containing one 896-bit Secure Serial Flash array. Access
—Read Password
—Write Password
to the memory array can be controlled by two 64-bit
passwords. These passwords protect read and write
operations of the memory array.
•Programmable Passwords
•32-bit Response to Reset (RST Input)
•8 byte Sector Write mode
The X76F101 features a serial interface and software
protocol allowing operation on a popular two wire bus.
•1MHz Clock Rate
•2 wire Serial Interface
•Low Power CMOS
The bus signals are a clock Input (SCL) and a bidirectional
data input and output (SDA). Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same bus.
—3.0 to 5.5V operation
—Standby current Less than 1µA
—Active current less than 3 mA
The X76F101 also features a synchronous response to reset
providing an automatic output of a hard-wired 32-bit
•High Reliability Endurance:
—100,000 Write Cycles
data stream conforming to the industry standard for
memory cards.
•Data Retention: 100 years
•Available in:
TM
The X76F101 utilizes Xicor’s proprietary Direct Write
—8 lead PDIP, SOIC, MSOP and ISO Card
—SmartCard Module
cell, providing a minimum endurance of 100,000 cycles and
a minimum data retention of 100 years.
Functional Diagram
8K BYTE
CS
CHIP ENABLE
SerialFlash ARRAY
ARRAY 0
DATA TRANSFER
SCL
SDA
(PASSWORD PROTECTED)
ARRAY ACCESS
ENABLE
Interface
Logic
112 Byte
32 BYTE
SerialFlash ARRAY
ARRAY 1
(PASSWORD PROTECTED)
PASSWORD ARRAY
AND PASSWORD
VERIFICATION LOGIC
RST
RETRY COUNTER
RESET
RESPONSE REGISTER
7025 FM 01
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
Characteristics subject to change without notice
1
7065 -1.1 4/17/98 T2/C0/D0 SH
X76F101
PIN DESCRIPTIONS
Serial Clock (SCL)
To ensure the correct communication, RST must remain LOW
under all conditions except when running a
“Response to Reset sequence”.
The SCL input is used to clock all data into and out of the
device.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
Serial Data (SDA)
SDA is an open drain serial data input/output pin. During a
read cycle, data is shifted out on this pin. During a write
If the X76F101 is in a nonvolatile write cycle a “no ACK”
(SDA=High) response will be issued in response to
cycle, data is shifted in on this pin. In all other cases, this pin is
in a high impedance state.
loading of the command byte. If a stop is issued prior to the
nonvolatile write cycle the write operation will be
Chip Select (CS)
terminated and the part will reset and enter into a
standby mode.
When CS is high, the X76F101 is deselected and the
SDA pin is at high impedance and unless an internal
The basic sequence is illustrated in Figure 1.
write operation is underway, the X76F101 will be in
standby mode. CS low enables the X76F101, placing it in
the active mode.
PIN NAMES
Symbol
CS
Description
Chip Select Input
Reset (RST)
RST is a device reset pin. When RST is pulsed high
while CS is low the X76F101 will output 32 bits of fixed
SDA
SCL
RST
Vcc
Vss
NC
Serial Data Input/Output
Serial Clock Input
Reset Input
data which conforms to the standard for “synchronous
response to reset”. CS must remain LOW and the part
must not be in a write cycle for the response to reset to occur.
See Figure 7. If at any time during the response to
Supply Voltage
Ground
reset CS goes HIGH, the response to reset will be
aborted and the part will return to the standby state. The
No Connect
response to reset is "mask programmable" only!
PIN CONFIGURATION
DEVICE OPERATION
Smart Card
PDIP
The X76F101 memory array consists of fourteen 8-byte
sectors. Read or write access to the array always begins
VCC
RST
SCL
1
2
8
7
6
5
NC
at the first address of the sector. Read operations then can
continue indefinitely. Write operations must total 8
NC
3
4
SDA
CS
bytes.
Vss
There are two primary modes of operation for the
X76F101; Protected READ and protected WRITE.
SOIC
VSS
VCC
1
2
8
7
6
5
Protected operations must be performed with one of two
8-byte passwords.
GND
VCC
RST
CS
SDA
NC
3
4
SCL
NC
RST
CS
The basic method of communication for the device is
established by first enabling the device (CS LOW),
SCL
NC
SDA
NC
generating a start condition, then transmitting a command,
followed by the correct password. All parts will
MSOP
be shipped from the factory with all passwords equal to ‘0’.
The user must perform ACK Polling to determine the
VSS
NC
VCC
NC
1
2
8
7
6
5
validity of the password, before starting a data transfer (see
Acknowledge Polling.) Only after the correct
RST
CS
3
4
SCL
SDA
password is accepted and a ACK polling has been
performed, can the data transfer occur.
2
X76F101
After each transaction is completed, the X76F101 will reset
and enter into a standby mode. This will also be the
A start may be issued to terminate the input of a control
byte or the input data to be written. This will reset the
response if an unsuccessful attempt is made to access a
protected array.
device and leave it ready to begin a new read or write
command. Because of the push/pull output, a start
cannot be generated while the part is outputting data.
Starts are inhibited while a write is in progress.
Figure 1. X76F101 Device Operation
Stop Condition
LOAD COMMAND/ADDRESS BYTE
All communications must be terminated by a stop
condition. The stop condition is a LOW to HIGH transition
of SDA when SCL is HIGH. The stop condition is also
used to reset the device during a command or data input
LOAD 8-BYTE
PASSWORD
sequence and will leave the device in the standby power
mode. As with starts, stops are inhibited when outputting
data and while a write is in progress.
VERIFY PASSWORD
ACCEPTANCE BY
USE OF ACK POLLING
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received the
eight bits of data.
READ/WRITE
DATA
BYTES
The X76F101 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F101 will respond with an acknowledge
after the receipt of each subsequent eight-bit word.
Device Protocol
The X76F101 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as a
receiver. The device controlling the transfer is a master
and the device being controlled is the slave. The master will
always initiate data transfers and provide the clock for
both transmit and receive operations. Therefore, the
X76F101 will be considered a slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA changes during SCL HIGH are reserved for
indicating start and stop conditions. Refer to Figure 2 and
Figure 3.
Start Condition
All commands are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F101 continuously monitors the SDA and SCL
lines for the start condition and will not respond to
any command until this condition is met.
3
X76F101
Figure 2. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 3. Definition of Start and Stop Conditions
SCL
SDA
Start Condition
Stop Condition
Table 1. X76F101 Instruction Set
Command
after Start
Password
used
Command Description
1 0 0 S S S S 0
1
Sector Write
Sector Read
Write
Read
Write
Write
None
3
2
0
1 0 0 S S S S 1
1
3
2
0
1 1 1 1 1 1 0 0
1 1 1 1 1 1 1 0
0 1 0 1 0 1 0 1
Change Write Password
Change Read Password
Password ACK Command
Illegal command codes will be disregarded. The part will respond with a “no-ACK” to the illegal byte and then return to the
standby mode. All write/read operations require a password.
PROGRAM OPERATIONS
Sector Write
issued which starts the nonvolatile write cycle. If more or less
than 8 bytes are transferred, the data in the sector
remains unchanged.
The sector write mode requires issuing the 8-bit write
command followed by the password and then the data
ACK Polling
bytes transferred as illustrated in figure 4. The write
command byte contains the address of the sector to be
Once a stop condition is issued to indicate the end of the
host’s write sequence, the X76F101 initiates the internal
written. Data is written starting at the first address of a sector
and eight bytes must be transferred. After the last
nonvolatile write cycle. In order to take advantage of the
typical 5ms write cycle, ACK polling can begin
byte to be transferred is acknowledged a stop condition is
immediately. This involves issuing the start condition
4
X76F101
followed by the new command code of 8 bits (1st byte of the
protocol.) If the X76F101 is still busy with the
Password ACK Polling Sequence
nonvolatile write operation, it will issue a “no-ACK” in
response. If the nonvolatile write operation has
PASSWORD LOAD
COMPLETED
completed, an “ACK” will be returned and the host can then
proceed with the rest of the protocol.
ENTER ACK POLLING
ISSUE START
Data ACK Polling Sequence
WRITE SEQUENCE
COMPLETED
ISSUE
PASSWORD
ENTER ACK POLLING
ACK COMMAND
ISSUE START
NO
ACK
RETURNED?
ISSUE NEW
COMMAND
CODE
YES
PROCEED
NO
ACK
RETURNED?
YES
READ OPERATIONS
PROCEED
Read operations are initiated in the same manner as write
operations but with a different command code.
Sector Read
After the password sequence, there is always a nonvolatile
write cycle. This is done to discourage random
With sector read, a sector address is supplied with the read
command. Once the password has been
guesses of the password if the device is being tampered with.
In order to continue the transaction, the X76F101
acknowledged data may be read from the sector. An
acknowledge must follow each 8-bit data transfer. A read
requires the master to perform a password ACK polling
sequence with the specific command code of 55h. As
operation always begins at the first byte in the sector, but may
stop at any time. Random accesses to the array are
with regular Acknowledge polling the user can either time out
for 10ms, and then issue the ACK polling once, or
not possible. Continuous reading from the array will return
data from successive sectors. After reading the
continuously loop as described in the flow.
last sector in the array, the address is automatically set to the
first sector in the array and data can continue to be
If the password that was inserted was correct, then an
“ACK” will be returned once the nonvolatile cycle in
read out. After the last bit has been read, a stop condition is
generated without sending a preceding acknowledge.
response to the password ACK polling sequence is over.
If the password that was inserted was incorrect, then a “no
ACK” will be returned even if the nonvolatile cycle is
over. Therefore, the user cannot be certain that the pass-
word is incorrect until the 10ms write cycle time has
elapsed.
5
X76F101
Figure 4. Sector Write Sequence (Password Required)
Write
Password
7
Write
Password
0
Host
Commands
WRITE
COMMAND
Wait tWC OR
Password
ACK
Command
SDA
S
X76F101
Response
If ACK, Then
Password Matches
Host
Commands
Password ACK
COMMAND
Wait tWC Data
ACK Polling
. . .
P
S
X76F101
Responce
Figure 5. Acknowledge Polling
SCL
SDA
8th clk.
of 8th
pwd. byte
‘ACK’
clk
‘ACK’
clk
8th
clk
8th bit
‘ACK’
ACK or
no ACK
START
condition
Figure 6. Sector Read Sequence (Password Required)
Read
Password
7
Read
Password
0
Host
Commands
READ
COMMAND
Wait tWC OR
Password
ACK
Command
SDA
S
X76F101
Response
If ACK, Then
Password Matches
Host
Commands
Password ACK
COMMAND
. . .
S
P
Data n
Data 0
X76F101
Responce
6
X76F101
PASSWORDS
This conforms to the ISO standard for “synchronous
response to reset”. CS must remain LOW and the part
Passwords are changed by sending the "change read
password" or "change write password" commands in a
must not be in a write cycle for the response to reset to
occur.
normal sector write operation. A full eight bytes
containing the new password must be sent, following
After initiating a nonvolatile write cycle the RST pin must not
be pulsed until the nonvolatile write cycle is complete.
successful transmission of the current write password and
a valid password ACK response. The user can use a
If not, the ISO response will not be activated. Also, any attempt
to pulse the RST pin in the middle of an ISO
repeated ACK Polling command to check that a new
password has been written correctly. An ACK indicates
transaction will stop the transaction with the SDA pin in high
impedance. The user will have to issue a stop
that the new password is valid.
condition and start the transaction again. If at any time
during the Response to Reset CS goes HIGH, the
There is no way to read any of the passwords.
response to reset will be aborted and the part will return
to the standby state. A Response to Reset is not
RESPONSE TO RESET (DEFAULT = 19 01 AA 55)
available during a nonvolatile write cycle.
The ISO Response to reset is controlled by the RST, CS and
CLK pins. When RST is pulsed high, while CS is low,
the device will output 32 bits of data, one bit per clock.
Continued clocks after the 32 bits, will output the 32 bit
sequence again, starting at byte 0.
Figure 7. Response to RESET (RST)
CS
RST
SCK
SO
MSB
LSB
LSB
MSB
MSB LSB
MSB
LSB
2
3
Byte
0
1
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias.....................–65°C to +135°C
Storage Temperature.........................–.65°C to +150°C
Voltage on any Pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of the
device at these or any other conditions above those
Respect to V .....................................–..1V to +7V
SS
D.C. Output Curren.t..............................................5..m. A
Lead Temperature
(Soldering, 10 seconds.)................................3.00°C
listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
7
X76F101
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
Max.
+70°C
+85°C
Supply Voltage
X76F101
Limits
0°C
4.5V to 5.5V
3.0V to 5.5V
–40°C
X76F101 – 3
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz,
SDA = Open
RST = CS = V
VCC Supply Current
(Read)
ICC1
1
mA
SS
fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz,
SDA = Open
RST = CS = V
VCC Supply Current
(Write)
(3)
ICC2
3
mA
SS
VIL = VCC x 0.1, VIH = VCC x 0.9
fSCL = 400 KHz, fSDA = 400 KHz
VCC Supply Current
(Standby)
(1)
ISB1
1
1
µA
µA
= VCC Other =
VSDA = VSCC
VCC Supply Current
(Standby)
(1)
ISB2
GND or VCC–0.3V
VIN = VSS to VCC
VOUT = VSS to VCC
ILI
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
ILO
(2)
VIL
VCC x 0.3
–0.5
(2)
VIH
VCC x 0.7VCC + 0.5
0.4
Input HIGH Voltage
Output LOW Voltage
V
VOL
IOL = 3mA
V
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
CC
A
Symbol
(3)
Test
Max.
Units
pF
Conditions
VI/O = 0V
COUT
(3)
Output Capacitance (SDA)
8
6
CIN
VIN = 0V
Input Capacitance (RST, SCL, CS)
pF
NOTES: (1)
Must perform a stop command after a read command prior to measurement
(2) VIL min. and V max. are for reference only and are not tested.
IH
(3) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
VCC x 0.1 to VCC x 0.9
10ns
Input Pulse Levels
5V
3V
Input Rise and Fall Times
Input and Output Timing Level
Output Load
1.53KΟ
1.3KΟ
VCC x 0.5
100pF
OUTPUT
OUTPUT
100pF
100pF
8
X76F101
AC CHARACTERISTICS
(T = -40˚C to +85˚C, V = +3.0V to +5.5V, unless otherwise specified.)
A CC
Symbol
fSCL
Parameter
Min
Max
Units
MHz
∝s
∝s
∝s
∝s
∝s
∝s
∝s
SCL Clock Frequency
0
1
(3)
tAA
SCL LOW to SDA Data Out Valid
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
0.1
0.9
tBUF
1.2
tHD:STA
tLOW
0.6
Clock LOW Period
1.2
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
Clock HIGH Period
0.6
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
0.6
0
Data In Setup Time
100
ns
ns
(2)
(2)
20+0.1XCb
SDA and SCL Rise Time
300
300
20+0.1XCb
tF
SDA and SCL Fall Time
ns
∝s
tSU:STO
tDH
Stop Condition Setup Time
0.6
0.1
500
0
∝s
Data Out Hold Time
tNOL
RST to SCL Non-Overlap
ns
ns
ns
ns
tRDV
RST LOW to SDA Valid During Response to Reset
CLK LOW to SDA Valid During Response to Reset
Device Deselect to SDA high impedance
Device Select to RST active
450
450
450
tCDV
0
tDHZ(1)
tSR(1)
tRST
0
0
ns
∝s
RST High Time
1.5
500
200
100
tSU:RST
tSU:CS
tSU:CS
RST Setup Time
CS Setup Time
ns
ns
ns
CS Hold Time
Notes:1.
These Specs are not defined in the ISO 7816-3 Standard, since CS is not defined.
2. Cb = total capacitance of one bus line in pF
3. tAA = 1.1µs Max below VCC = 3.0V.
RESET AC SPECIFICATIONS
Power Up Timing
(2)
Symbol
(1)
Parameter
Min.
Typ
Max.
Units
tPUR
Time from Power Up to Read
Time from Power Up to Write
1
5
mS
mS
(1)
tPUW
Notes:1.
Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not
100% tested.
2. Typical values are for TA = 25˚C and VCC = 5.0V
9
X76F101
Nonvolatile Write Cycle Timing
Symbol
Parameter
Write Cycle Time
Min.
Typ.(1)
Max.
Units
(1)
tWC
5
10
mS
Notes:1.
tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
BUS TIMING
SCL
t
t
t
t
HIGH
LOW
R
F
t
t
t
t
t
SU:STA
HD:STA
HD:DAT
SU:DAT
SU:STO
SDA IN
t
t
t
AA
DH
BUF
SDA OUT
Write Cycle Timing
SCL
8th bit of last byte
ACK
SDA
tWC
Stop
Condition
Start
Condition
CS Timing Diagram (Selecting/Deselecting the Part)
SCL
tHD:CS
tSU:CS
CS
from
master
10
X76F101
RST Timing Diagram – Response to a Synchronous Reset
tSR
CS
RST
tRST
tHIGH_RST
tNOL
tNOL
1st
clk
pulse
2nd
clk
pulse
3rd
clk
pulse
CLK
I/O
tLOW_RST
tSU:RST
tCDV
tRDV
DATA BIT (2)
DATA BIT (1)
CS
RST
CLK
tDHZ
I/O
DATA BIT (N+1)
(N+2)
DATA BIT (N)
GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS
100
V
CCMAX
------------------------=-- 1.8KΟ
OLMIN
80
R
=
MIN
I
R
MAX
60
40
20
t
R
----------------
BUS
R
-
=
MAX
C
R
MIN
20
40 60 80 100
tR = maximum allowable SDA rise time
Bus capacitance in pF
11
X76F101
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.300
(7.62) REF.
0.060 (1.52)
0.020 (0.51)
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.065 (1.65)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
.073 (1.84)
MAX.
0°
15°
TYP
0.010 (0.25)
.
NOTE:
1.ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2.
PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
12
X76F101
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.020 (.508)
0.012 (.305)
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
(5.41) .205
(5.21)
.213
.330
(8.38) .300
(7.62)
PIN 1 INDEX
PIN 1 ID
PIN 1
0.014 (0.35)
0.019 (0.49)
.050 (1.27) BSC
0.188 (4.78)
0.197 (5.00)
.212
(5.38) .203
(5.16)
(4X) 7°
.080
(2.03) .070
(1.78)
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
.013
0.010 (0.25)
(.330) .004
(.102)
0.050 (1.27)
0
REF
8
0.050" TYPICAL
0.010 (0.25)
0.020 (0.50)
.010
(.254) .007
(.178)
X 45°
0.050"
TYPICAL
.035
(.889) .020
(.508)
0° – 8°
0.250"
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN P
0.030"
TYPICAL
8 PLACES
7025 FM 24
FOOTPRINT
ARENTHESES IN MILLIMETERS) 2.
PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
13
X76F101
8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M
0.118 0.002
(3.00 0.05)
0.012 + 0.006 / -0.002
0.0256 (0.65) TYP
(0.30 + 0.15 / -0.05)
R 0.014 (0.36)
0.118 0.002
(3.00 0.05)
0.030 (0.76)
0.0216 (0.55)
7°TYP
0.036 (0.91)
0.032 (0.81)
0.0256" TYPICAL
0.040 0.002
(1.02 0.05)
0.008 (0.20)
0.004 (0.10)
0.025"
TYPICAL
0.220"
0.150 (3.81)
0.020"
TYPICAL
8 PLACES
0.007 (0.18)
0.005 (0.13)
REF.
0.193 (4.90)
REF.
FOOTPRINT
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
3003 ILL 01
14
X76F101
8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X
SMART CARD TYPE Y
3.369 0.002
(85.57 0.05)
3° MAX.
DRAFT ANGLE
(ALL AROUND)
0.593 0.002
(15.06 0.05)
0.430 0.002
(10.92 0.05)
R. 0.125
(3.18) (4x)
A
0.010
0.25)
2.125 0.00
(53.98 0.05
A
R. 0.030 (0.76) (4x)
15
X76F101
X76F041 8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X
0.465 0.002
(11.81 0.05)
0.088 (2.24) MIN EPOXY
FREE AREA (TYP.)
0.285 (7.24) MAX.
SEE NOTE 7 SHT. 2
R. 0.078 (2.00)
0.069 (1.75) MIN EPOXY
FREE AREA (TYP.)
0.270 (6.86) MAX.
SEE NOTE 7 SHT. 2
0.420 0.002
(10.67 0.05)
A
A
0.008 0.001
(0.20 0.03)
0.210 0.002
(5.33 0.05)
0.233 0.002
(5.92 0.05)
DIE
0.0235 (0.60) MAX.
SECTION A-A
GLOB SIZE
0.015 (0.38) MAX.
0.008 (0.20) MAX.
FR4 TAPE
SEE DETAIL SHEET 3
COPPER, NICKEL PLATED, GOLD FLASH
0.174 0.002
(4.42 0.05)
0.146 0.002
(3.71 0.05)
R. 0.013 (0.33) (8x)
Vcc
RST
SCL
NC
Vss
CS
0.105 0.002
(2.67 0.05)
TYP.
(8x)
SDA
NC
0.105 0.002
(2.67 0.05)
(8x)
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
SC Type X ILL 1.0
16
X76F101
ORDERING INFORMATION
X76F101
P
T
G
-V
VCC Limits
Blank = 5V 10%
3.0 = 3.0V to 5.5V
Device
G = RoHS Compliant Lead Free package
Blank = Standard package. Non lead free
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial= –40°C to +85°C
Package
S = 8-Lead SOIC
M = 8- Lead MSOP
P = 8-Lead PDIP
H = Die in Waffle Packs
W = Die in Wafer Form
X = Smart Card Module
Y = Smart Card
Part Mark Convention
8-Lead MSOP
8-Lead SOIC/PDIP
EYWW
XXX
X76F101 XG
XX
A = 8-Lead SOIC
G = RoHS compliant Lead Free
AAQ = 3.0 to 5.5V, 0 to +76°C
AAR = 3.0 to 5.5V, -40 to +85°C
AAS = 4.5 to 5.5V, 0 to +76°C
AAT = 4.5 to 5.5V, -40 to +85°C
D = 3.0 to 5.5V, 0 to +70°C
E = 3.0 to 5.5V, -40 to +85°C
Blank = 4.5 to 5.5V, 0 to +70°C
I = 4.5 to 5.5V, -40 to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no
warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without
notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402;
4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and
correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1.
2.
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
17
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