X24C02_技术文档

TM

ICmic

256 x 8 Bit

This X24C02 device has been acquired by

IC Microsystems Sdn Bhd from Xicor, Inc.

IC MICROSYSTEMS

2K

X24C02

Serial E²PROM

FEATURES

•2.7V to 5.5V Power Supply

•Low Power CMOS

—Active Current Less Than 1 mA

DESCRIPTION

The X24C02 is CMOS a 2048 bit serial E²PROM,

internally organized 256 x 8. The X24C02 features a serial

interface and software protocol allowing operation on a

simple two wire bus. Three address inputs allow up to eight

—Standby Current Less Than 50 ∝A

•Internally Organized 256 x 8

devices to share a common two wire bus.

•Self Timed Write Cycle

—Typical Write Cycle Time of 5 ms

•2 Wire Serial Interface

Xicor E²PROMs are designed and tested for applications

requiring extended endurance. Inherent data

—Bidirectional Data Transfer Protocol

•Four Byte Page Write Operation

—Minimizes Total Write Time Per Byte

•High Reliability

retention is greater than 100 years. Available in DIP,

MSOP and SOIC packages.

—Endurance: 100,000 Cycles

—Data Retention: 100 Years

•New Hardwire—Write Control Function

FUNCTIONAL DIAGRAM

(8)

(4)

V

CC

SS

(7) WC

H.V. GENERATION

START CYCLE

TIMING

& CONTROL

(5) SDA

START

STOP

LOGIC

CONTROL

LOGIC

SLAVE ADDRESS

REGISTER

2

E PROM

64 X 32

XDEC

LOAD

INC

(6) SCL

(3) A

+COMPARATOR

2

WORD

ADDRESS

COUNTER

(2) A

1

(1) A

0

R/W

YDEC

8

CK

D

OUT

DATA REGISTER

D

OUT

ACK

3838 FHD F01

3838-1.2 7/30/96 T0/C3/D1 SH

Characteristics subject to change without notice

1

X24C02

PIN DESCRIPTIONS

PIN CONFIGURATION

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the

device.

DIP/SOIC/MSOP

V

1

2

3

4

8

7

6

5

CC

A

0

1

WC

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out

of the device. It is an open drain output and may be

X24C02

A

2

SCL

SDA

V

SS

wire-ORed with any number of open drain or open

collector outputs.

3838 FHD F02

An open drain output requires the use of a pull-up

resistor. For selecting typical values, refer to the Guide-

lines for Calculating Typical Values of Bus Pull-Up

Resistors graph.

PIN DESCRIPTIONS

Symbol

Description

Address (A₀, A₁, A₂)

A –A

0

Address Inputs

Serial Data

Serial Clock

Write Control

Ground

2

The address inputs are used to set the least significant

three bits of the seven bit slave address. These inputs

can be static or actively driven. If used statically they must

SDA

SCL

WC

be tied to V_SSor V_CCas appropriate. If actively

driven, they must be driven to V_SSor to V_CC.

V

SS

V

CC

+5V

Write Control (WC)

3838 PGM T01

The Write Control input controls the ability to write to the

device. When WC is LOW (tied to V_SS) the X24C02 will

be enabled to perform write operations. When WC is HIGH

(tied to V_CC) the internal high voltage circuitry will

be disabled and all writes will be disabled.

2

X24C02

DEVICE OPERATION

Clock and Data Conventions

Data states on the SDA line can change only during SCL

LOW. SDA state changes during SCL HIGH are re-

The X24C02 supports a bidirectional bus oriented protocol

The protocol defines any device that sends data onto the

served for indicating start and stop conditions. Refer to

Figures 1 and 2.

bus as a transmitter and the receiving device as the receiver.

The device controlling the transfer is a master and the

device being controlled is the slave. The master will always

initiate data transfers and provide the clock for both transmit

Start Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL is

and receive operations. Therefore, the X24C02 will be

considered a slave in all applications.

HIGH. The X24C02 continuously monitors the SDA and SCL

lines for the start condition and will not respond to

any command until this condition has been met.

Figure 1. Data Validity

SCL

SDA

DATA

CHANGE

DATA STABLE

3838 FHD F06

3

X24C02

The X24C02 will respond with an acknowledge after

recognition of a start condition and its slave address. If

Stop Condition

All communications must be terminated by a stop condition,

which is a LOW to HIGH transition of SDA when SCL is

both the device and a write operation have been

selected, the X24C02 will respond with an acknowledge

after the receipt of each subsequent eight bit word.

HIGH. The stop condition is also used by the X24C02 to

place the device in the standby power mode after a read

sequence. A stop condition can only be issued after the

transmitting device has released the bus.

In the read mode the X24C02 will transmit eight bits of data,

release the SDA line and monitor the line for an

acknowledge. If an acknowledge is detected and no stop

condition is generated by the master, the X24C02

Acknowledge

Acknowledge is a software convention used to indicate

successful data transfer. The transmitting device, either

will continue to transmit data. If an acknowledge is not

detected, the X24C02 will terminate further data trans-

master or slave, will release the bus after transmitting

eight bits. During the ninth clock cycle the receiver will

missions. The master must then issue a stop condition to

return the X24C02 to the standby power mode and

pull the SDA line LOW to acknowledge that it received the

eight bits of data. Refer to Figure 3.

place the device into a known state.

Figure 2. Definition of Start and Stop

SCL

SDA

START BIT

STOP BIT

3838 FHD F07

Figure 3. Acknowledge Response From Receiver

SCL FROM

MASTER

1

8

9

DATA

OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

3838 FHD F08

4

X24C02

DEVICE ADDRESSING

Following the start condition, the X24C02 monitors the

SDA bus comparing the slave address being transmitted

with its slave address (device type and state of A₀, A₁and

Following a start condition the master must output the

address of the slave it is accessing. The most significant

A₂inputs). Upon a correct compare the X24C02 outputs an

four bits of the slave are the device type identifier

(see Figure 4). For the X24C02 this is fixed as 1010[B].

acknowledge on the SDA line. Depending on the state of the

R/W bit, the X24C02 will execute a read or write operation.

Figure 4. Slave Address

WRITE OPERATIONS

DEVICE TYPE

IDENTIFIER

Byte Write

For a write operation, the X24C02 requires a second

address field. This address field is the word address,

1

0

1

0

A2

A1

A0 R/W

comprised of eight bits, providing access to any one of the

256 words of memory. Upon receipt of the word

DEVICE

ADDRESS

address the X24C02 responds with an acknowledge, and

awaits the next eight bits of data, again responding

3838 FHD F09

with an acknowledge. The master then terminates the

transfer by generating a stop condition, at which time the

The next three significant bits address a particular device.

A system could have up to eight X24C02 devices on the

bus (see Figure 10). The eight addresses are defined by the

state of the A₀, A₁and A₂inputs.

X24C02 begins the internal write cycle to the nonvolatile

memory. While the internal write cycle is in progress the

X24C02 inputs are disabled, and the device will not

respond to any requests from the master. Refer to

The last bit of the slave address defines the operation to be

performed. When set to one a read operation is

selected, when set to zero a write operations is selected.

Figure 5 for the address, acknowledge and data transfer

sequence.

Figure 5. Byte Write

S

T

S

T

SLAVE

WORD

ADDRESS

A

BUS ACTIVITY:

ADDRESS

DATA

R

T

MASTER

O

P

SDA LINE

S

P

A

C

K

A

C

K

A

C

K

BUS ACTIVITY:

X24C02

3838 FHD F010

Figure 6. Page Write

S

T

A

R

T

S

T

SLAVE

ADDRESS

WORD

ADDRESS (n)

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+3

O

P

SDA LINE

S

P

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

BUS ACTIVITY:

X24C02

NOTE: In this example n = xxxx 000 (B); x = 1 or 0

3838 FHD F011

5

X24C02

Flow 1. ACK Polling Sequence

Page Write

The X24C02 is capable of a four byte page write operation.

It is initiated in the same manner as the byte write

operation, but instead of terminating the write cycle after

the first data word is transferred, the master can transmit

WRITE OPERATION

COMPLETED

ENTER ACK POLLING

up to three more words. After the receipt of each word, the

X24C02 will respond with an acknowledge.

After the receipt of each word, the two low order address

bits are internally incremented by one. The high order six

ISSUE

START

bits of the address remain constant. If the master should

transmit more than four words prior to generating the stop

condition, the address counter will “roll over” and the

previously written data will be overwritten. As with the byte

ISSUE SLAVE

ADDRESS AND R/W = 0

ISSUE STOP

write operation, all inputs are disabled until completion

of the internal write cycle. Refer to Figure 6 for the address

acknowledge and data transfer sequence.

ACK

RETURNED?

NO

Acknowledge Polling

The disabling of the inputs, during the internal write

operation, can be used to take advantage of the typical

YES

A WRITE?

5 ms write cycle time. Once the stop condition is issued

to indicate the end of the host’s write operation the

NO

X24C02 initiates the internal write cycle. ACK polling

can be initiated immediately. This involves issuing the

YES

start condition followed by the slave address for a write

operation. If the X24C02 is still busy with the write

ISSUE BYTE

ADDRESS

operation no ACK will be returned. If the X24C02 has

completed the write operation an ACK will be returned

ISSUE STOP

PROCEED

and the master can then proceed with the next read or write

operation.

READ OPERATIONS

PROCEED

Read operations are initiated in the same manner as

write operations with the exception that the R/W bit of the

slave address is set to a one. There are three basic read

operations: current address read, random read and

3838 FHD F12

sequential read.

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read

operation, the master must either issue a stop condition

during the ninth cycle or hold SDA HIGH during the ninth

clock cycle and then issue a stop condition.

6

X24C02

Current Address Read

Internally the X24C02 contains an address counter that

maintains the address of the last word accessed,

Random Read

Random read operations allow the master to access any

memory location in a random manner. Prior to issuing

incremented by one. Therefore, if the last access (either

a read or write) was to address n, the next read operation

the slave address with the R/W bit set to one, the master

must first perform a “dummy” write operation. The master

would access data from address n + 1. Upon receipt of the

slave address with the R/W bit set to one, the

ter issues the start condition, and the slave address

followed by the word address it is to read. After the word

X24C02 issues an acknowledge and transmits the eight bit

word during the next eight clock cycles. The master

address acknowledge, the master immediately reissues

the start condition and the slave address with the R/W bit

terminates this transmission by issuing a stop condition,

omitting the ninth clock cycle acknowledge. Refer to

set to one. This will be followed by an acknowledge from

the X24C02 and then by the eight bit word. The master

Figure 7 for the sequence of address, acknowledge and

data transfer.

terminates this transmission by issuing a stop condition,

omitting the ninth clock cycle acknowledge. Refer to

Figure 8 for the address, acknowledge and data transfer

sequence.

Figure 7. Current Address Read

S

T

A

R

T

S

T

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

DATA

O

P

SDA LINE

S

P

A

C

K

BUS ACTIVITY:

X24C02

3838 FHD F13

Figure 8. Random Read

S

T

A

R

T

A

R

T

S

T

SLAVE

ADDRESS

WORD

ADDRESS n

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

DATA n

O

P

SDA LINE

S

P

A

C

K

A

C

K

A

C

K

BUS ACTIVITY:

X24C02

3838 FHD F14

7

X24C02

The data output is sequential, with the data from address

and followed by the data from n + 1. The address counter

Sequential Read

Sequential Read can be initiated as either a current

address read or random access read. The first word is

for read operations increments all address bits, allowing the

entire memory contents to be serially read during

transmitted as with the other modes, however, the

master now responds with an acknowledge, indicating it

one operation. At the end of the address space (address 255),

the counter “rolls over” to address 0 and the

requires additional data. The X24C02 continues to output

data for each acknowledge received. The master

X24C02 continues to output data for each acknowledge

received. Refer to Figure 9 for the address, acknowledge

and data transfer sequence.

terminates this transmission by issuing a stop condition,

omitting the ninth clock cycle acknowledge.

Figure 9. Sequential Read

S

T

SLAVE

ADDRESS

A

C

K

A

C

K

A

C

K

BUS ACTIVITY:

MASTER

O

P

SDA LINE

P

A

C

K

BUS ACTIVITY:

X24C02

DATA n

DATA n+1

DATA n+2

DATA n+x

3838 FHD F15

Figure 10. Typical System Configuration

V

CC

SDA

SCL

MASTER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

TRANSMITTER/

RECEIVER

3838 FHD F16

8

X24C02

ABSOLUTE MAXIMUM RATINGS*

.................. –65°C to +135°C

Storage Temperature ....................... –65°C to +150°C

*COMMENT

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

Temperature Under Bias

Voltage on any Pin with

................................ –1.0V to +7.0V

D.C. Output Current ............................................ 5 mA

This is a stress rating only and the functional operation of

the device at these or any other conditions above those

Respect to V

SS

indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions

Lead Temperature (Soldering, 10 Seconds) ..... 300°C

for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Supply Voltage

Limits

Temperature

Min.

Max.

X24C02

4.5V to 5.5V

3.5V to 5.5V

3V to 5.5V

2.7 to 5.5V

Commercial

Industrial

Military

0°C

70°C

+85°C

+125°C

X24C02-3.5

X24C02-3

X24C02-2.7

–40°C

–55°C

3838 PGM T09

3838 PGM T10

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified).

Limits

Symbol

Parameter

Min.

Max.

Units

Test Conditions

l

Power Supply Current (read)

1

mA

CC1

SCL = V_CCx 0.1/V_CCx 0.9 Levels @ 100

KHz, SDA = Open, All Other

Inputs = GND or V – 0.3V

l

Power Supply Current (write)

Standby Current

2

CC2

CC

(1)

∝A

SCL = SDA = V_CC– 0.3V, All other

Inputs = GND or V_CC, V_CC= 5.5V

SCL = SDA = V_CC– 0.3V, All Other

Inputs = GND or V_CC= 3.3V + 10%

I_SB

50

(2)

I_SB

Standby Current

30

∝A

I

V

= GND to V

IN CC

Input Leakage Current

Output Leakage Current

Input Low Voltage

10

LI

I

LO

V_OUT= GND to V_CC

(2)

V

x 0.3

V_lL

–1.0

V

CC

(2)

V

x 0.7V + 0.5

CC

V_IH

Input High Voltage

CC

V

I

OL

= 3 mA

Output Low Voltage

0.4

OL

3838 PGM T02

CAPACITANCE T_A= 25°C, f = 1 MHz, V_CC= 5V

Symbol

Parameter

Max.

Units

Test Conditions

(3)

V

= 0V

C_I/O

Input/Output Capacitance (SDA)

8

6

pF

I/O

(3)

Input Capacitance (A , A , A , SCL, WC)

2

= 0V

C_IN

0

1

IN

3838 PGM T04

Notes:(1)Must perform a stop command prior to measurement.

(2)V_ILmin. and V_IHmax. are for reference only and are not tested. (3)This

parameter is periodically sampled and not 100% tested.

9

X24C02

A.C. CONDITIONS OF TEST

EQUIVALENT A.C. LOAD CIRCUIT

5.0V

V_CCx 0.1 to V_CCx 0.9

Input Pulse Levels

1533Ο

Input Rise and

Fall Times

10 ns

x 0.5

OUTPUT

Input and Output

Timing Levels

100pF

V

CC

3838 FHD F18

3838 PGM T05

A.C. CHARACTERISTICS (Over recommended operating conditions)

DATA INPUT TIMING

Symbol

Parameter

Min.

Max.

Units

f

SCL Clock Frequency

0

100

KHz

ns

SCL

T

Noise Suppression Time

Constant at SCL, SDA Inputs

I

∝s

t

SCL Low to SDA Data Out Valid

0.3

4.7

3.5

AA

t

Time the Bus Must Be Free Before a

New Transmission Can Start

BUF

∝s

t

Start Condition Hold Time

Clock Low Period

4.0

4.7

4.0

4.7

0

HD:STA

t

LOW

t

Clock High Period

HIGH

t

Start Condition Setup Time

Data In Hold Time

SU:STA

t_HD:DAT

t

Data In Setup Time

250

ns

∝s

SU:DAT

t

R

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

Data Out Hold Time

1

t

F

300

ns

∝s

t_SU:STO

4.7

t

300

ns

3838 PGM T06

DH

Bus Timing

t

HIGH

LOW

R

F

SCL

t

SU:STA

HD:STA

HD:DAT

SU:DAT

SU:STO

SDA IN

t

AA

DH

BUF

SDA OUT

3838 FHD F04

POWER-UP TIMING

Symbol

Parameter

Max.

Units

(4)

t_PUR

Power-up to Read Operation

Power-up to Write Operation

1

5

ms

(4)

t_PUW

3838 PGM T07

Notes:(4) t_PURand t_PUWare the delays required from the time V_CCis stable until the specified operation can be initiated. These parameters are periodically

sampled and not 100% tested.

10

X24C02

WRITE CYCLE LIMITS

(5)

Symbol

Parameter

Write Cycle Time

Min.

Typ.

Max.

Units

(6)

t_WR

5

10

ms

3838 PGM T08

The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.

During the write cycle, the X24C02 bus interface circuits are disabled, SDA is allowed to remain high, and the device does not

respond to its slave address.

Write Cycle Timing

SCL

ACK

SDA

8th BIT

WORD n

t

WR

STOP

CONDITION

START

CONDITION

X24C02

ADDRESS

3838 FHD F05

Notes: (5)Typical values are for T_A= 25 C and nominal supply voltage (5V)

(6) t_WRis the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the

device requires to perform the internal write operation.

SYMBOL TABLE

Guidelines for Calculating Typical Values of

Bus Pull-Up Resistors

WAVEFORM

INPUTS

OUTPUTS

120

Must be

steady

Will be

steady

V

CC MAX

R

=

=1.8KΟ

MIN

I

100

80

OL MIN

t

May change

from Low to

High

Will change

from Low to

High

R

=

MAX

C

BUS

MAX.

RESISTANCE

60

40

20

0

May change

from High to

Low

Will change

from High to

Low

MIN.

RESISTANCE

Changing:

State Not

Known

Don’t Care:

Changes

Allowed

20 40 60 80100120

BUS CAPACITANCE (pF)

0

Center Line

is High

Impedance

N/A

3838 FHD F17

11

X24C02

PACKAGING INFORMATION

8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

0.430 (10.92)

0.360 (9.14)

0.092 (2.34)

DIA. NOM.

0.255 (6.47)

0.245 (6.22)

PIN 1 INDEX

PIN 1

0.300

(7.62) REF.

0.060 (1.52)

0.020 (0.51)

HALF SHOULDER WIDTH ON

ALL END PINS OPTIONAL

0.140 (3.56)

0.130 (3.30)

SEATING

PLANE

0.020 (0.51)

0.015 (0.38)

0.150 (3.81)

0.125 (3.18)

0.062 (1.57)

0.058 (1.47)

0.110 (2.79)

0.090 (2.29)

0.020 (0.51)

0.016 (0.41)

0.325 (8.25)

0.300 (7.62)

0.015 (0.38)

MAX.

0°

15°

TYP. 0.010 (0.25)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

12

X24C02

PACKAGING INFORMATION

8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

0.150 (3.80)

0.158 (4.00)

0.228 (5.80)

0.244 (6.20)

PIN 1 INDEX

PIN 1

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

(4X) 7°

0.053 (1.35)

0.069 (1.75)

0.004 (0.19)

0.010 (0.25)

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

X 45°

0° – 8°

0.0075 (0.19)

0.010 (0.25)

0.027 (0.683)

0.037 (0.937)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESIS IN MILLIMETERS)

13

X24C02

PACKAGING INFORMATION

8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M

0.118 0.002

(3.00 0.05)

0.012 + 0.006 / -0.002

(0.30 + 0.15 / -0.05)

0.0256 (0.65) TYP

R 0.014 (0.36)

0.118 0.002

(3.00 0.05)

0.030 (0.76)

0.0216 (0.55)

7° TYP

0.036 (0.91)

0.032 (0.81)

0.040 0.002

(1.02 0.05)

0.008 (0.20)

0.004 (0.10)

0.150 (3.81)

0.007 (0.18)

0.005 (0.13)

REF.

0.193 (4.90)

REF.

NOTE:

1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)

3003 ILL 01

14

X24C02

NOTES

15

X24C02

ORDERING INFORMATION

V_CCLimits

X24C02

P

T

G

-V

Blank = 4.5V to 5.5V

3.5 = 3.5V to 5.5V

3 = 3.0V to 5.5V

2.7 = 2.7V to 5.5V

Device

G = RoHS Compliant Lead Free packge

Blank = Standard package. Non lead free

Temperature Range

Blank = Commercial = 0°C to +70°C

I = Industrial = –40°C to +85°C

M = Military = –55°C to +125°C

Package

P = 8-Lead Plastic DIP

S8 = 8-Lead SOIC

M = 8-Lead MSOP

Part Mark Convention

X24C02 X G

Blank = 8-Lead SOIC

P = 8-Lead Plastic DIP

S8 = 8-Lead SOIC

M = 8-Lead MSOP

G= RoHS compliant lead free

X

Blank = 4.5V to 5.5V, 0°C to +70°C

I = 4.5V to 5.5V, –40°C to +85°C

M = 4.5V to 5.5V, –55°C to 125°C

B = 3.5V to 5.5V, 0°C to +70°C

C = 3.5V to 5.5V, –40°C to +85°C

D = 3.0V to 5.5V, 0°C to +70°C

E = 3.0V to 5.5V, –40°C to +85°C

F = 2.7V to 5.5V, 0°C to +70°C

G = 2.7V to 5.5V, –40°C to +85°C

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,

statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no

warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without

notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402;

4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents

pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection

and correction, redundancy and back-up features to prevent such an occurence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose

failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the

user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

16


型号：	X24C02
厂家：	IC MICROSYSTEMS
描述：	Serial E2PROM 串行E2PROM 可编程只读存储器
文件：	总16页 (文件大小：294K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

X24C02 [ICMIC]

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