X24012ES [ICMIC]
Serial E2PROM; 串行E2PROM型号: | X24012ES |
厂家: | IC MICROSYSTEMS |
描述: | Serial E2PROM |
文件: | 总14页 (文件大小:271K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TM
This X24012 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
ICmic
128 x 8 Bit
IC MICROSYSTEMS
1K
X24012
Serial E2PROM
FEATURES
DESCRIPTION
The X24012 is a CMOS 1024 bit serial E2PROM,
internally organized as one 128 x 8 bank. The X24012
•2.7 to 5.5V Power Supply
•Low Power CMOS
—Active Current Less Than 1 mA
features a serial interface and software protocol allowing
operation on a simple two wire bus. Three address
—Standby Current Less Than 50 ∝A
•Internally Organized 128 x 8
•Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
inputs allow up to eight devices to share a common two wire
bus.
Xicor E2PROMs are designed and tested for applications
requiring extended endurance. Inherent data retention
•2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
•Four Byte Page Write Operation
—Minimizes Total Write Time Per Byte
•High Reliability
is greater than 100 years. The X24012 is available in eight
pin DIP and SOIC packages.
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
FUNCTIONAL DIAGRAM
(8)
(4)
V
V
CC
SS
H.V. GENERATION
TIMING
START CYCLE
& CONTROL
(5) SDA
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
2
E PROM
32 X 32
XDEC
LOAD
WORD
INC
(6) SCL
(3) A
+COMPARATOR
2
ADDRESS
COUNTER
(2) A
(1) A
1
0
R/W
YDEC
8
CK
D
OUT
PIN
DATA REGISTER
D
OUT
ACK
3847 FHD F01
© Xicor, 1991 Patents Pending
3847-1
Characteristics subject to change without notice
1
X24012
PIN DESCRIPTIONS
PIN CONFIGURATION
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
DIP/SOIC
1
2
3
4
8
7
6
5
A
A
V
0
1
CC
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be
NC
X24012
A
2
SCL
SDA
V
SS
wire-ORed with any number of open drain or open
collector outputs.
3847 FHD F02
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Guide-
lines for Calculating Typical Values of Bus Pull-Up
Resistors graph.
PIN NAMES
Symbol
A –A
Description
Address (A0, A1, A2)
The address inputs are used to set the least significant
three bits of the seven bit slave address. These inputs
Address Inputs
Serial Data
Serial Clock
No Connect
Ground
0
2
SDA
SCL
NC
can be static or actively driven. If used statically they must
be tied to VSS or VCC as appropriate. If actively
driven, they must be driven to VSS or to VCC
.
V
SS
V
CC
+5V
3847 PGM T01
2
X24012
DEVICE OPERATION
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are
The X24012 supports a bidirectional bus oriented proto- col.
The protocol defines any device that sends data
reserved for indicating start and stop conditions. Refer to
Figures 1 and 2.
onto the bus as a transmitter, and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers and provide the
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
clock for both transmit and receive operations. Therefore, the
X24012 will be considered a slave in all
HIGH. The X24012 continuously monitors the SDA and SCL
lines for the start condition and will not respond to
any command until this condition has been met.
applications.
Figure 1. Data Validity
SCL
SDA
DATA
CHANGE
DATA STABLE
3847 FHD F05
Figure 2. Definition of Start and Stop
SCL
SDA
3847 FHD F06
START BIT
STOP BIT
3
X24012
The X24012 will respond with an acknowledge after
recognition of a start condition and its slave address. If
Stop Condition
All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA when SCL
both the device and a write operation have been selected,
the X24012 will respond with an acknowledge
is HIGH. The stop condition is also used by the X24012 to
place the device into the standby power mode after a read
after the receipt of each subsequent eight bit word.
sequence. A stop condition can only be issued after the
transmitting device has released the bus.
In the read mode the X24012 will transmit eight bits of data,
release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the X24012
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device will
will continue to transmit data. If an acknowledge is not
detected, the X24012 will terminate further data trans-
release the bus after transmitting eight bits. During the ninth
clock cycle the receiver will pull the SDA line LOW
missions. The master must then issue a stop condition to
return the X24012 to the standby power mode and
to acknowledge that it received the eight bits of data. Refer
to Figure 3.
place the device into a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
3847 FHD F07
START
ACKNOWLEDGE
4
X24012
DEVICE ADDRESSING
Following the start condition, the X24012 monitors the SDA
bus comparing the slave address being transmit-
Following a start condition the master must output the
address of the slave it is accessing. The most significant
ted with its slave address (device type and state of A0, A1
and A2 inputs). Upon a correct compare the X24012
four bits of the slave address are the device type
identifier (see Figure 4). For the X24012 this is fixed as
1010[B].
outputs an acknowledge on the SDA line. Depending on the
state of the R/W bit, the X24012 will execute a read
or write operation.
Figure 4. Slave Address
WRITE OPERATIONS
DEVICE TYPE
IDENTIFIER
Byte Write
For a write operation, the X24012 requires a second
address field. This address field is the word address,
1
0
1
0
A2
A1
A0 R/W
comprised of eight bits, providing access to any one of the
128 words of memory. Note: the most significant bit
DEVICE
ADDRESS
is a don’t care. Upon receipt of the word address the
X24012 responds with an acknowledge, and awaits the
3847 FHD F08
next eight bits of data, again responding with an ac-
knowledge. The master then terminates the transfer by
The next three significant bits address a particular device.
A system could have up to eight X24012 devices
on the bus (see Figure 10). The eight addresses are defined
by the state of the A0, A1 and A2 inputs.
generating a stop condition, at which time the X24012 begins
the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress the X24012
inputs are disabled, and the device will not respond to
any requests from the master. Refer to Figure 5 for the
address, acknowledge and data transfer sequence.
The last bit of the slave address defines the operation to be
performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Figure 5. Byte Write
S
T
S
T
SLAVE
ADDRESS
WORD
ADDRESS
BUS ACTIVITY:
MASTER
A
R
T
DATA
O
P
SDA LINE
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
X24012
BUS ACTIVITY:
X24012
3847 FHD F09
Figure 6. Page Write
S
T
A
R
T
S
T
SLAVE
ADDRESS
BUS ACTIVITY:
BUS
MASTER
WORD ADDRESS n
DATA n
DATA n–1
DATA n+3
MASTER
O
P
SDA LINE
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
BUS ACTIVITY:
X24012
X24012
3847 FHD F10
NOTE: In this example n = xxxx 0000 (B); x = 1 or 0
5
X24012
Flow 1. ACK Polling Sequence
Page Write
The X24012 is capable of an four byte page write
operation. It is initiated in the same manner as the byte
WRITE OPERATION
COMPLETED
ENTER ACK POLLING
write operation, but instead of terminating the write cycle after
the first data word is transferred, the master can
transmit up to three more words. After the receipt of each word,
the X24012 will respond with an acknowledge.
ISSUE
START
After the receipt of each word, the two low order address bits
are internally incremented by one. The high order
five bits of the address remain constant. If the master should
transmit more than four words prior to generating
ISSUE SLAVE
ADDRESS AND R/W = 0
the stop condition, the address counter will “roll over” and the
previously written data will be overwritten. As
ISSUE STOP
with the byte write operation, all inputs are disabled until
completion of the internal write cycle. Refer to Figure 6
for the address, acknowledge and data transfer sequence.
ACK
RETURNED?
NO
YES
Acknowledge Polling
The disabling of the inputs, during the internal write
operation, can be used to take advantage of the typical
NEXT
OPERATION
A WRITE?
NO
5 ms write cycle time. Once the stop condition is issued to
indicate the end of the host’s write operation the
X24012 initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
YES
ISSUE STOP
PROCEED
condition followed by the slave address for a write
operation. If the X24012 is still busy with the write
ISSUE BYTE
ADDRESS
operation no ACK will be returned. If the X24012 has
completed the write operation an ACK will be returned
and the master can then proceed with the next read or write
operation (See Flow 1).
PROCEED
READ OPERATIONS
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the
3847 FHD F11
slave address is set to a one. There are three basic read
operations: current address read, random read and
sequential read.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
6
X24012
Current Address Read
Internally the X24012 contains an address counter that
maintains the address of the last word accessed,
Random Read
Random read operations allow the master to access any
memory location in a random manner. Prior to issuing
incremented by one. Therefore, if the last access (either a
read or write) was to address n, the next read operation
the slave address with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master
would access data from address n + 1. Upon receipt of the
slave address with R/W set to one, the X24012
issues the start condition, and the slave address followed
by the word address it is to read. After the word
issues an acknowledge and transmits the eight bit word
during the next eight clock cycles. The read operation is
address acknowledge, the master immediately reissues the
start condition and the slave address with the R/W bit
terminated by the master; by not responding with an
acknowledge and by issuing a stop condition. Refer to
set to one. This will be followed by an acknowledge from the
X24012 and then by the eight bit word. The read
Figure 7 for the sequence of address, acknowledge and data
transfer.
operation is terminated by the master; by not responding with
an acknowledge and by issuing a stop condition.
Refer to Figure 8 for the address, acknowledge and data
transfer sequence.
Figure 7. Current Address Read
S
T
S
T
SLAVE
A
BUS ACTIVITY:
ADDRESS
R
T
MASTER
O
P
SDA LINE
S
P
A
C
BUS ACTIVITY:
X24012
DATA
K
3847 FHD F12
Figure 8. Random Read
S
T
A
R
T
S
T
A
R
T
S
T
SLAVE
ADDRESS
WORD
ADDRESS n
SLAVE
ADDRESS
BUS ACTIVITY:
MASTER
O
P
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
X24012
DATA n
3847 FHD F13
7
X24012
The data output is sequential, with the data from address n
followed by the data from n + 1. The address counter
Sequential Read
Sequential Read can be initiated as either a current
address read or random access read. The first word is
for read operations increments all address bits, allowing the
entire memory contents to be serially read during
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating it
one operation. At the end of the address space (address 127),
the counter “rolls over” to address 0 and the
requires additional data. The X24012 continues to out- put
data for each acknowledge received. The read
X24012 continues to output data for each acknowledge
received. Refer to Figure 9 for the address, acknowledge
and data transfer sequence.
operation is terminated by the master, by not responding with
an acknowledge and by issuing a stop condition.
Figure 9. Sequential Read
S
T
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
O
P
SDA LINE
P
A
C
K
BUS ACTIVITY:
X24012
DATA n
DATA n+1
DATA n+2
DATA n+x
3847 FHD F14
Figure 10. Typical System Configuration
V
CC
SDA
SCL
MASTER
SLAVE
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
TRANSMITTER/
RECEIVER
RECEIVER
3847 FHD F15
8
X24012
ABSOLUTE MAXIMUM RATINGS*
.................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
Temperature Under Bias
Voltage on any Pin with
............................... –1.0V to +7V
Respect to V
SS
D.C. Output Current ............................................ 5 mA
This is a stress rating only and the functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Lead Temperature (Soldering,
............................. 300°C
RECOMMENDED OPERATING CONDITIONS
10 Seconds)
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
Industrial
Military
0°C
70°C
+85°C
+125°C
X24012
4.5V to 5.5V
3V to 5.5V
–40°C
–55°C
X24012-3
X24012-2.7
2.7V to 5.5V
3847 PGM T02
3847 PGM T03
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
l
Power Supply Current (Read)
1
mA
CC1
SCL = V x 0.1/V x 0.9 Levels @ 100
CC CC
KHz, SDA = Open, All Other
l
Inputs = GND or VCC – 0.3V
Power Supply Current (Write)
Standby Current
2
CC2
(1)
∝A
∝A
SCL = SDA = VCC – 0.3V, All Other
Inputs = GND or VCC, VCC = 5.5V
SCL = SDA = VCC – 0.3V, All Other
Inputs = GND or VCC, VCC= 3V
ISB
50
(2)
ISB
Standby Current
30
∝A
∝A
I
V
= GND to V
IN CC
Input Leakage Current
Output Leakage Current
Input Low Voltage
10
10
LI
I
LO
VOUT = GND to VCC
(2)
V
V
x 0.3
VlL
–1.0
V
V
V
CC
(2)
V
x 0.7
+ 0.5
CC
VIH
Input High Voltage
CC
V
I
OL
= 3 mA
Output Low Voltage
0.4
OL
3847 PGM T04
CAPACITANCE TA = 25°C, F = 1.0MHZ, VCC = 5V
Symbol
Test
Max.
Units
Conditions
(3)
V
V
= 0V
CI/O
Input/Output Capacitance (SDA)
8
6
pF
pF
I/O
(3)
Input Capacitance (A0, A1, A2, SCL, WC)
= 0V
CIN
IN
3847 PGM T06
Notes:(1) Must perform a stop command prior to measurement. (2)
min. and V
V
IL
IH
max. are for reference only and are not tested. (3)
This parameter is periodically sampled and not 100% tested.
9
X24012
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUIT
5.0V
V
CC
x 0.1 to V x 0.9
CC
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
10ns
1533Ο
V
x 0.5
CC
Output
3847 PGM T07
100pF
3847 FHD F17
A.C. CHARACTERISTICS LIMITS (Over recommended operating conditions unless otherwise specified)
Read & Write Cycle Limits
Symbol
Parameter
Min.
Max.
Units
f
SCL Clock Frequency
0
100
100
3.5
KHz
SCL
T
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
ns
∝s
I
t
AA
0.3
4.7
4.0
4.7
4.0
4.7
0
∝s
∝s
∝s
∝s
∝s
∝s
t
BUF
t
HD:STA
t
Clock Low Period
LOW
t
Clock High Period
HIGH
t
Start Condition Setup Time
Data In Hold Time
SU:STA
tHD:DAT
t
Data In Setup Time
250
ns
∝s
SU:DAT
t
R
SDA and SCL Rise Time
1
t
SDA and SCL Fall Time
300
ns
∝s
F
tSU:STO
Stop Condition Setup Time
Data Out Hold Time
4.7
t
300
ns
3847 PGM T08
DH
POWER-UP TIMING
Symbol
Parameter
Max.
Units
(4)
tPUR
Power-Up to Read Operation
Power-Up to Write Operation
1
5
ms
ms
(4)
tPUW
3847 PGM T09
Bus Timing
t
t
t
R
t
F
HIGH
LOW
SCL
t
t
t
t
t
SU:STA
HD:STA
HD:DAT
SU:DAT
SU:STO
SDA IN
t
AA
t
DH
t
BUF
SDA OUT
3847 FHD F03
Note: (4)t
and t
are the delays required from the time V
is stable until the specified operation can be initiated. These param-
PUR PUW
eters are periodically sampled and not 100% tested.
CC
10
X24012
WRITE CYCLE LIMITS
Symbol
(5)
Typ.
Parameter
Min.
Max.
Units
(6)
tWR
Write Cycle Time
5
10
ms
3847 PGM T10
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
bus interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
erase/program cycle. During the write cycle, the X24012
address.
Write Cycle Timing
SCL
ACK
SDA
8th BIT
WORD n
t
WR
X24012
ADDRESS
STOP
CONDITION
START
CONDITION
3847 FHD F04
Notes:(5) Typical values are for T = 25°C and nominal supply voltage (5V).
A
(6) t
is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device
requires to perform the internal write operation.
WR
SYMBOL TABLE
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
WAVEFORM
INPUTS
OUTPUTS
120
V
Must be
steady
Will be
steady
CC MAX
R
=
=1.8KΟ
MIN
I
100
80
OL MIN
t
R
May change
from Low to
High
Will change
from Low to
High
R
=
MAX
C
BUS
MAX.
RESISTANCE
60
40
20
0
May change
from High to
Low
Will change
from High to
Low
MIN.
RESISTANCE
Changing:
State Not
Known
Don’t Care:
Changes
Allowed
20 40
60 80100120
0
Center Line
is High
Impedance
BUS CAPACITANCE (pF)
N/A
3847 FHD F16
11
X24012
NOTES
12
X24012
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL
IN-LINE PACKAGE TYPE P
8-LEAD PLASTIC SMALL OUTLINE GULL WING
PACKAGE TYPE S
0.430 (10.92)
0.360 (9.14)
0.092 (2.34)
DIA. NOM.
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
0.255 (6.47)
0.245 (6.22)
PIN 1 INDEX
PIN 1 INDEX
PIN 1
PIN 1
0.300
(7.62) REF.
0.060 (1.52)
0.020 (0.51)
0.014 (0.35)
0.019 (0.49)
HALF SHOULDER
WIDTH ON ALL END
PINS OPTIONAL
0.188 (4.78)
0.197 (5.00)
0.140 (3.56)
0.130 (3.30)
SEATING
PLANE
(4X) 7°
0.020 (0.51)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.053 (1.35)
0.069 (1.75)
0.062 (1.57)
0.058 (1.47)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.010 (0.25)
0.020 (0.50)
X 45°
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
MAX.
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0°
15°
0.027 (0.683)
0.037 (0.937)
TYP. 0.010 (0.25)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
13
X24012
ORDERING INFORMATION
P
T G -V
X24012
VCC Limits
Blank = 4.5V to 5.5V
3 = 3.0V to 5.5V
2.7 = 2.7V to 5.5V
Device
G=RoHS Compliant Lead Free package
Blank = Standard package. Non lead free
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
P = 8-Lead Plastic DIP
S = 8-Lead SOIC
Part Mark Convention
X24012
X G
Blank = 8-Lead SOIC
P = 8-Lead Plastic DIP
S = 8-Lead SOIC
G = RoHS compliant lead free
X
Blank = 4.5V to 5.5V, 0°C to +70°C
I = 4.5V to 5.5V, –40°C to +85°C
D = 3.0V to 5.5V, 0°C to +70°C
E = 3.0V to 5.5V, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no
warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without
notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402;
4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents
pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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