HYM7V65831ATFG1-8 [HYNIX]
Synchronous DRAM Module, 8MX64, 6ns, CMOS, DIMM-168;
| 型号： | HYM7V65831ATFG1-8 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Synchronous DRAM Module, 8MX64, 6ns, CMOS, DIMM-168 动态存储器 |
| 文件： | 总14页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PC100 SDRAM Unbuffered DIMM
8Mx64bit F1-Series
based on 8Mx8 SDRAM, LVTTL, 2/4-Banks & 4K/8Krefresh
HYM7V65800A/HYM7V65801A/ HYM7V65830A/ HYM7V65831A
Preliminary
DESCRIPTION
The HYM7V65800A/ 65801A/ 65830A/ 65831A F1-Series are high speed 3.3-Volt synchronous dynamic
RAM Modules composed of eight 8Mx8 bit Synchronous DRAMs in 54-pin TSOPII and 8-pin TSSOP 2K bit
E2PROM on a 168-pin glass-epoxy printed circuit board. One 0.22mF and one 0.0022mF decoupling
capacitors per each SDRAM are mounted on the module.
The HYM7V65800A/ 65801A/ 65830A/ 65831A F1-Series are gold plated socket type Dual In-line
Memory Modules suitable for easy interchange and addition of 64M bytes memory. All addresses, data and
control inputs are latched on the rising edge of the master clock input. The data paths are internally pipelined
to achieve very high bandwidths.
FEATURES
· 1.000” (25.40mm) PCB Height
· Possible to assert random column address
every clock cycle
· 168-Pin Unbuffered DIMM with Double Sided
· One 0.22mF and one 0.0022mF decoupling
capacitors adopted
· Serial Presence Detect with Serial E2PROM
· Meets all the other JEDEC specifications
· Single 3.3V±0.3V power supply
· Interleaved auto refresh mode
· Programmable burst lengths and sequences
- 1,2,4,8,full page for Sequential type
- 1,2,4,8 for Interleave type
· Programmable /CAS latency ; 2,3 clocks
· Support clock suspend/power down mode by
CKE0
· All device pins are LVTTL compatible
· 4096 refresh cycles every 64ms or 8192 refresh
cycles every 128ms
· Data mask function by DQM
· Mode register set programming
· Burst termination command
· Fully synchronous ; all inputs referenced to
positive edge of system clock
· Dual or Quad internal banks with single pulsed
/RAS
· Self refresh provides minimum power, full
internal refresh control
· Auto precharge/precharge all banks by A10 flag
ORDERING INFORMATION
Part No.
Max. Frequency
SDRAM Bank
Ref.
Package Plating
HYM7V65800ATFG1 - 8/10P/10S 125/ 100/ 100 MHz
HYM7V65801ATFG1- 8/10P/10S 125/ 100/ 100 MHz
HYM7V65830ATFG1- 8/10P/10S 125/ 100/ 100 MHz
HYM7V65831ATFG1- 8/10P/10S 125/ 100/ 100 MHz
2 Banks
4 Banks
2 Banks
4 Banks
4K
4K
8K
8K
TSOPII
TSOPII
TSOPII
TSOPII
Gold
Gold
Gold
Gold
BASED COMPONENTS
Module Part No.
Based Comp. Part No.
Module Part No.
Based Comp. Part No.
HYM7V65800ATFG1
HYM7V65801ATFG1
HY57V658010ATC
HY57V658020ATC
HYM7V65830ATFG1
HYM7V65831ATFG1
HY57V648010ATC
HY57V648020ATC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Dec. 1998
Preliminary Rev.B
HYM7V65800A/ HYM7V65801A/ HYM7V65830A/ HYM7V65831A F1-Series
PIN DESCRIPTION
Pin Name
Pin Type
Description
System Clock Input; All other inputs except CKE are registered
to the SDRAM on the rising edge of CLK.
CK0-CK3
INPUT
INPUT
Clock Enable; Controls internal clock signal and when deactiva-
ted, the SDRAM will be either one of the states among power
down, suspend, or self refresh.
CKE0
/S0, /S2
/RAS
INPUT
INPUT
INPUT
Chip select; Functions command mask(NOP).
Row address strobe
Column address strobe
/CAS
Write Enable
/WE
INPUT
INPUT
DQM0-7
Data Input / Output Mask
INPUT/
OUTPUT
Data Input / Output; Include inputs, outputs, or Hi-z state.
DQ0-DQ63
VCC
VSS
SUPPLY
SUPPLY
Power Supplies; 3.3V±0.3V
Ground
INPUT/
SDA
Serial Address and Data Input / Output.
OUTPUT
SCL
INPUT
INPUT
Serial Clock
SA0-SA2
Addresses in Serial E2PROM for Socket Presence.
HYM7V65800A/HYM7V65830A F1-Series ( 2Bank 8Mx8 SDRAM Based )
Pin Name
Pin Type
Description
Bank select address inputs; Select one of dual banks during
both /RAS and /CAS activity.
BA0
INPUT
Address Inputs;
A0-A8; X&Y addresses
A0-A12
INPUT
A10; Precharge flag, A9-A12; X addresses only.
HYM7V65801A/HYM7V65831A F1-Series ( 4Bank 8Mx8 SDRAM Based )
Pin Name
Pin Type
Description
Bank address inputs; Select one of quad banks during both
/RAS and /CAS activity.
BA0, BA1
INPUT
Address Inputs;
A0-A8; X&Y addresses
A0-A11
INPUT
A10; Precharge flag, A9-A11; X addresses only.
Preliminary Rev B
2
HYM7V65800A/ HYM7V65801A/ HYM7V65830A/ HYM7V65831A F1-Series
PIN NAME
#
NAME
#
NAME
#
NAME
#
NAME
1
2
3
4
5
6
7
8
9
Vss
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Vss
85
86
Vss
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
NC
DQ32
DQ33
DQ34
DQ35
Vcc
CKE0
NC
/S2
87
DQM2
DQM3
NC
88
DQM6
DQM7
NC
89
90
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
Vcc
91
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
Vcc
NC
92
NC
NC
93
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NC
94
NC
NC
95
NC
Vss
96
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ16
DQ17
DQ18
DQ19
Vcc
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ48
DQ49
DQ50
DQ51
Vcc
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
DQ20
NC
DQ52
NC
DQ14
DQ15
NC
DQ46
DQ47
NC
NC
NC
NC
NC
NC
Vss
NC
Vss
Vss
DQ21
DQ22
DQ23
Vss
Vss
DQ53
DQ54
DQ55
Vss
NC
NC
NC
NC
Vcc
Vcc
/WE
DQM0
DQM1
/S0
DQ24
DQ25
DQ26
DQ27
Vcc
/CAS
DQM4
DQM5
NC
DQ56
DQ57
DQ58
DQ59
Vcc
NC
/RAS
Vss
Vss
DQ28
DQ29
DQ30
DQ31
Vss
DQ60
DQ61
DQ62
DQ63
Vss
A0
A1
A2
A3
A4
A5
A6
A7
A8
CK2
NC
A9
*CK3
NC
A10(AP)
* BA1
Vcc
BA0
WP
A11
SA0
SDA
SCL
Vcc
Vcc
SA1
Vcc
*CK1
* A12
SA2
CK0
Vcc
Note : 1. BA1 is used for HYM7V65801A/HYM7V65831A F1-Series ( 4 Bank 8Mx8 Based )
2. A12 is used for HYM7V65800A/HYM7V65830A F1-Series ( 2 Bank 8Mx8 Based )
3. CK1 and CK3 are connected with termination R/C ( Refer to the block diagram )
3
Preliminary Rev.B
HYM7V65800A/ HYM7V65801A/ HYM7V65830A/ HYM7V65831A F1-Series
BLOCK DIAGRAM
Note : 1. The serial resistor values of DQs are 10 Ohms.
2. The padding capacitance of termination R/C for CK1/3 is 10pF.
Preliminary Rev B
4
HYM7V65800A/ HYM7V65801A/ HYM7V65830A/ HYM7V65831A F1-Series
I-1 SERIAL PRESENCE DETECT
[ HYM7V65800A/HYM7V65830A F1-Series; 2 Banks ]
BYTE
FUNCTION
DESCRIBED
FUNCTION
-10P
VALUE
NOTE
NUMBER
-8
-10S
-8
-10P -10S
# of Bytes Written into Serial Memory
at Module Manufacturer
BYTE0
128 Bytes
80h
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
256 Bytes
SDRAM
2 Banks; 13
9
08h
04h
0Dh
09h
01h
40h
00h
01h
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
1
1 Bank
64 Bits
-
Data Width of This Assembly (Continued)
Voltage Interface Standard of This Assembly
LVTTL
BYTE9
SDRAM Cycle Time @ /CAS Latency=3
Access Time from Clock @ /CAS Latency=3
DIMM Configuration Type
8ns
6ns
10ns 10ns 80h A0h A0h
BYTE10
BYTE11
6ns
6ns
60h 60h 60h
00h
None
15.625ms
/ Self Refresh Supported
BYTE12
Refresh Rate/Type
80h
BYTE13
BYTE14
x8
08h
00h
Primary SDRAM Width
Error Checking SDRAM Width
None
Minimum Clock Delay Back to Back Random
Column Address
BYTE15
tCCD=1 Latency
01h
BYTE16
BYTE17
Burst Lengths Supported
1,2,4,8,Full Page
2 Banks
8Fh
02h
2
# of Banks on SDRAM Device
BYTE18
BYTE19
BYTE20
CAS # Latency
CS # Latency
Write Latency
/CAS Latency=2,3
/CS Latency=0
/WE Latency=0
06h
01h
01h
Neither Buffered nor
Registered
BYTE21
SDRAM Module Attributes
00h
+/-10% voltage
tolerance, Burst read,
Precharge all, Auto
precharge
BYTE22
SDRAM Module Attributes, General
06h
BYTE23
BYTE24
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
BYTE31
BYTE32
BYTE33
BYTE34
BYTE35
SDRAM Cycle Time @ /CAS Latency=2
Access Time from Clock @ /CAS Latency=2
SDRAM Cycle Time @ /CAS Latency=1
Access Time from Clock @ /CAS Latency=1
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active Delay (tRRD)
Minimum /RAS to /CAS Delay (tRCD)
Minimum /RAS Pulse width (tRAS)
10ns 10ns 12ns A0h A0h C0h
6ns
6ns
6ns
60h 60h 60h
00h 00h 00h
00h 00h 00h
-
-
-
-
-
-
20ns 20ns 20ns 14h 14h 14h
16ns 20ns 20ns 10h 14h 14h
20ns 20ns 20ns 14h 14h 14h
48ns 50ns 50ns 30h 32h 32h
Module Bank Density
64MB
2ns
10h
Command & Address signal input setup time (tAS)
Command & Address signal input hold time (tAH)
Data signal input setup time (tDS)
2ns
1ns
2ns
1ns
2ns
1ns
2ns
1ns
20h 20h 20h
10h 10h 10h
20h 20h 20h
10h 10h 10h
1ns
2ns
Data signal input hold time (tDH)
1ns
5
Preliminary Rev.B
HYM7V65800A/ HYM7V65801A/ HYM7V65830A/ HYM7V65831A F1-Series
I-2 SERIAL PRESENCE DETECT
[ HYM7V65800A/HYM7V65830A F1-Series; 2 Banks: Continued ]
BYTE
FUNCTION
FUNCTION
-10P
VALUE
NOTE
NUMBER
DESCRIBED
-8
-10S
-8
-10P -10S
BYTE36
-61
Superset Information(May be used in the future)
-
00h
12h
BYTE62
BYTE63
BYTE64
SPD Revision
Intel SPD 1.2A
4, 5
Checksum for Byte 0-62
Manufacturer JEDEC ID Code
D6h FCh 1Ch
ADh
Hyundai JEDEC ID
Unused
BYTE65
-71
…..Manufacturer JEDEC ID Code
FFh
HEI (Korea)
01h
BYTE72
Manufacturing Location
HEA (United States)
02h
HEU (Europe)
03h
BYTE73
BYTE74
BYTE75
BYTE76
BYTE77
Manufacturer’ s Part Number (SDRAM)
Manufacturer’ s Part Number (3.3V)
7
37h
6
6
6
6
6
V
56h
Manufacturer’ s Part Number (Data Width)
…..Manufacturer’ s Part Number (Data Width)
Manufacturer’ s Part Number (Memory Depth)
6
36h
5
35h
8
38h
0 (4K Ref.)
3 (8K Ref.)
30h
33h
BYTE78
Manufacturer’ s Part Number (Refresh)
6
BYTE79
BYTE80
BYTE81
BYTE82
BYTE83
BYTE84
BYTE85
BYTE86
BYTE87
BYTE88
Manufacturer’ s Part Number (2 Internal Banks)
Manufacturer’ s Part Number (Generation)
Manufacturer’ s Part Number (TSOPII Mounted)
Manufacturer’ s Part Number (x8 Unbuffered)
Manufacturer’ s Part Number (Plating Type : Gold)
Manufacturer’ s Part Number (Different PCB)
Manufacturer’ s Part Number (Hyphen)
0
A
T
F
G
1
-
30h
6
6
6
6
6
6
6
6
6
6
41h
54h
46h
47h
31h
2Dh
Manufacturer’ s Part Number (Min. Cycle Time)
8
1
0
P
1
0
S
38h 31h 31h
20h 30h 30h
20h 50h 53h
…..Manufacturer’ s Part Number (Min. Cycle Time) Blank
…..Manufacturer’ s Part Number (Min. Cycle Time) Blank
BYTE89
-90
Manufacturer’ s Part Number
Blanks
20h
6
BYTE91
BYTE92
BYTE93
BYTE94
Revision Code for Components
…..Revision Code for PCB
Manufacturing Date
Process Code
Process Code
Work Week
Year
-
-
-
-
3, 6
3, 6
3, 5
3, 5
…..Manufacturing Date
BYTE95
-98
Assembly Serial Number
-
-
3
BYTE99
-125
Manufacturer Specific Data (May be used in the
Future)
None
00h
BYTE126 System Frequency support
100MHz
Note 7
64h
4
4
BYTE127 Intel Specification details for 100MHz Support
A7h A7h A5h
BYTE128
-256
Unused storage locations
-
00h
Note: 1. The bank address is excluded.
3. Not fixed but dependent.
5. BCD adopted.
2. In interleaved type, the burst lengths supported is 1, 2, 4, 8.
4. Refer to Intel SPD 1.2A specifications.
6. ASCII adopted.
7. CLK0,2 connected to the DIMM, TBD junction temp, CL=2(3) support and supporting Intel defined
Concurrent Auto Precharge.
Preliminary Rev B
6
HYM7V65800A/ HYM7V65801A/ HYM7V65830A/ HYM7V65831A F1-Series
II-1 SERIAL PRESENCE DETECT
[ HYM7V65801A/HYM7V65831A F1-Series; 4 Banks ]
BYTE
FUNCTION
DESCRIBED
FUNCTION
-10P
VALUE
NOTE
NUMBER
-8
-10S
-8
-10P -10S
# of Bytes Written into Serial Memory
at Module Manufacturer
BYTE0
128 Bytes
80h
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
256 Bytes
SDRAM
4 Banks; 12
9
08h
04h
0Ch
09h
01h
40h
00h
01h
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
1
1 Bank
64 Bits
-
Data Width of This Assembly (Continued)
Voltage Interface Standard of This Assembly
LVTTL
BYTE9
SDRAM Cycle Time @ /CAS Latency=3
Access Time from Clock @ /CAS Latency=3
DIMM Configuration Type
8ns
6ns
10ns 10ns 80h A0h A0h
BYTE10
BYTE11
6ns
6ns
60h 60h 60h
00h
None
15.625ms
/ Self Refresh Supported
BYTE12
Refresh Rate/Type
80h
BYTE13
BYTE14
x8
08h
00h
Primary SDRAM Width
Error Checking SDRAM Width
None
Minimum Clock Delay Back to Back Random
Column Address
BYTE15
tCCD=1 Latency
01h
BYTE16
BYTE17
Burst Lengths Supported
1,2,4,8,Full Page
4 Banks
8Fh
04h
2
# of Banks on SDRAM Device
BYTE18
BYTE19
BYTE20
CAS # Latency
CS # Latency
Write Latency
/CAS Latency=2,3
/CS Latency=0
/WE Latency=0
06h
01h
01h
Neither Buffered nor
Registered
BYTE21
SDRAM Module Attributes
00h
+/-10% voltage
tolerance, Burst read,
Precharge all, Auto
precharge
BYTE22
SDRAM Module Attributes, General
06h
BYTE23
BYTE24
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
BYTE31
BYTE32
BYTE33
BYTE34
BYTE35
SDRAM Cycle Time @ /CAS Latency=2
Access Time from Clock @ /CAS Latency=2
SDRAM Cycle Time @ /CAS Latency=1
Access Time from Clock @ /CAS Latency=1
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active Delay (tRRD)
Minimum /RAS to /CAS Delay (tRCD)
Minimum /RAS Pulse width (tRAS)
10ns 10ns 12ns A0h A0h C0h
6ns
6ns
6ns
60h 60h 60h
00h 00h 00h
00h 00h 00h
-
-
-
-
-
-
20ns 20ns 20ns 14h 14h 14h
16ns 20ns 20ns 10h 14h 14h
20ns 20ns 20ns 14h 14h 14h
48ns 50ns 50ns 30h 32h 32h
Module Bank Density
64MB
2ns
10h
Command & Address signal input setup time (tAS)
Command & Address signal input hold time (tAH)
Data signal input setup time (tDS)
2ns
1ns
2ns
1ns
2ns
1ns
2ns
1ns
20h 20h 20h
10h 10h 10h
20h 20h 20h
10h 10h 10h
1ns
2ns
Data signal input hold time (tDH)
1ns
7
Preliminary Rev.B
HYM7V65800A/ HYM7V65801A/ HYM7V65830A/ HYM7V65831A F1-Series
II-2 SERIAL PRESENCE DETECT
[ HYM7V65801A/HYM7V65831A F1-Series; 4 Banks: Continued ]
BYTE
FUNCTION
FUNCTION
-10P
VALUE
NOTE
NUMBER
DESCRIBED
-8
-10S
-8
-10P -10S
BYTE36
-61
Superset Information(May be used in the future)
-
00h
12h
BYTE62
BYTE63
BYTE64
SPD Revision
Intel SPD 1.2A
4, 5
Checksum for Byte 0-62
Manufacturer JEDEC ID Code
D7h FDh 1Dh
ADh
Hyundai JEDEC ID
Unused
BYTE65
-71
…..Manufacturer JEDEC ID Code
FFh
HEI (Korea)
01h
BYTE72
Manufacturing Location
HEA (United States)
02h
HEU (Europe)
03h
BYTE73
BYTE74
BYTE75
BYTE76
BYTE77
Manufacturer’ s Part Number (SDRAM)
Manufacturer’ s Part Number (3.3V)
7
37h
6
6
6
6
6
V
56h
Manufacturer’ s Part Number (Data Width)
…..Manufacturer’ s Part Number (Data Width)
Manufacturer’ s Part Number (Memory Depth)
6
36h
5
35h
8
38h
0 (4K Ref.)
3 (8K Ref.)
30h
33h
BYTE78
Manufacturer’ s Part Number (Refresh)
6
BYTE79
BYTE80
BYTE81
BYTE82
BYTE83
BYTE84
BYTE85
BYTE86
BYTE87
BYTE88
Manufacturer’ s Part Number (4 Internal Banks)
Manufacturer’ s Part Number (Generation)
Manufacturer’ s Part Number (TSOPII Mounted)
Manufacturer’ s Part Number (x8 Unbuffered)
Manufacturer’ s Part Number (Plating Type : Gold)
Manufacturer’ s Part Number (Different PCB)
Manufacturer’ s Part Number (Hyphen)
1
A
T
F
G
1
-
31h
6
6
6
6
6
6
6
6
6
6
41h
54h
46h
47h
31h
2Dh
Manufacturer’ s Part Number (Min. Cycle Time)
8
1
0
P
1
0
S
38h 31h 31h
20h 30h 30h
20h 50h 53h
…..Manufacturer’ s Part Number (Min. Cycle Time) Blank
…..Manufacturer’ s Part Number (Min. Cycle Time) Blank
BYTE89
-90
Manufacturer’ s Part Number
Blanks
20h
6
BYTE91
BYTE92
BYTE93
BYTE94
Revision Code for Components
…..Revision Code for PCB
Manufacturing Date
Process Code
Process Code
Work Week
Year
-
-
-
-
3, 6
3, 6
3, 5
3, 5
…..Manufacturing Date
BYTE95
-98
Assembly Serial Number
-
-
3
BYTE99
-125
Manufacturer Specific Data (May be used in the
Future)
None
00h
BYTE126 System Frequency support
100MHz
Note 7
64h
4
4
BYTE127 Intel Specification details for 100MHz Support
A7h A7h A5h
BYTE128
-256
Unused storage locations
-
00h
Note: 1. The bank address is excluded.
3. Not fixed but dependent.
5. BCD adopted.
2. In interleaved type, the burst lengths supported is 1, 2, 4, 8.
4. Refer to Intel SPD 1.2A specifications.
6. ASCII adopted.
7. CLK0,2 connected to the DIMM, TBD junction temp, CL=2(3) support and supporting Intel defined
Concurrent Auto Precharge.
Preliminary Rev B
8
HYM7V65800A/ HYM7V65801A/ HYM7V65830A/ HYM7V65831A F1-Series
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rating
0 to 70
-55 to 125
-1.0 to 4.6
-1.0 to 4.6
50
Unit
TA
Ambient Temperature
°C
°C
TSTG
Storage Temperature
VIN, VOUT
VCC
Voltage on Any Pin relative to VSS
Voltage on VCC relative to VSS
Short Circuit Output Current
Power Dissipation
V
V
IOS
MA
W
PD
8
TSOLDER
Soldering Temperature×Time
260×10
°C×sec
Note : Operation at above Absolute Maximum Ratings can adversely affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS*
(TA=0°C to 70°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Note
VCC, VCCQ
Vss
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
3.0
0
3.3
0
3.6
0
V
V
V
V
VIH
2.0
-0.3
3.0
0
VCC + 0.4
0.8
1
2
VIL
Note : 1. VIH(max)=4.6V AC for pulse width £10ns acceptable.
2. VIL(min)=-1.5V AC for pulse width £10ns acceptable.
RECOMMENDED AC OPERATING CONDITIONS* (TA=0°C to 70°C, VCC=3.3V±10%, VSS=0V)
Symbol
Parameter
Value
Unit Note
VIH / VIL
Vtrip
AC Input High/Low Level Voltage
2.4/0.4
1.4
1
V
V
Input Timing Measurement Reference Level Voltage
Input Rise/Fall Time
Tr / tf
Voutref
CL
ns
V
Output Reference Voltage
1.4
50
Output Load Capacitance for Access Time Measurement
pF
Note : Output load to measure access times is equivalent to two TTL gates and one capacitance(50pF).
Note : *
DC Output Load Circuit
AC Output Load Circuit
Rt=250
Output
Vtt=1.4V
Output
50pF
50pF
9
Preliminary Rev.B
HYM7V65800A/ HYM7V65801A/ HYM7V65830A/ HYM7V65831A F1-Series
DC CHARACTERISTICS(I)
(TA=0°C to 70°C, VCC=3.3V±10%, VSS=0V)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
VI=0 to 3.6V, All other
pins not undertest=0V
ILI
Input Leakage Current
-8
8
mA
DOUT is disabled,
VO=0 to 3.6V
IOL=4.0mA
ILO
Output Leakage Current
-1
1
mA
VOL
VOH
Output Low Voltage
Output High Voltage
-
0.4
-
V
V
IOH=-4.0mA
2.4
DC CHARACTERISTICS(II)
(TA=0°C to 70°C, VCC=3.3V±10%, VSS=0V)
Parameter
Symbol
Test Condition
Max. Unit Note
Burst Length=1, One bank active
tRAS³ tRAS(min),
-8
920
Operating current
ICC1
-10P 800
-10S 800
16
mA
mA
1
tRP³ tRP(min), IO=0mA
CKE£VIL(max), tCK=15ns
CKE£VIL(max), tCK= ¥
ICC2P
Precharge Standby Current
in Power Down Mode
ICC2PS
16
CKE³ VIL(min), /CS³ VIL(min), tCK=15ns
Input signals are chaged one time during
30ns. All other pins³ VDD-0.2V or £0.2V
ICC2N
120
Precharge Standby Current
in Non Power Down Mode
mA
mA
CKE³ VIL(min), tCK= ¥
Input signals are stable
CKE£VIL(max), tCK=15ns
CKE£VIL(max), tCK= ¥
ICC2NS
120
Active Standby Current
in Power Down Mode
ICC3P
40
40
ICC3PS
CKE³ VIL(min), /CS³ VIL(min), tCK=15ns
Input signals are chaged one time during
30ns. All other pins³ VDD-0.2V or £0.2V
CKE³ VIL(min), tCK= ¥
ICC3N
280
Active Standby Current
in Non Power Down Mode
mA
mA
ICC3NS
280
880
Input signals are stable
-8
CL=3 -10P 800
-10S 8000
tCK³ tCK(min),
Burst Mode Operating
Current
ICC4
1
2
tRAS³ tRAS(min), IO=0mA
All banks active
720
-8
CL=2 -10P 560
-10S 560
Auto Refresh Current
ICC5
ICC6
1600 mA
16 mA
tRRC³ tRRC(min), All banks active
CKE£0.2V
Self Refresh Current
Note :
1. ICC1 and ICC4 depend on output loading and cycle rates. Specified values are measured with the output
open.
2. Minimum of tRRC(Refresh /RAS cycle time)=96ns
Preliminary Rev B
10
HYM7V65800A/ HYM7V65801A/ HYM7V65830A/ HYM7V65831A F1-Series
AC CHARACTERISTICS I
-8
-10P
Max
-10S
Parameter
Symbol
CL=3 tCK3
CL=2 tCK2
Unit Note
Min
8
Max
Min
10
10
3
Min
Max
10
10
3
3
-
ns
ns
System clock cycle time
1000
1000
1000
10
3
Clock high pulse width
Clock low pulse width
tCHW
tCLW
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
2
2
2
1
1
1
1
1
1
1
1
2
3
3
CL=3 tAC3
CL=2 tAC2
tOH
-
6
6
-
-
6
6
-
6
6
-
Access time from clock
-
-
-
Data-Out hold time
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
CKE setup time
3
3
3
2
1
2
1
2
1
2
1
1
3
3
tDS
2
-
2
-
-
tDH
1
-
1
-
-
tAS
2
-
2
-
-
tAH
1
-
1
-
-
tCKS
2
-
2
-
-
CKE hold time
tCKH
1
-
1
-
-
Command setup time
Command hold time
tCS
2
-
2
-
-
tCH
1
-
1
-
-
CLK to data output in low Z-time
tOLZ
1
-
1
-
-
CL=3 tOHZ3
CL=2 tOHZ2
3
6
6
3
6
6
6
6
CLK to data output in
high Z-time
3
3
Note : 1. Assumed input rise and fall time (tR / tF) is 1ns. If tR & tF is longer than 1ns, transient time
compensation should be considered. i.e., [(tR+tF)/2-1]ns should be added to the parameter.
2. If clock rising time is longer than 1ns, (tR/2-0.5)ns should be added to the parameter.
AC CHARACTERISTICS II
-8
-10P
Max
-10S
Parameter
Symbol
Unit Note
Min
70
70
20
48
20
16
1
Max
Min
70
70
20
50
20
20
1
Min
Max
Operation
Auto Refresh
tRC
-
-
70
70
20
50
20
20
1
-
ns
/RAS cycle time
tRRC
tRCD
tRAS
tRP
-
-
-
ns
/RAS to /CAS delay
/RAS active time
-
-
-
ns
100K
100K
100K
ns
/RAS precharge time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
/RAS to /RAS bank active delay
/CAS to /CAS delay
tRRD
tCCD
tWTL
tDPL
tDAL
tDQZ
tDQM
tMRD
ns
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Write command to data-in delay
Data-in to precharge command
Data-in to active command
DQM to data-out Hi-Z
0
0
0
1
1
1
4
4
4
2
2
2
DQM to data-in mask
0
0
0
MRS to new command
2
2
2
Precharge to data
output Hi-Z
CL=3 tPROZ3
CL=2 tPROZ2
tPDE
3
3
3
2
2
2
Power down exit time
Self refresh exit time
1
1
1
tSRE
1
1
1
CLK
1
4K
64
128
64
128
64
128
Refresh time
tREF
ms
8K
Note : 1. A new command can be given tRRC after self refresh exit.
11
Preliminary Rev.B
HYM7V65800A/ HYM7V65801A/ HYM7V65830A/ HYM7V65831A F1-Series
CAPACITANCE
(TA=25°C, f=1MHz)
Symbol
Parameter
Pin
Typ. Max. Unit
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Output Capacitance
A0-A11/12, BA0/BA1
/RAS, /CAS, /WE
/S0, /S2
-
-
-
-
60
60
35
40
55
20
15
pF
pF
pF
pF
pF
pF
pF
CK0, CK2
CKE0
DQM0-DQM7
DQ0-DQ63
-
-
MODULE OPERATING OPTION TABLE
HYM7V65800/801/830/831ATFG1-8
/CAS Latency
3CLKs
tRCD
tRAS
tRC
tRP
tAC
6ns
6ns
6ns
6ns
tOH
125MHz
100MHz
83MHz
66MHz
3CLKs
2CLKs
2CLKs
2CLKs
6CLKs
5CLKs
4CLKs
4CLKs
9CLKs
7CLKs
6CLKs
5CLKs
3CLKs
2CLKs
2CLKs
2CLKs
3ns
3ns
3ns
3ns
2CLKs
2CLKs
2CLKs
HYM7V65800/801/830/831ATFG1-10P
/CAS Latency
2CLKs
tRCD
tRAS
tRC
tRP
tAC
6ns
6ns
6ns
6ns
tOH
3ns
3ns
3ns
3ns
100MHz
83MHz
66MHz
50MHz
2CLKs
2CLKs
2CLKs
1CLKs
5CLKs
5CLKs
4CLKs
3CLKs
7CLKs
6CLKs
5CLKs
4CLKs
2CLKs
2CLKs
2CLKs
1CLKs
2CLKs
2CLKs
2CLKs
HYM7V65800/801/830/831ATFG1-10S
/CAS Latency
3CLKs
tRCD
tRAS
tRC
tRP
tAC
6ns
6ns
6ns
6ns
tOH
3ns
3ns
3ns
3ns
100MHz
83MHz
66MHz
50MHz
2CLKs
2CLKs
2CLKs
1CLKs
5CLKs
5CLKs
4CLKs
3CLKs
7CLKs
6CLKs
5CLKs
4CLKs
2CLKs
2CLKs
2CLKs
1CLKs
2CLKs
2CLKs
2CLKs
Preliminary Rev B
12
HYM7V65800A/ HYM7V65801A/ HYM7V65830A/ HYM7V65831A F1-Series
COMMAND TRUTH TABLE
A10/
AP
Command
CKEn-1 CKEn /CS /RAS /CAS /WE DQM ADDR
BA
Note
Mode Register
set
H
X
L
L
L
L
X
OP code
1, 2
H
L
L
X
H
L
X
H
H
X
H
H
No Operation
Bank Active
Read
H
H
X
X
X
X
X
RA
L
V
V
4
H
H
H
X
X
L
L
H
H
L
L
L
H
L
X
X
X
CA
CA
X
Read with
Autoprecharge
H
L
4, 5
4
Write
V
Write with
H
H
L
4, 5
Autoprecharge
Precharge All
baknks
Precharge
selected bank
Burst Stop
DQM
X
V
X
X
L
L
H
H
L
L
H
H
H
H
H
X
L
X
V
X
X
X
X
X
6
7
3
3
Auto Refresh
H
L
L
L
H
L
H
L
H
L
L
L
H
H
X
H
X
H
X
H
X
Entry
L
Self
X
H
X
H
X
H
X
X
H
X
H
X
H
X
X
X
X
Refresh
Exit
L
H
L
H
L
X
X
X
3
Entry
Exit
Precharge
Power
down
H
H
Entry
Exit
H
L
L
X
X
Clock
Suspend
H
X
(V=Valid, X=Don’ t care, H=Logic High, L=Logic Low)
Note: 1. OP code : Operand Code. ADDR, A10/AP, BA : Program keys (@MRS)
2.MRS can be issued only at both banks precharge state.
A new command can be issued after 2CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM
The automatical precharge without row precharge command is meant by “ Auto” .
Auto/self refresh can be issued only at both banks precharge state.
4. BA : Bank select address.
If “ Low” at read, write, row active and precharge, Bank A is selected.
If “ High” at read, write, row active and precharge, Bank B is selected.
If A10/AP is “ High” at row precharge, BA is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (write DQM
Latency is 0), but makes Hi-Z state the data-out of 2CLK cycles after. (Read DQM latency is 2)
13
Preliminary Rev.B
HYM7V65800A/ HYM7V65801A/ HYM7V65830A/ HYM7V65831A F1-Series
PACKAGE DIMENSION
Preliminary Rev B
14
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