HY62UF16406C-SM55I [HYNIX]
Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, MICRO, BGA-48;
| 型号： | HY62UF16406C-SM55I |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, MICRO, BGA-48 静态存储器 内存集成电路 |
| 文件： | 总11页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY62UF16406C Series
256Kx16bit full CMOS SRAM
Document Title
256K x16 bit 2.7 ~ 3.3V Super Low Power FCMOS Slow SRAM
Revision History
Revision No History
Draft Date
Remark
Final
00
01
02
Initial Draft
Dec.20.2000
Mar.23.2001
Jun.07.2001
Changed Logo
Changed Isb1 values
Final
Final
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev.02 / Jun.01
Hynix Semiconductor
HY62UF16406C Series
DESCRIPTION
FEATURES
The HY62UF16406C is a high speed, super low
power and 4Mbit full CMOS SRAM organized as
256K words by 16bits. The HY62UF16406C uses
high performance full CMOS process technology
and is designed for high speed and low power
circuit technology. It is particularly well-suited for
the high density low power system application.
This device has a data retention mode that
guarantees data to remain valid at a minimum
power supply voltage of 1.2V.
·
·
·
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup
-. 1.2V(min) data retention
Standard pin configuration
-. 48-ball uBGA
·
Standby
Temperature
Current(uA)
Voltage
Operation
Current/Icc(mA)
Product No.
Speed (ns)
55/70
(V)
(°C)
LL
15
SL
6
HY62UF16406C-I 2.7~3.3
Note 1. I : Industrial
5
-40~85
2. Current value is max.
PIN CONNECTION
BLOCK DIAGRAM
1
2
3
4
5
6
ROW
DECODER
I/O1
I/O8
I/O9
I/O16
/LB /OE A0
A1
A2 CS2
/CS1
A
IO9
A3
A5
A4
A6
IO1
/UB
B
C
D
E
F
IO10
Vss
IO2 IO3
IO4 Vcc
IO11
IO12
IO13
IO14
A17 A7
MEMORY ARRAY
256K x 16
Vcc
NC A16 IO5 Vss
A14 A15 IO6 IO7
IO15
A17
IO16 NC A12 A13 /WE IO8
G
H
NC
A9
A10 A11 NC
A8
/CS1
CS2
/OE
/LB
FBGA
/UB
/WE
PIN DESCRIPTION
Pin Name
/CS1, CS2 Chip Select
/WE
/OE
/LB
Pin Function
Pin Name
I/O1~I/O16
A0~A17
Vcc
Pin Function
Data Inputs/Outputs
Address Inputs
Power (2.7~3.3V)
Ground
Write Enable
Output Enable
Lower Byte Control (I/O1~I/O8)
Vss
/UB
Upper Byte Control (I/O9~I/O16) NC
No Connection
Rev.02 / Jun.01
2
HY62UF16406C Series
ORDERING INFORMATION
Part No.
HY62UF16406C-DM(I)
HY62UF16406C-SM(I)
Speed
55/70
55/70
Power
LL-part
SL-part
Temp.
Package
uBGA
uBGA
I
I
Note 1. I : Industrial
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VIN, VOUT
Vcc
TA
TSTG
Parameter
Input/Output Voltage
Power Supply
Operating Temperature
Storage Temperature
Power Dissipation
Rating
Unit
V
V
°C
°C
W
Remark
-0.3 to 3.6
-0.3 to 4.6
-40 to 85
-55 to 150
1.0
HY62UF16406C-I
PD
TSOLDER
Ball Soldering Temperature & Time
260 · 10
°C·sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
I/O Pin
/CS1 CS2
/WE
/OE /LB /UB
Mode
Deselected
Output Disabled
Read
Power
Standby
Active
I/O1~I/O8
I/O9~I/O16
H
X
X
X
L
X
X
X
X
X
X
X
X
X
H
L
X
L
X
X
H
X
L
H
L
L
Hi-Z
Hi-Z
L
L
H
H
H
H
H
L
Hi-Z
Hi-Z
DOUT
Hi-Z
DOUT
DIN
Hi-Z
DIN
Hi-Z
DOUT
DOUT
Hi-Z
DIN
Active
H
L
L
H
L
X
L
H
L
H
L
L
Write
Active
DIN
Note:
1. H=VIH, L=VIL, X=don't care (VIL or VIH)
2. /UB, /LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When /LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8.
When /UB is LOW, data is written or read to the upper byte, I/O 9 -I/O 16.
Rev.02 / Jun.01
2
HY62UF16406C Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
VIH
VIL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
2.7
0
Typ
3.0
0
-
-
Max.
3.3
0
Vcc+0.3
0.6
Unit
V
V
V
V
2.2
-0.31.
Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns
2. Undershoot is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
TA = -40°C to 85°C
Sym
ILI
Parameter
Test Condition
Vss < VIN < Vcc
Min Typ1.
Max
1
Unit
uA
Input Leakage Current
-1
-
Vss < VOUT < Vcc,
/CS1 = VIH or CS2=VIL or
/OE = VIH or /WE = VIL or
/UB = VIH , /LB = VIH
ILO
Icc
Output Leakage Current
-1
-
1
uA
/CS1 = VIL, CS2=VIH,
Operating Power Supply Current
5
mA
mA
VIN = VIH or VIL, II/O = 0mA
/CS1 = VIL, CS2 = VIH,
VIN = VIH or VIL, Cycle Time = Min,
100% Duty, II/O = 0mA
/CS1 < 0.2V, CS2 > Vcc-0.2V,
VIN < 0.2V or VIN > Vcc-0.2V,
Cycle Time = 1us,
50
ICC1
Average Operating Current
mA
5
100% Duty, II/O = 0mA
/CS1 = VIH or CS2 = VIL or
/UB, /LB = VIH
ISB
Standby Current (TTL Input)
Standby Current (CMOS Input)
0.5
6
mA
uA
VIN = VIH or VIL
/CS1 > Vcc - 0.2V or
CS2 < Vss + 0.2V or
/UB, /LB > Vcc - 0.2V
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
IOL = 2.1mA
SL
LL
0.2
0.2
ISB1
15
uA
VOL
VOH
Output Low
Output High
-
-
-
0.4
-
V
V
IOH = -1.0mA
2.4
Note
1. Typical values are at Vcc = 3.0V TA = 25°C
2. Typical values are not 100% tested
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol
CIN
COUT
Parameter
Condition
VIN = 0V
VI/O = 0V
Max.
8
10
Unit
pF
pF
Input Capacitance (Add, /CS1,CS2,/LB,/UB, /WE, /OE)
Output Capacitance (I/O)
Note : These parameters are sampled and not 100% tested
Rev.02 / Jun.01
3
HY62UF16406C Series
AC CHARACTERISTICS
TA = -40°C to 85°C, unless otherwise specified
55ns
70ns
#
Symbol
Parameter
Unit
Min. Max. Min.
Max.
READ CYCLE
1
2
3
4
5
6
7
8
9
tRC
tAA
tACS
tOE
tBA
tCLZ
tOLZ
tBLZ
tCHZ
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
/LB, /UB Access Time
Chip Select to Output in Low Z
Output Enable to Output in Low Z
/LB, /UB Enable to Output in Low Z
Chip Deselection to Output in High Z
Out Disable to Output in High Z
/LB, /UB Disable to Output in High Z
Output Hold from Address Change
55
-
-
-
-
10
5
10
0
0
0
-
70
-
-
-
-
10
5
10
0
0
0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
55
30
55
-
-
-
30
30
30
-
70
70
35
70
-
-
-
30
30
30
-
10 tOHZ
11 tBHZ
12 tOH
10
10
WRITE CYCLE
13 tWC
14 tCW
15 tAW
16 tBW
17 tAS
18 tWP
19 tWR
20 tWHZ
21 tDW
22 tDH
23 tOW
Write Cycle Time
55
50
50
50
0
45
0
0
-
-
-
-
-
-
-
20
-
-
70
60
60
60
0
50
0
0
-
-
-
-
-
-
-
20
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
/LB, /UB Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
25
0
5
30
0
5
-
-
AC TEST CONDITIONS
TA = -40°C to 85°C, unless otherwise specified
Parameter
Value
Input Pulse Level
Input Rise and Fall Time
0.4V to 2.2V
5ns
Input and Output Timing Reference Level
1.5V
Output Load tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW
Others
CL = 5pF + 1TTL Load
CL = 30pF + 1TTL Load
AC TEST LOADS
VTM=2.8V
1029 Ohm
DOUT
CL(1)
1728 Ohm
Note 1. Including jig and scope capacitance:
Rev.02 / Jun.01
4
HY62UF16406C Series
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
tRC
ADDR
/CS1
tAA
tACS
tOH
CS2
tCHZ(3)
tBA
/UB ,/ LB
/OE
tBHZ(3)
tOE
tOLZ(3)
tBLZ(3)
tOHZ(3)
tCLZ(3)
Data
High-Z
Out
Data Valid
READ CYCLE 2(Note 1,2,4)
tRC
ADDR
tAA
tOH
tOH
Data
Out
Previous Data
Data Valid
READ CYCLE 3(Note 1,2,4)
/CS1
/UB, /LB
CS2
tACS
tCLZ(3)
tCHZ(3)
Data
Out
Data Valid
Notes:
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and
CS2 are in active status.
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active. /UB and /LB in high for the standby, low for active
Rev.02 / Jun.01
5
HY62UF16406C Series
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
tWC
tCW
ADDR
tWR(2)
/CS1
CS2
tAW
tBW
/UB,/LB
tWP
/WE
tAS
tDW
Data Valid
tDH
High-Z
Data In
tWHZ(3,7)
tOW
(5)
(6)
Data
Out
WRITE CYCLE 2 (Note 1,4,8) (/CS1, CS2 Controlled)
tWC
ADDR
/CS1
CS2
tCW
tAS
tWR(2)
tAW
tBW
/UB,/LB
/WE
tWP
tDW
Data Valid
tDH
High-Z
Data In
High-Z
Data
Out
Rev.02 / Jun.01
6
HY62UF16406C Series
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1, a high CS2 and a low /UB and/or /LB .
2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high or CS2 going low to the
end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS1, /LB and /UB low transition and CS2 high transition occur simultaneously with the /WE low
transition or after the /WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured + 200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active.
/UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
TA= -40°C to 85°C
Symbol
Parameter
Test Condition
/CS1 > Vcc - 0.2V or
Min
Typ1. Max
Unit
V
CS2 < Vss + 0.2V or
/UB, /LB > Vcc - 0.2V,
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
VDR
Vcc for Data Retention
1.2
-
3.3
Vcc=1.5V,
uA
uA
/CS1 > Vcc - 0.2V or
CS2 < Vss + 0.2V or
/UB, /LB > Vcc - 0.2V
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
SL
-
-
0.1
0.1
3
Iccdr
Data Retention Current
LL
10
Chip Deselect to Data
Retention Time
Operating Recovery Time
tCDR
tR
0
-
-
-
-
ns
ns
See Data Retention Timing Diagram
tRC
Notes:
1. Typical values are under the condition of TA = 25°C.
2. Typical value are sampled and not 100% tested
Rev.02 / Jun.01
7
HY62UF16406C Series
DATA RETENTION TIMING DIAGRAM 1
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
VIH
VDR
CS1>VCC-0.2V
/CS1
VSS
DATA RETENTION TIMING DIAGRAM 2
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
CS2
VDR
0.4V
CS2<0.2V
VSS
Rev.02 / Jun.01
8
HY62UF16406C Series
PACKAGE INFORMATION
48ball Micro Ball Grid Array Package(M)
BOTTOM VIEW
TOP VIEW
B
A
A1 CORNER
INDEX AREA
6
5
4
3
2
1
A
A
B
C
D
C
C1
E
3.0 X 5.0 MIN
FLAT AREA
F
G
H
C1/2
B1/2
B1
SIDE VIEW
5
E1
E2
C
E
SEATING PLANE
4
A
r
3
D(DIAMETER)
Note
Symbol
Min.
-
-
6.7
-
8.3
0.3
0.85
0.6
0.2
-
Typ.
0.75
3.75
6.8
5.25
8.4
0.35
0.9
0.65
0.25
-
Max.
-
-
6.9
-
8.5
0.4
0.95
0.7
0.3
0.08
A
B
B1
C
C1
D
E
E1
E2
r
1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994.
2. ALL DIMENSIONS ARE MILLIMETERS.
3. DIMENSION “D” IS MEASURED AT THE MAXIMUM SOLDER
BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE
CROWN OF THE SOLDER BALLS.
5. THIS IS A CONTROLLING DIMENSION.
Rev.02 / Jun.01
9
HY62UF16406C Series
MARKING INFORMATION
Package
Marking Example
H
Y
U
F
6
4
y
0
6
C
c
x
s
x
s
x
t
w
K
w
O
p
uBGA
x
x
R
Index
• HYUF6406C
• c
: Part Name
: Power Consumption
- D
- S
: Low Low Power
: Super Low Power
• ss
: Speed
- 55
: 55ns
: 70ns
- 70
• t
: Temperature
- I
: Industrial ( -40 ~ 85 °C )
• y
: Year (ex : 0 = year 2000, 1= year 2001)
: Work Week ( ex : 12 = work week 12 )
: Process Code
• ww
• p
• xxxxx
• KOR
: Lot No.
: Origin Country
Note
- Capital Letter
- Small Letter
: Fixed Item
: Non-fixed Item
Rev.02 / Jun.01
10
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