HY57V281620HCLT-H_技术文档

HY57V281620HC(L)T

4 Banks x 2M x 16bits Synchronous DRAM

DESCRIPTION

The Hynix HY57V281620HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications

which require large memory density and high bandwidth. HY57V281620HC(L)T is organized as 4banks of 2,097,152x16

HY57V281620HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are syn-

chronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and

output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated

by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of

read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst

read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm

of pin pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by UDQM or LDQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V281620HCT-6

HY57V281620HCT-7

HY57V281620HCT-K

HY57V281620HCT-H

HY57V281620HCT-8

HY57V281620HCT-P

HY57V281620HCT-S

HY57V281620HCLT-6

HY57V281620HCLT-7

HY57V281620HCLT-K

HY57V281620HCLT-H

HY57V281620HCLT-8

HY57V281620HCLT-P

HY57V281620HCLT-S

166MHz

143MHz

133MHz

125MHz

100MHz

166MHz

143MHz

133MHz

125MHz

100MHz

Normal

4Banks x 2Mbits

x16

LVTTL

400mil 54pin TSOP II

Low power

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of

circuits described. No patent licenses are implied.

Rev. 0.2/Aug. 01

HY57V281620HC(L)T

PIN CONFIGURATION

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

1

2

3

4

5

6

7

8

9

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

DQ5 10

DQ6 11

VSSQ

12

DQ7 13

VDD 14

LDQM 15

/WE 16

/CAS 17

/RAS 18

/CS 19

BA0 20

BA1 21

A10/AP 22

A0 23

54pin TSOP II

400mil x 875mil

0.8mm pin pitch

NC

UDQM

CLK

CKE

NC

A11

A9

A8

A7

A6

A5

A1 24

A2 25

A3 26

VDD 27

A4

VSS

PIN DESCRIPTION

PIN NAME

DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM on the

rising edge of CLK

CLK

Clock

Controls internal clock signal and when deactivated, the SDRAM will be one

of the states among power down, suspend or self refresh

CKE

CS

Clock Enable

Chip Select

Enables or disables all inputs except CLK, CKE, UDQM and LDQM

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

BA0, BA1

A0 ~ A11

Bank Address

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8

Auto-precharge flag : A10

Address

Row Address Strobe, Col-

umn Address Strobe, Write

Enable

RAS, CAS and WE define the operation

Refer function truth table for details

RAS, CAS, WE

UDQM, LDQM

DQ0 ~ DQ15

VDD/VSS

Data Input/Output Mask

Data Input/Output

Controls output buffers in read mode and masks input data in write mode

Multiplexed data input / output pin

Power Supply/Ground

Data Output Power/Ground

No Connection

Power supply for internal circuits and input buffers

Power supply for output buffers

VDDQ/VSSQ

NC

No connection

Rev. 0.2/Aug. 01

3

HY57V281620HC(L)T

FUNCTIONAL BLOCK DIAGRAM

2Mbit x 4banks x 16 I/O Synchronous DRAM

Self refresh logic

& timer

Internal Row

counter

2Mx16 Bank 3

2Mx16 Bank 2

CLK

CKE

CS

Row

Pre

Decoders

Row active

2Mx16 Bank 1

2Mx16 Bank 0

DQ0

DQ1

RAS

CAS

WE

Memory

Cell

Array

refresh

Column

Active

Column

Pre

UDQM

LDQM

Decoders

DQ14

DQ15

Y decoders

Column Add

Counter

Bank Select

A0

A1

Address

Registers

Burst

Counter

A11

BA0

BA1

CAS Latency

Pipe Line Control

Mode Registers

Data Out Control

Rev. 0.2/Aug. 01

4

HY57V281620HC(L)T

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

Unit

Ambient Temperature

TA

0 ~ 70

-55 ~ 125

-1.0 ~ 4.6

50

°C

Storage Temperature

TSTG

°C

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Short Circuit Output Current

Power Dissipation

VIN, VOUT

V

VDD, VDDQ

IOS

V

mA

PD

1

W

Soldering Temperature × Time

TSOLDER

260 × 10

°C × Sec

Note : Operation at above absolute maximum rating can adversely affect device reliability.

DC OPERATING CONDITION (TA=0 to 70°C)

Parameter

Symbol

Min

Typ

Max

Unit

Note

Power Supply Voltage

Input High voltage

Input Low voltage

VDD, VDDQ

VIH

3.0

2.0

3.3

3.0

0

3.6

VDDQ + 0.3

0.8

V

1

1,2

1,3

VIL

-0.3

Note :

1.All voltages are referenced to VSS = 0V

2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.

3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.

AC OPERATING TEST CONDITION(TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)

Parameter

Symbol

Value

Unit

Note

AC Input High / Low Level Voltage

VIH / VIL

Vtrip

2.4/0.4

1.4

1

V

Input Timing Measurement Reference Level Voltage

Input Rise / Fall Time

tR / tF

Voutref

CL

ns

V

Output Timing Measurement Reference Level Voltage

Output Load Capacitance for Access Time Measurement

1.4

50

pF

1

Note :

1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output

load circuit

Rev. 0.2/Aug. 01

5

HY57V281620HC(L)T

CAPACITANCE (TA=25°C, f=1MHz)

-6/K/H

-8/P/S

Unit

Parameter

Symbol

Min

Max

Min

Max

Input capacitance

CLK

CI1

CI2

2.5

3.5

3.8

2.5

4.0

5.0

pF

A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS,

WE, UDQM, LDQM

Data input / output capacitance

DQ0 ~ DQ15

CI/O

4.0

6.5

4.0

6.5

pF

OUTPUT LOAD CIRCUIT

Vtt=1.4V

RT=250 W

Output

50pF

DC Output Load Circuit

AC Output Load Circuit

DC CHARACTERISTICS I(TA=0 to 70°C, VDD=3.3±0.3V)

Parameter

Symbol

Min.

Max

Unit

Note

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

ILI

-1

1

uA

V

1

2

ILO

VOH

VOL

2.4

-

IOH = -2mA

IOL = +2mA

0.4

V

Note :

1.VIN = 0 to 3.6V, All other pins are not tested under V IN =0V

2.DOUT is disabled, VOUT=0 to 3.6

Rev. 0.2/Aug. 01

6

HY57V281620HC(L)T

DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)

Speed

Parameter

Symbol

Test Condition

Unit Note

-6

-7

-K

-H

-8

-P

-S

Burst length=1, One bank active

tRC ³ tRC(min), IOL=0mA

130

120

110

mA

1

Operating Current

IDD1

IDD2P

CKE £ VIL(max), tCK = 15ns

2

1

Precharge Standby Current

in Power Down Mode

IDD2PS CKE £ VIL(max), tCK = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCK = 15ns

IDD2N

Input signals are changed one time during

30ns. All other pins ³ VDD-0.2V or £ 0.2V

15

Precharge Standby Current

in Non Power Down Mode

mA

CKE ³ VIH(min), tCK = ¥

Input signals are stable.

IDD2NS

IDD3P

CKE £ VIL(max), tCK = 15ns

5

Active Standby Current

in Power Down Mode

IDD3PS CKE £ VIL(max), tCK = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCK = 15ns

30

20

IDD3N

Input signals are changed one time during

30ns. All other pins ³ VDD-0.2V or £ 0.2V

Active Standby Current

mA

in Non Power Down Mode

CKE ³ VIH(min), tCK = ¥

Input signals are stable.

IDD3NS

150

160

240

140

240

130

140

220

130

140

220

2

130

140

200

110

120

200

110

120

200

CL=3

Burst Mode Operating

Current

tCK ³ tCK(min), IOL=0mA

1

IDD4

IDD5

IDD6

All banks active

CL=2

mA

uA

2

3

4

Auto Refresh Current

Self Refresh Current

tRRC ³ tRRC(min), All banks active

CKE £ 0.2V

800

Note :

1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open

2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3.HY57V281620HCT-6/K/H/8/P/S

4.HY57V281620HCLT-6/K/H/8/P/S

Rev. 0.2/Aug. 01

7

HY57V281620HC(L)T

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

-6

-7

-K

-H

-8

-P

-S

Parameter

Symbol

Unit Note

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

CAS Latency = 3 tCK3

CAS Latency = 2 tCK2

6

7

1000

7.5

1000

7.5

8

10

ns

System Clock

Cycle Time

1000

10

2.5

-

10

2.5

-

7.5

2.5

-

10

2.5

-

10

3

-

10

3

-

12

3

-

Clock High Pulse Width

Clock Low Pulse Width

tCHW

tCLW

-

ns

1

-

CAS Latency = 3 tAC3

CAS Latency = 2 tAC2

tOH

5.4

6

-

6

-

6

-

Access Time

From Clock

2

-

6

-

6

-

5.4

-

6

-

Data-Out Hold Time

2.7

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

1

-

2.7

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

1

-

2.7

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

1

-

2.7

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

1

3

2

1

2

1

2

1

2

1

3

2

1

2

1

2

1

2

1

3

2

1

2

1

2

1

2

1

3

Data-Input Setup Time

Data-Input Hold Time

Address Setup Time

Address Hold Time

tDS

-

1

tDH

-

tAS

-

tAH

-

CKE Setup Time

tCKS

tCKH

tCS

-

CKE Hold Time

-

Command Setup Time

Command Hold Time

CLK to Data Output in Low-Z Time

-

tCH

-

tOLZ

-

CAS Latency = 3 tOHZ3

CAS Latency = 2 tOHZ2

2.7

5.4

2.7

5.4

2.7

5.4

2.7

3

5.4

6

CLK to Data

Output in High-Z

Time

Note :

1.Assume tR / tF (input rise and fall time ) is 1ns

If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter

2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v

If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter

Rev. 0.2/Aug. 01

8

HY57V281620HC(L)T

AC CHARACTERISTICS II

-6

-7

-K

-H

-8

-P

-S

Parameter

Symbol

Unit Note

Min

60

18

42

18

12

1

Max

Min

60

65

20

45

20

14

1

Max

Min

60

65

15

45

15

1

Max

Min

65

20

45

20

15

1

Max

Min

68

20

48

20

16

1

Max

Min

70

20

50

20

1

Max

Min

70

20

50

20

1

Max

Operation

Auto Refresh

tRC

-

ns

RAS Cycle Time

tRRC

tRCD

tRAS

tRP

-

RAS to CAS Delay

RAS Active Time

-

ns

100K

ns

RAS Precharge Time

-

ns

RAS to RAS Bank Active Delay

CAS to CAS Delay

tRRD

tCCD

tWTL

tDPL

tDAL

tDQZ

tDQM

tMRD

ns

-

CLK

Write Command to Data-In Delay

Data-In to Precharge Command

Data-In to Active Command

DQM to Data-Out Hi-Z

0

-

0

-

0

-

0

-

0

-

0

-

0

-

2

-

2

-

2

-

2

-

1

-

1

-

1

-

5

-

5

-

4

-

5

-

4

-

3

-

3

-

2

-

2

-

2

-

2

-

2

-

2

-

2

-

DQM to Data-In Mask

0

-

0

-

0

-

0

-

0

-

0

-

0

-

MRS to New Command

2

-

2

-

2

-

2

-

2

-

2

-

2

-

CAS Latency = 3 tPROZ3

CAS Latency = 2 tPROZ2

3

-

3

-

3

-

3

-

3

-

3

-

3

-

Precharge to Data

Output Hi-Z

2

-

2

-

2

-

2

-

2

-

2

-

2

-

Power Down Exit Time

Self Refresh Exit Time

Refresh Time

tPDE

tSRE

tREF

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

CLK

ms

1

-

64

-

64

-

64

-

64

-

64

-

64

-

64

Note :

1. A new command can be given tRRC after self refresh exit

Rev. 0.2/Aug. 01

9

HY57V281620HC(L)T

IBIS SPECIFICATION

IOH Characteristics (Pull-up)

66MHz and 100MHz Pull-up

100MHz

(Min)

100MHz

(Max)

66MHz

(Min)

Voltage

0

0.5

1

1.5

2

2.5

3

3.5

(V)

3.45

3.3

3.0

2.6

2.4

2.0

1.8

1.65

1.5

1.4

1.0

0

I(mA)

-2.4

I(mA)

0

-100

-200

-300

-400

-500

-600

-27.3

-74.1

-129.2

-153.3

-197

0

-0.7

-7.5

-21.1

-34.1

-58.7

-67.3

-73

-13.3

-27.5

-35.5

-41.1

-47.9

-52.4

-72.5

-93

-226.2

-248

Voltage (V)

-77.9

-80.8

-88.6

-93

-269.7

-284.3

-344.5

-502.4

I

OH Min (100MHz)

OH Min (66MHz)

I

OH Max (66 /100MHz)

IOL Characteristics (Pull-down)

66MHz and 100MHz Pull-down

100MHz

(Min)

100MHz

(Max)

66MHz

(Min)

Voltage

250

200

150

100

50

(V)

0

I(mA)

0

I(mA)

0

I(mA)

0

0.4

0.65

0.85

1.0

1.4

1.5

1.65

1.8

1.95

3.0

3.45

27.5

41.8

51.6

58.0

70.7

72.9

75.4

77.0

77.6

80.3

81.4

70.2

17.7

26.9

33.3

37.6

46.6

48.0

49.5

50.7

51.5

54.2

54.9

107.5

133.8

151.2

187.7

194.4

202.5

208.6

212.0

219.6

222.6

0

0.5

1

1.5

2

2.5

3

3.5

Voltage (V)

I

OL Min(100MHz)

OL Min (66MHz)

I

IOL Max (100MHz)

Rev. 0.2/Aug. 01

10

HY57V281620HC(L)T

VDD Clamp @ CLK, CKE, CS, DQM & DQ

Minimum V DD clamp current

(Referenced to VDD)

VDD (V)

I(mA)

0.0

0.2

0.4

0.6

0.7

0.8

0.9

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

0.0

2 0

1 5

1 0

5

0.0

0.23

1.34

3.02

5.06

7.35

9.83

12.48

15.30

18.31

0

1

2

3

V o lta g e

I(m A)

Minimum VSS clamp current

VSS Clamp @ CLK, CKE, CS, DQM & DQ

VSS(V)

I (mA)

- 3

- 2 .5

- 2

- 1 .5

- 1

- 0 .5

0

-2.6

-2.4

-2.2

-2.0

-1.8

-1.6

-1.4

-1.2

-1.0

-0.9

-0.8

-0.7

-0.6

-0.4

-0.2

0.0

-57.23

-45.77

-38.26

-31.22

-24.58

-18.37

-12.56

-7.57

-3.37

-1.75

-0.58

-0.05

0.0

0

-10

-20

-30

-40

-50

-60

V o lta g e

0.0

I(m A)

0.0

Rev. 0.2/Aug. 01

11

HY57V281620HC(L)T

DEVICE OPERATING OPTION TABLE

HY57V281620HC(L)T-6

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

166MHz(6ns)

143MHz(7ns)

133MHz(7.5ns)

3CLKs

2CLKs

3CLKs

7CLKs

6CLKs

10CLKs

9CLKs

3CLKs

5.4ns

2.7ns

HY57V281620HC(L)T-7

CAS Latency

3CLKs

tRCD

tRAS

tRC

tRP

tAC

tOH

143MHz(7ns)

133MHz(7.5ns)

125MHz(8ns)

3CLKs

7CLKs

10CLKs

3CLKs

5.4ns

6ns

2.7ns

3ns

3CLKs

HY57V281620HC(L)T-K

CAS Latency

2CLKs

tRCD

tRAS

tRC

tRP

tAC

tOH

133MHz(7.5ns)

125MHz(8ns)

100MHz(10ns)

2CLKs

3CLKs

2CLKs

6CLKs

5CLKs

8CLKs

9CLKs

7CLKs

2CLKs

3CLKs

2CLKs

5.4ns

6ns

2.7ns

3ns

3CLKs

2CLKs

6ns

3ns

HY57V281620HC(L)T-H

CAS Latency

3CLKs

tRCD

tRAS

tRC

tRP

tAC

tOH

133MHz(7.5ns)

125MHz(8ns)

100MHz(10ns)

3CLKs

2CLKs

6CLKs

5CLKs

9CLKs

7CLKs

3CLKs

2CLKs

5.4ns

6ns

2.7ns

3ns

3CLKs

2CLKs

6ns

3ns

HY57V281620HC(L)T-8

CAS Latency

3CLKs

tRCD

tRAS

tRC

tRP

tAC

tOH

125MHz(8ns)

100MHz(10ns)

83MHz(12ns)

3CLKs

2CLKs

6CLKs

5CLKs

4CLKs

9CLKs

7CLKs

6CLKs

3CLKs

2CLKs

6ns

3ns

2CLKs

HY57V281620HC(L)T-P

CAS Latency

2CLKs

tRCD

tRAS

tRC

tRP

tAC

tOH

100MHz(10ns)

83MHz(12ns)

66MHz(15ns)

2CLKs

5CLKs

4CLKs

7CLKs

6CLKs

2CLKs

6ns

3ns

2CLKs

HY57V281620HC(L)T-S

CAS Latency

3CLKs

tRCD

tRAS

tRC

tRP

tAC

tOH

100MHz(10ns)

83MHz(12ns)

66MHz(15ns)

2CLKs

5CLKs

4CLKs

7CLKs

6CLKs

2CLKs

6ns

3ns

2CLKs

Rev. 0.2/Aug. 01

12

HY57V281620HC(L)T

COMMAND TRUTH TABLE

A10/

AP

ADDR

Command

CKEn-1

CKEn

CS

RAS

CAS

WE

DQM

BA

Note

Mode Register Set

H

X

L

H

L

X

H

L

X

H

L

X

H

X

OP code

No Operation

X

Bank Active

L

RA

V

Read

L

H

L

H

L

CA

X

Read with Autoprecharge

Write

H

L

H

X

V

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Burst Stop

H

X

V

X

L

H

L

H

X

L

X

V

X

DQM

X

Auto Refresh

H

X

L

H

L

Burst-Read-Single-

WRITE

A9 Pin High

(Other Pins OP code)

MRS

Mode

H

L

X

Entry

L

H

L

X

H

X

H

X

H

X

V

L

X

H

X

H

X

H

X

V

H

X

H

X

H

X

H

X

V

1

X

Self Refresh

Exit

L

H

L

H

L

X

H

L

Entry

Precharge

power down

X

H

L

Exit

H

L

Entry

Clock

Suspend

H

L

X

Exit

H

X

Note :

1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high

2. X = Don¢t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,

Opcode = Operand Code, NOP = No Operation

3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.

Rev. 0.2/Aug. 01

13

HY57V281620HC(L)T

PACKAGE INFORMATION

400mil 54pin Thin Small Outline Package

UNIT : mm(inch)

11.938(0.4700)

11.735(0.4620)

22.327(0.8790)

22.149(0.8720)

10.262(0.4040)

10.058(0.3960)

0.150(0.0059)

0.050(0.0020)

1.194(0.0470)

0.991(0.0390)

5deg

0deg

0.210(0.0083)

0.120(0.0047)

0.597(0.0235)

0.406(0.0160)

0.400(0.016)

0.80(0.0315)BSC

0.300(0.012)

Rev. 0.2/Aug. 01

14


型号：	HY57V281620HCLT-H
厂家：	HYNIX SEMICONDUCTOR
描述：	4 Banks x 2M x 16bits Synchronous DRAM 4银行x 2米X 16位同步DRAM 动态存储器
文件：	总13页 (文件大小：97K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HY57V281620HCLT-H [HYNIX]

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