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H57V1262GFR-50C [HYNIX]

Synchronous DRAM, 8MX16, 4.5ns, CMOS, PBGA54, 8 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, FBGA-54;
H57V1262GFR-50C
型号： H57V1262GFR-50C
厂家： HYNIX SEMICONDUCTOR    HYNIX SEMICONDUCTOR
描述：

Synchronous DRAM, 8MX16, 4.5ns, CMOS, PBGA54, 8 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, FBGA-54

时钟 动态存储器 内存集成电路
文件： 总12页 (文件大小：250K)
中文：  中文翻译
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128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O  
Document Title  
4Bank x 2M x 16bits Synchronous DRAM  
Revision History  
Revision No.  
History  
Initial Draft  
Release  
Draft Date  
Jul. 2009  
Remark  
0.1  
1.0  
Preliminary  
Aug. 2009  
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for  
use of circuits described. No patent licenses are implied.  
Rev. 1.0 / Aug. 2009  
1
Synchronous DRAM Memory 128Mbit (8Mx16bit)  
H57V1262GFR Series  
DESCRIPTION  
The Hynix H57V1262GFR series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applica-  
tions which require wide data I/O and high bandwidth. H57V1262GFR series is organized as 4banks of 2,097,152 x 16.  
H57V1262GFR is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs  
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high  
bandwidth. All input and output voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write  
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-  
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or  
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-  
stricted by a '2N' rule)  
FEATURES  
•
•
•
•
Voltage: VDD and VDDQ 3.3V supply voltage  
All device pins are compatible with LVTTL interface  
54 Ball FBGA (Lead or Lead Free Package)  
•
Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 or full page for Sequential Burst  
- 1, 2, 4 or 8 for Interleave Burst  
All inputs and outputs referenced to positive edge of  
system clock  
•
•
•
Programmable CAS Latency; 2, 3 Clocks  
Burst Read Single Write operation  
•
•
•
•
Data mask function by UDQM, LDQM  
Internal four banks operation  
Auto refresh and self refresh  
4096 Refresh cycles / 64ms  
Operation temperature  
HY5V26F(L)F(P)-XX Series: 0 ~ 70oC  
HY5V26F(L)F(P)-X(I) Series: -40 ~ 85oC  
● This product is in compliance with the directive pertaining of RoHS.  
ORDERING INFORMATION  
Part No.  
Clock Frequency  
Organization  
Interface  
Package  
H57V1262GFR-50X  
H57V1262GFR-60X  
H57V1262GFR-70X  
H57V1262GFR-75X  
200MHz  
166MHz  
143MHz  
133MHz  
4Banks x 2Mbits  
x16  
LVTTL  
54 Ball FBGA  
1. H57V1262GFR-XXC Series: Normal power, Commercial Temp.(0oC to 70oC)  
2. H57V1262GFR-XXI Series: Normal power, Industrial Temp. (-40oC to 85oC)  
3. H57V1262GFR-XXL Series: Low power, Commercial Temp.(0oC to 70oC)  
4. H57V1262GFR-XXJ Series: Low power, Industrial Temp. (-40oC to 85oC)  
Rev. 1.0 / Aug. 2009  
2
Synchronous DRAM Memory 128Mbit (8Mx16bit)  
H57V1262GFR Series  
BALL CONFIGURATION  
3
8
2
1
9
7
A
B
C
D
54 Ball  
FBGA  
E
F
0.8mm  
Ball Pitch  
G
H
J
<Bottom View>  
1
2
3
7
8
9
VSS  
DQ15  
DQ13  
DQ11  
DQ9  
NC  
VSSQ  
VDDQ  
VSSQ  
VDDQ  
VSSQ  
VDD  
/CAS  
BA0  
DQ0  
DQ2  
DQ4  
DQ6  
VDD  
A
B
C
D
E
F
DQ14  
DQ12  
DQ10  
DQ8  
UDQM  
NC  
VDDQ  
VSSQ  
VDDQ  
VSS  
CKE  
A9  
DQ1  
DQ3  
DQ5  
DQ7  
/WE  
/CS  
LDQM  
/RAS  
BA1  
A1  
CLK  
A11  
A7  
G
H
J
A8  
A6  
A0  
A10  
VSS  
A5  
A4  
A3  
A2  
VDD  
< Top View >  
Rev. 1.0 / Aug. 2009  
3
Synchronous DRAM Memory 128Mbit (8Mx16bit)  
H57V1262GFR Series  
FUNCTIONAL BLOCK DIAGRAM  
2Mbit x 4banks x 16 I/O Synchronous DRAM  
Internal Row  
Counter  
Self refresh  
logic & timer  
2Mx16 BANK 3  
2Mx16 BANK 2  
2Mx16 BANK 1  
2Mx16 BANK 0  
CLK  
Row  
Pre  
Decoder  
Row Active  
CKE  
CS  
DQ0  
RAS  
CAS  
Refresh  
Memory  
Cell  
Array  
Column  
Active  
Column  
Pre  
WE  
Decoder  
DQ15  
U/LDQM  
Y-Decoder  
Column Add  
Counter  
Bank Select  
Address  
Register  
A0  
A1  
Burst  
Counter  
Pipe Line  
Control  
A11  
BA1  
BA0  
CAS Latency  
Mode Register  
Data Out Control  
Rev. 1.0 / Aug. 2009  
4
Synchronous DRAM Memory 128Mbit (8Mx16bit)  
H57V1262GFR Series  
BASIC FUNCTIONAL DESCRIPTION  
Mode Register  
BA1  
0
BA0  
0
A11  
0
A10  
0
A9  
A8  
0
A7  
0
A6  
A5  
A4  
A3  
BT  
A2  
A1  
A0  
OP Code  
CAS Latency  
Burst Length  
OP Code  
A9  
0
Write Mode  
Burst Read and Burst Write  
Burst Read and Single Write  
Burst Type  
1
A3  
0
1
Burst Type  
Sequential  
Interleave  
CAS Latency  
Burst Length  
A6  
0
A5  
0
A4  
0
CAS Latency  
R e s e r v e d  
1
Burst Length  
A2  
A1  
A0  
A3 = 0  
A3=1  
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
1
2
4
8
0
1
0
2
0
1
1
3
4
1
0
0
Reserved  
R e s e r v e d  
R e s e r v e d  
Reserved  
8
1
0
1
Reserved  
Reserved  
Reserved  
Full Page  
Reserved  
Reserved  
Reserved  
Reserved  
1
1
0
1
1
1
Rev. 1.0 / Aug. 2009  
5
Synchronous DRAM Memory 128Mbit (8Mx16bit)  
H57V1262GFR Series  
ABSOLUTE MAXIMUM RATING  
Parameter  
Symbol  
Rating  
Unit  
oC  
oC  
oC  
V
Note  
0 ~ 70oC  
1
2
Ambient Temperature  
TA  
-40 ~ 85oC  
-55 ~ 125  
-1.0 ~ 4.6  
-1.0 ~ 4.6  
50  
Storage Temperature  
TSTG  
VIN, VOUT  
VDD, VDDQ  
IOS  
Voltage on Any Pin relative to VSS  
Voltage on VDD relative to VSS  
Short Circuit Output Current  
Power Dissipation  
V
mA  
W
PD  
1
oC / Sec  
Soldering Temperature / Time  
TSOLDER  
260 / 10  
Notes:  
1. Commercial (0 ~ 70oC)  
2. Industrial (-40 ~ 85oC)  
DC OPERATING CONDITION  
Parameter  
Power Supply Voltage  
Input High Voltage  
Input Low Voltage  
Symbol  
VDD, VDDQ  
VIH  
Typ  
Max  
3.6  
Unit  
Note  
1
Min.  
3.0  
3.3  
3.0  
-
V
V
V
2.0  
VDDQ + 0.3  
0.8  
1, 2  
1, 3  
VIL  
-0.3  
Notes:  
1. All voltages are referenced to VSS = 0V  
2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.  
3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration  
AC OPERATING TEST CONDITION (VDD=3.3±0.3V, VSS=0V)  
Parameter  
Symbol  
VIH / VIL  
Vtrip  
Value  
2.4 / 0.4  
1.4  
Unit  
Note  
AC Input High / Low Level Voltage  
V
V
Input Timing Measurement Reference Level Voltage  
Input Rise / Fall Time  
tR / tF  
Voutref  
CL  
1
ns  
V
Output Timing Measurement Reference Level Voltage  
Output Load Capacitance for Access Time Measurement  
1.4  
50  
pF  
1
Vtt = 1.4V  
Vtt = 1.4V  
Note: 1.  
Ω
RT = 500  
Ω
RT = 50  
50pF  
Output  
Output  
Z0 = 50Ω  
50pF  
DC Output Load Circuit  
AC Output Load Circuit  
Rev. 1.0 / Aug. 2009  
6
Synchronous DRAM Memory 128Mbit (8Mx16bit)  
H57V1262GFR Series  
CAPACITANCE (f=1MHz, VDD=3.3V)  
Parameter  
Pin  
Symbol  
Min  
Max  
Unit  
CLK  
CI1  
2.0  
4.0  
pF  
Input capacitance  
A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS,  
WE, LDQM, UDQM  
CI2  
2.0  
3.0  
4.0  
5.5  
pF  
pF  
Data input / output capacitance  
DQ0 ~ DQ15  
CI/O  
DC CHARACTERISTICS I  
Parameter  
Symbol  
Min  
Max  
Unit  
Note  
Input Leakage Current  
Output Leakage Current  
Output High Voltage  
Output Low Voltage  
ILI  
ILO  
-1  
-1  
2.4  
-
1
1
uA  
uA  
V
1
2
VOH  
VOL  
-
IOH = -2mA  
0.4  
V
IOL = +2mA  
Notes:  
1. VIN = 0 to 3.3V, All other balls are not tested under VIN =0V  
2. DOUT is disabled, VOUT=0 to 3.6  
Rev. 1.0 / Aug. 2009  
7
Synchronous DRAM Memory 128Mbit (8Mx16bit)  
H57V1262GFR Series  
DC CHARACTERISTICS II  
Speed  
Parameter  
Symbol  
Test Condition  
Unit Note  
5
6
7
H
Burst length=1, One bank active  
tRC ≥ tRC(min), IOL=0mA  
CKE ≤ VIL(max), tCK = 15ns  
CKE ≤ VIL(max), tCK = ∞  
CKE ≥ VIH(min), CS ≥ VIH(min), tCK =  
15ns  
Operating Current  
IDD1  
100  
80  
70  
70 mA  
1
IDD2P  
2
2
mA  
mA  
Precharge Standby Current  
in Power Down Mode  
IDD2PS  
IDD2N  
Input signals are changed one time  
during 2clks.  
18  
Precharge Standby Current  
in Non Power Down Mode  
mA  
mA  
mA  
All other pins ≥ VDD-0.2V or ≤ 0.2V  
CKE ≥ VIH(min), tCK = ∞  
Input signals are stable.  
CKE ≤ VIL(max), tCK = 15ns  
CKE ≤ VIL(max), tCK = ∞  
CKE ≥ VIH(min), CS ≥ VIH(min), tCK =  
15ns  
IDD2NS  
15  
IDD3P  
5
5
Active Standby Current  
in Power Down Mode  
IDD3PS  
IDD3N  
Input signals are changed one time  
during 2clks.  
40  
Active Standby Current  
in Non Power Down Mode  
All other pins ≥ VDD-0.2V or ≤ 0.2V  
CKE ≥ VIH(min), tCK = ∞  
Input signals are stable.  
tCK ≥ tCK(min), IOL=0mA  
All banks active  
IDD3NS  
35  
Burst Mode Operating Cur-  
rent  
IDD4  
IDD5  
120 100 100 100 mA  
210 200 190 190 mA  
1
2
Auto Refresh Current  
tRC ≥ tRC(min), All banks active  
Normal  
2
mA  
Self Refresh Current  
IDD6  
CKE ≤ 0.2V  
3
Low  
800  
uA  
power  
Notes:  
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open  
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II  
3. H57V1262GTR-XXC Series: Normal Power  
H57V1262GTR-XXL Series: Low Power  
Rev. 1.0 / Aug. 2009  
8
Synchronous DRAM Memory 128Mbit (8Mx16bit)  
H57V1262GFR Series  
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)  
5
6
7
H
Sym-  
bol  
Parameter  
Unit Note  
Min Max Min Max Min Max Min Max  
CL = 3  
CL = 2  
tCK3  
5.0  
-
6.0  
-
7.0  
-
7.5  
10  
2.5  
2.5  
-
ns  
ns  
System Clock Cycle Time  
1000  
1000  
1000  
1000  
tCK2  
tCHW  
tCLW  
tAC3  
tAC2  
tOH  
Clock High Pulse Width  
Clock Low Pulse Width  
1.75  
1.75  
-
-
2.0  
2.0  
-
-
2.0  
2.0  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1
1
-
-
-
-
CL = 3  
CL = 2  
4.5  
5.4  
5.4  
5.4  
Access Time From Clock  
2
-
-
-
-
-
-
-
-
-
-
6.0  
Data-out Hold Time  
Data-Input Setup Time  
Data-Input Hold Time  
Address Setup Time  
Address Hold Time  
CKE Setup Time  
2.0  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.0  
-
2.0  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.0  
-
2.5  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
-
2.7  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
-
-
tDS  
-
-
-
-
1
1
1
1
1
1
1
1
tDH  
-
-
-
-
tAS  
-
-
-
-
tAH  
-
-
-
-
-
tCKS  
tCKH  
tCS  
-
-
-
CKE Hold Time  
-
-
-
-
Command Setup Time  
Command Hold Time  
-
-
-
-
tCH  
-
-
-
-
CLK to Data Output in Low-Z Time  
tOLZ  
tOHZ3  
tOHZ2  
-
-
-
-
CL = 3  
CL = 2  
4.5  
-
5.4  
-
5.4  
-
5.4  
6.0  
CLK to Data Output  
in High-Z Time  
-
-
-
-
Notes:  
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.  
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,  
then (tR/2-0.5)ns should be added to the parameter.  
Rev. 1.0 / Aug. 2009  
9
Synchronous DRAM Memory 128Mbit (8Mx16bit)  
H57V1262GFR Series  
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)  
5
6
7
H
Uni Not  
Parameter  
Symbol  
t
e
Min Max Min Max Min Max Min Max  
RAS Cycle Time  
RAS Cycle Time  
RAS to CAS Delay  
RAS Active Time  
RAS Precharge Time  
Operation  
tRC  
55  
55  
15  
-
-
-
60  
60  
18  
42  
-
63  
63  
20  
42  
-
-
-
63  
63  
20  
-
-
-
ns  
ns  
ns  
ns  
Auto  
Refresh  
tRRC  
tRCD  
tRAS  
-
-
120  
K
38.7 100K  
100K  
100K 42  
tRP  
15  
10  
1
-
-
-
18  
12  
1
-
-
-
20  
14  
1
-
-
-
20  
15  
1
-
-
-
ns  
ns  
RAS to RAS Bank Active Delay  
CAS to CAS Delay  
tRRD  
tCCD  
CLK  
Write Command to  
Data-In Delay  
tWTL  
0
2
-
-
0
2
-
-
0
2
-
-
0
2
-
-
CLK  
CLK  
Data-in to Precharge Command  
Data-In to Active Command  
DQM to Data-Out Hi-Z  
tDPL  
tDAL  
tDPL + tRP  
tDQZ  
tDQM  
tMRD  
tPROZ3  
tPROZ2  
tDPE  
2
0
2
3
-
-
-
2
0
2
3
-
-
-
2
0
2
3
-
-
-
2
0
2
3
2
1
1
-
-
-
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
ms  
DQM to Data-In Mask  
MRS to New Command  
-
-
-
-
Precharge to Data  
Output High-Z  
CL = 3  
CL = 2  
-
-
-
-
-
-
-
-
Power Down Exit Time  
Self Refresh Exit Time  
Refresh Time  
1
1
-
-
1
1
-
-
1
1
-
-
-
tSRE  
-
-
-
-
1
tREF  
64  
64  
64  
64  
Note:  
1. A new command can be given tRRC after self refresh exit.  
Rev. 1.0 / Aug. 2009  
10  
Synchronous DRAM Memory 128Mbit (8Mx16bit)  
H57V1262GFR Series  
COMMAND TRUTH TABLE  
Command  
CKEn-1  
CKEn  
CS  
L
RAS  
CAS  
L
WE  
L
DQM  
ADDR  
A10/AP  
BA  
Note  
Mode Register Set  
H
X
L
X
H
L
X
OP code  
H
L
X
X
No Operation  
H
H
H
X
X
X
X
X
X
X
H
H
Bank Active  
L
H
H
RA  
V
V
Read  
L
H
L
L
L
H
H
L
L
L
H
L
CA  
CA  
X
Read with Autoprecharge  
Write  
H
H
X
X
X
V
Write with Autoprecharge  
Precharge All Banks  
Precharge selected Bank  
Burst Stop  
H
H
L
X
V
X
X
L
L
H
H
L
L
H
H
H
H
X
X
V
X
X
DQM  
X
Auto Refresh  
H
X
L
L
L
L
L
L
H
L
X
A9 ball High  
MRS  
Mode  
Burst-Read-Single-WRITE  
Entry  
H
H
L
X
X
(Other balls OP code)  
L
H
L
L
X
H
X
H
X
H
X
V
L
X
H
X
H
X
H
X
V
H
X
H
X
H
X
H
X
V
Self Refresh1  
Exit  
X
L
H
L
H
L
X
X
X
H
L
Entry  
Precharge  
power down  
X
X
H
L
Exit  
H
H
L
Entry  
H
L
L
X
X
Clock Suspend  
Exit  
H
X
Rev. 1.0 / Aug. 2009  
11  
Synchronous DRAM Memory 128Mbit (8Mx16bit)  
H57V1262GFR Series  
PACKAGE INFORMATION  
54 Ball FBGA 8.0mm x 8.0mm  
8.00 Typ.  
A1 INDEX MARK  
6.4  
Unit  
[mm]  
0.8±0.1  
0.80 Typ.  
Bottom  
View  
8.00  
Typ.  
0.45  
+/- 0.05  
6.4  
0.35  
+0.025/- 0.05  
0.8±  
0.1  
1.60  
0.80  
Typ.  
1.0 max  
Rev. 1.0 / Aug. 2009  
12  

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H57V1262GFR-60X

 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O
HYNIX

H57V1262GFR-70X

 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O
HYNIX

H57V1262GFR-75C

 Synchronous DRAM, 2MX16, 5.4ns, CMOS, PBGA54, 8 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, FBGA-54
HYNIX

H57V1262GFR-75I

 Synchronous DRAM, 2MX16, 5.4ns, CMOS, PBGA54, 8 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, FBGA-54
HYNIX
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