GMS34140T [HYNIX]
4-BIT SINGLE CHIP MICROCOMPUTERS; 4位单芯片微型计算机
| 型号： | GMS34140T |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | 4-BIT SINGLE CHIP MICROCOMPUTERS |
| 文件： | 总49页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4-BIT SINGLE CHIP MICROCOMPUTERS
GMS34XXXT SERIES
USER`S MANUAL
• GMS34004T
• GMS34112T
• GMS34140T
Revision 1.0
Published by
MCU Application Team in Hyundai Electronics Industrial Co., Ltd.
Hyundai Electronics Industrial Co., Ltd. 1996 All Right Reserved.
Editor's E-Mail :
kanghan@hei.co.kr
lbkd@hei.co.kr
rhja@hei.co.kr
Additional information of this manual may be served by Hyundai Electronics Industrial Offices in
Korea or Distributors and Representative listed at address directory.
Hyundai Electronics Industrial reserves the right to make changes to any Information here in at
any time without notice.
The information, diagrams, and other data in this manual are correct and reliable; however, Hyundai
Electronics Industrial Co., Ltd. is in no way responsible for any violations of patents or other rights of
the third party generated by the use of this manual.
Table of Contents
Table of Contents
Chapter 1
Introduction
............................................................................................1-1
Outline of Characteristics
.................................................................1-1
..................................................................................1-1
..................................................................................1-2
Characteristics
Block Diagram
Pin Assignment and Terminal
Pin Dimension ..................................................................................1-4
Pin Description and Circuit .................................................................1-7
..........................................................1-3
I/O circuit types and options
Electrical Characteristics
.............................................................1-8
................................................................1-10
Chapter 2
Architecture
...........................................................................................2-1
Block Description
Program Memory (ROM)
EPROM Address Register
Data Memory (RAM)
.............................................................................2-1
..................................................................2-1
................................................................2-2
........................................................................2-3
X-Register (X)
...................................................................................2-3
Y-Register (Y) ...................................................................................2-4
Accumulator (Acc) ............................................................................2-4
Arithmetic and Logic Unit (ALU) .......................................................2-4
State Counter (SC)
Clock Generator
Pulse Generator
...........................................................................2-5
...............................................................................2-6
...............................................................................2-7
Initial Reset Circuit ............................................................................2-8
Watch Dog Timer (WDT) .................................................................2-8
Stop Function ....................................................................................2-9
Port Operation
..................................................................................2-9
Chapter 3
Instruction
........................................................................................3-1
Table of Contents
Chapter 4
EPROM
.................................................................................................4-1
GMS34004TK/34112TK/34140TK
.........................................................4-1
Mode Define
Port Define
Programming Data
Write/Read Data Conversion
.....................................................................................4-1
.......................................................................................4-2
...........................................................................4-2
............................................................4-3
Checksum .........................................................................................4-3
Programming Control ........................................................................4-3
Programming DC Specification .........................................................4-3
EPROM read mode(1/2)
EPROM read mode (2/2)
...................................................................4-4
..................................................................4-4
EPROM write mode (1/2) ..................................................................4-5
EPROM write mode (2/2) ..................................................................4-5
Lock bit write mode (1/2)
Lock bit write mode (2/2)
Lock bit read mode (1/2)
Lock bit read mode (2/2)
..................................................................4-6
..................................................................4-6
..................................................................4-7
..................................................................4-7
GMS34004T/112T/140T (Pin assignment & Package) .....................4-8
EPROM (KHz) mode .........................................................................4-9
EPROM write only mode
..................................................................4-9
GMS34004TK/34112TK/34140TK .............................................................4-10
Mode Define .....................................................................................4-10
Port Define ........................................................................................4-11
Programming Data ...........................................................................4-11
Write/Read Data Conversion ............................................................4-12
Checksum ........................................................................................4-12
Programming Control ......................................................................4-12
Programming DC Specification ........................................................4-12
EPROM read mode(1/2) ...................................................................4-13
EPROM read mode (2/2) ...................................................................4-13
EPROM write mode (1/4) ..................................................................4-14
EPROM write mode (2/4) ..................................................................4-14
EPROM write mode (3/4) ..................................................................4-15
EPROM write mode (4/4) ..................................................................4-15
Lock bit write mode (1/3) ..................................................................4-16
Lock bit write mode (2/3) ..................................................................4-16
Lock bit write mode (3/3) ..................................................................4-16
Lock bit read mode (1/2) ..................................................................4-18
Lock bit read mode (2/2) ..................................................................4-18
INTRODUCTION
ARCHITECTURE
INSTRUCTION
EPROM
1
2
3
4
Chapter 1. Introduction
CHAPTER 1. Introduction
OUTLINE OF CHARACTERISTICS
The GMS340 series are remote control transmitter which uses CMOS technology,
and the EPROM version of GMS34XXX series.
This enables transmission code outputs of different configurations, multiple custom
code output, and double push key output for easy fabrication.
The GMS340 series are suitable for remote control of TV, VCR, FANS, Air-
conditioners, Audio Equipments, Toys, Games etc.
Characteristics
·
Program memory : 512bytes for GMS34004T
1,024 bytes for GMS34112T/140T
¡ ¿
4 bits
43 types of instruction set
3 levels of subroutine nesting
1 bit output port for a large current (REMOUT signal)
Operating frequency :300KHz~500KHz at KHz version
2.4MHz~4MHz at MHz version
·
·
·
·
·
Data memory : 32
300KHz~4.2MHz at WIDE version
·
Instruction cycle : fOSC/6 at KHz and WIDE version
fOSC/48 at MHz version
·
·
·
·
·
·
CMOS process (3.0V or 5.0V power supply)
Stop mode (Through internal instruction)
Released stop mode by key input
Built in capacitor for ceramic oscillation circuit at KHz version
Built in a watch dog timer (WDT)
Low operating voltage : 2.2~4.5V (at KHz and MHz version)
Normal operating voltage: 4.0~5.0V (at WIDE version)
Series
Program memory
Data memory
I/O ports
GMS34004T
GMS34112T
GMS34140T
¡ ç
¡ ç
¡ ç
¡ ç
512
1,024
¡ ¿
¡ ç
32
4
-
4
¡ ç
Input ports
4
6
¡ ç
¡ ç
10
D0 ~ D9
Output ports
D0 ~ D5
Package
16DIP
20DIP/SOP/SSOP
GMS34112TK
GMS34112TM
GMS34112TW
24DIP/SOP
GMS34140TK
GMS34140TM
GMS34140TW
KHz version
MHz version
WIDE version
GMS34004TK
GMS34004TM
GMS34004TW
Table 1-1 GMS34XXXT series members
1 - 1
Chapter 1. Introduction
Block Diagram
RESET/Vpp VDD
GND
2
1
24
Reset
ROM
10
Watchdog
timer
Stack
¡ ¿
64word
16page
¡ ¿
Program counter
10
8bit
8
4
4
8
4
Instruction
Decoder
4
ALU
MUX
4
4
RAM
Word
Selector
Control Signal
2
16
RAM
16word x
2page x 4bit
X-Reg
Y-Reg
ST
4
ACC
4
10
4
R-Latch
D-Latch
10
OSC
Pulse
Generator
4
4
4
23 22
7
8
9
10
3
4
5
6
11 12 13 14 15 16 17 18 19 20
D0 ~ D9
21
OSC1 OSC2
K0 ~ K3
R0 ~ R3
REMOUT
Fig 1-1 Block Diagram (In case of GMS34140T)
1 - 2
Chapter 1. Introduction
Pin Assignment and terminals
Pin Assignment
RESET/Vpp
1
2
3
4
5
6
7
8
16 VDD
15 OSC1
14 OSC2
13 REMOUT
12 D5
K0
K1
K2
K3
D0
D1
D2
D3
D4
1
2
3
4
5
6
7
8
9
20 R3
GND
K0
19 R2
18 R1
K1
17 R0
K2
16 GND
15 RESET/Vpp
14 VDD
13 OSC1
12 OSC2
11 REMOUT
K3
11 D4
D0
D1
10 D3
9
D2
D5 10
Fig 1-2 GMS34004T Pin Assignment
(16PDIP)
Fig 1-3 GMS34112T Pin Assignment
(20DIP/SOP)
GND
R0
R1
R2
R3
K0
1
2
3
4
5
6
7
8
9
20 RESET/Vpp
19 VDD
18 OSC1
17 OSC2
16 REMOUT
15 D5
RESET/Vpp
1
2
3
4
5
6
7
8
9
24 VDD
23 OSC1
22 OSC2
21 REMOUT
20 D7
GND
R0
R1
R2
R3
K0
19 D6
K1
14 D4
18 D5
K2
13 D3
K1
17 D4
K3
12 D2
K2
16 D3
D0 10
11 D1
K3 10
D0 11
D8 12
15 D2
14 D1
13 D9
Fig 1-4 GMS34112T Pin Assignment
(20SSOP only)
Fig 1-5 GMS34140T Pin Assignment
(24DIP/SOP)
1 - 3
Chapter 1. Introduction
Pin Dimension
16 15 14 13 12 11 10
9
1
2
3
4
5
6
7
8
0.300BSC
0.260MAX
0.240MIN
0.785MAX
0.745MIN
0.065MAX
0.050MIN
0.100BSC
0.014MAX
0~15¡ Ç
0.022MAX
0.015MIN
¡ æ ¡ ç
¡ æ ¡ ç
0.008MIN
0.040MAX
0.020MIN
Outline (Unit:Inch)
Fig 1-6 16PDIP Pin Dimension
20 19 18 17 16 15 14 13 12 11
1
2
3
4
5
6
7
8
9
10
0.3TYP
0.270MAX
0.250MIN
0.984MAX
0.968MIN
0.1TYP
0.012MAX
0.065MAX
0.055MIN
0.022MAX
0.015MIN
0~15¡ Ç
¡ æ ¡ ç
¡ æ ¡ ç
0.008MIN
Outline (Unit : Inch)
Fig 1-7 20PDIP Pin Dimension
1 - 4
Chapter 1. Introduction
20 19 1 8 17 16 15 14 13 12 11
1
2
3
4
5
6
7
8
9
10
0.419MAX
0.398MIN
0.5118MAX
0.4961MIN
0.299MAX
0.292MIN
0.042MAX
0.016MIN
¡ æ
¡ ç
0.0125MAX
0.0091MIN
0.05TYP
0.020MAX
0.014MIN
Outline (Unit : Inch)
Fig 1-8 20SOP Pin Dimension
20 19 1 8 17 16 15 14 13 12 11
0.244MAX
0.234MIN
1
2
3
4
5
6
7
8
9
10
0.157MAX
0.150MIN
0.344MAX
0.337MIN
0-8¢ª
¡ é
¡ è
¡ æ
¡ ç
0.022MIN
0.025BSC
0.012MAX
0.008MIN
0.032MAX
Outline (Unit : Inch)
Fig 1-9 20SSOP Pin Dimension
1 - 5
Chapter 1. Introduction
13
12
24 23 22 21 20 19 18 17 16 15 14
1
2
3
4
5
6
7
8
9
10 11
0.3TYP
0.270MAX
0.250MIN
1.255MAX
1.245MIN
0.1TYP
0.012MAX
0.065MAX
0.055MIN
0.022MAX
0.015MIN
0~15¢ª
¡ æ ¡ ç
¡ æ ¡ ç
0.008MIN
Outline (Unit : Inch)
Fig 1-10 24Skinny DIP Pin Dimension
13
24 23 22 21 20 19 18 17 16 15 14
1
2
3
4
5
6
7
8
9
10 11 12
0.419MAX
0.398MIN
0.299MAX
0.292MIN
0.616MAX
0.595MIN
0.042MAX
0.016MIN
¡ æ
¡ ç
0.05TYP
0.0125MAX
0.0091MIN
0.020MAX
0.014MIN
0.018MAX
0.004MIN
Outline (Unit : Inch)
Fig 1-11 24SOP Pin Dimension
1 - 6
Chapter 1. Introduction
Pin Description and Circuit
Pin Description
Pin
I/O
Function
VDD
-
Connected to 2.2~4.5V power supply at KHz and MHz
version or 4.0 ~ 5.5V power supply at WIDE version.
GND
-
Connected to 0V power supply.
Used to input a manual reset. When the pin goes "L",
the D-output ports and REMOUT-output port are initialized to
"L", and ROM address is set to address 0 on page 0.
For programming, this pin receives 12.5V programming
voltage.
RESET
Input
4-bit input port.
STOP mode is released by "L" input of each pin.
K0~K3
D0~D9
Input
Output
The output is the structure of N-channel-open-drain.
4-bit I/O port. (Input mode is set only when each of them
output "H".)
In outputting, each can be set and reset independently(or at
once.)
R0~R3
I/O
The output is in the form of C-MOS.
STOP mode is released by "L" input of each pin.
High current output port.
The output is in the form of C-MOS.
The state of large current on is "H".
REMOUT
Output
Oscillator input. Input to the oscillator circuit and connection
point for ceramic resonator.
Internal capacitors available at KHz version.
OSC1
OSC2
Input
A feedback resistor is connected between this pin and OSC2.
Output
Connect a resonator between this pin and OSC1.
1 - 7
Chapter 1. Introduction
I/O circuit types and options
Pin
I/O
I/Ocircuit
Note
¡ æ
¡ ç
Hysteresis Input Type.
Built in pull-up-resistor,
Reset/Vpp
I
§Ú
Typical 800
¡ æ
¡ ç
pull-up
CMOS output.
"H" output at reset.
Built in MOS Tr for
¡ ç
¡ æ
¡ ç
R0~R3
I/O
¡ æ
§Ú
.
pull-up about 120
pull-up
¡ æ
K0~K3
I
¡ æ
¡ ç
Built in MOS Tr for
§Ú
pull-up About 120
.
D0~D9
Open drain output.
"L" output at reset.
O
¡ ç
CMOS output.
"L" output at reset.
High current output
source.
¡ æ
¡ ç
REMOUT
O
1 - 8
Chapter 1. Introduction
Pin
I/O
I/Ocircuit
Note
Built in feedback-resistor
STOP
§Û
about 1
OSC2
O
¡ æ
¡ ç
OSC1
OSC2
Rd
Built in damping-resistor
§Ú
Rd = 4
¡ æ
¡ ç
[No resistor in MHz
operation]
Built in resonance
Capacitor at KHz version
¡ ¾
C1=C2 = 100pF 15%
¡ è
¡ è
[C1,C2 are not available
for MHz and WIDE
version]
OSC1
I
C1
C2
Rf
Frequency
ResonatorMaker
Part Name
Load Capacitor
320KHz
500KHz
CQ
CQ
ZTB320D
ZTB500E
C1=C2=Open
C1=C2=Open
CQ recommend 430KHz~500KHz resonator
3.43MHz
3.52MHz
CQ
TDK
CQ
ZTA3.43MG
FCR3.52M5
ZTA3.64MG
FCR3.64M5
ZTA3.84MG
FCR3.84M5
ZTA4.00MG
C1=C2=30pF
C1=C2=33pF
C1=C2=30pF
C1=C2=33pF
C1=C2=30pF
C1=C2=33pF
C1=C2=30pF
3.64MHz
TDK
CQ
3.84MHz
4.00MHz
TDK
CQ
1 - 9
Chapter 1. Introduction
Electrical Characteristics
¡ É
Absolute maximum ratings (Ta = 25
)
Parameter
Symbol
Max. rating
Unit
Supply Voltage
VDD
-0.3 ~ 7.0
V
Programming Voltage
Power dissipation
Storage temperature range
Input voltage
VPP
PD
-0.3 ~ 13.5
700 *
V
mW
¡ É
Tstg
VIN
-55 ~ 125
-0.3 ~ VDD+0.3
-0.3 ~ VDD+0.3
V
V
Output voltage
VOUT
¡ É
* Thermal derating above 25
¡ É
rise in temperature.
: 6mW per degree
Recommended operation condition
Parameter
Symbol
Condition
300 ~ 500KHz
2.4 ~ 4MHz
Rating
2.2 ~ 4.5
2.2 ~ 4.5
Unit
V
VDD
Supply Voltage
300KHz ~ 4.2MHz
-
4.0 ~ 5.5
-20 ~ +70
Topr
Operating temperature
¡ É
1 - 10
Chapter 1. Introduction
¡ É
Electrical characteristics for low voltage products (Ta=25 , VDD=3V)
Limits
Unit
Condition
Parameter
Symbol
Min. Typ. Max.
1
uA
uA
VI=VDD
IIH
-
-
Input H current
-16
VI=GND
IIL2
-2
-7.5
RESET input L current
VI=GND, Output
off, Pull-Up resistor
provided.
-50
uA
IIL1
-9
-25
K, R input L current
-
0.9
-
V
V
-
VIH1
VIL1
VIH2
VIL2
2.1
-
-
-
-
K, R input H voltage
K, R input L voltage
-
-
2.25
-
V
-
RESET input H voltage
RESET input L voltage
0.75
0.4
0.4
-
V
V
V
IOL=1mA
IOL=100uA
IOH=-8mA
IOL=70uA
IOH=70uA
VOL2
VOL1
VOH1
VOL3
VOH3
-
-
0.15
0.15
2.5
D. R output L voltage
REMOUT output L voltage
V
V
2.1
-
REMOUT output H voltage
OSC2 output L voltage
0.9
-
V
0.4
V
2.1
2.5
OSC2 output H voltage
D, R output leakage current
1
uA
uA
IOL
-
-
-
-
V0UT=VDD, Output off
At STOP mode
fOSC=455KHz
1
ISTOP
Current on STOP mode
4.0
4.0
500
4
mA
mA
IDD1
IDD2
*
*
-
0.3
0.5
-
Operating supply current 1
fOSC=4MHz
-
Operating supply current 2
fOSC/6
KHz
MHz
KHz version
MHz version
fOSC
fOSC
300
2.4
System
clock
frequency
fOSC/48
-
* IDD1, IDD2, is measured at RESET mode.
1 - 11
Chapter 1. Introduction
¡ É
Electrical characteristics (Ta=25 , VDD=5V)
Limits
Unit
Condition
Parameter
Symb
ol
Min.
Typ. Max.
5
uA
uA
VI=VDD
IIH
-
-
-
Input H current
-20
VI=GND
IIL2
-2
-9
RESET input L current
VI=GND, Output
off, Pull-Up resistor
provided.
-150
uA
IIL1
-
K, R input L current
-
V
V
-
VIH1
VIL1
VIH2
VIL2
0.7*VDD
-
-
-
-
K, R input H voltage
K, R input L voltage
0.3*VDD
-
-
-
V
-
0.75*VDD
-
RESET input H voltage
RESET input L voltage
0.25*VDD
V
V
0.4
0.4
-
V
IOL=2mA
IOL=100uA
IOH=-8mA
IOL=70uA
IOH=-70uA
VOL2
VOL1
VOH1
VOL3
VOH3
-
-
-
-
-
-
D. R output L voltage
REMOUT output L voltage
V
-
V
VDD-1.0
-
REMOUT output H voltage
OSC2 output L voltage
0.9
-
V
V
VDD-1.0
OSC2 output H voltage
D, R output leakage current
5
uA
uA
mA
IOL
ISTOP
IDD
-
-
-
-
-
-
V0UT=VDD, Output off
At STOP mode
10
10
Current on STOP mode
Operating supply current
At RESET mode
System
fOSC/6
4.2
MHz
WIDE version
0.3
-
fOSC
clock
frequency
1 - 12
INTRODUCTION
ARCHITECTURE
INSTRUCTION
EPROM
1
2
3
4
Chapter 2. Architecture
CHAPTER 2. Architecture
BLOCK DESCRIPTION
Program Memory (EPROM)
¡ ¿
The GMS34XXXT series can incorporate maximum 1,024 words (64 words 16
¡ ¿
pages 8bits) for program memory. Program counter PC (A0~A5) and page
address register (A6~A9) are used to address the whole area of program
memory having an instruction (8bits) to be next executed.
The program memory consists of 64 words on each page, and thus each page
can hold up to 64 steps of instructions.
The program memory is composed as shown below.
Program capacity (pages)
0
1
2
3
4
8
5
6
7
Page 0
Page 1
Page 2
Page 15
63
0
1
2
15
A0~A5
A6~A9
Program counter (PC)
6
Page address register (PA)
Page buffer (PB)
4
4
Stack register
(Level "1")
(Level "2")
(Level "3")
(SR)
(PSR)
Fig 2-1 Configuration of Program Memory
2 - 1
Chapter 2. Architecture
EPROM Address Register
The following registers are used to address the EPROM.
• Page address register (PA) :
Holds EPROM's page number (0~Fh) to be addressed.
• Page buffer register (PB) :
Value of PB is loaded by an LPBI command when newly addressing a page.
Then it is shifted into the PA when rightly executing a branch instruction (BR)
and a subroutine call (CAL).
• Program counter (PC) :
Available for addressing word on each page.
• Stack register (SR) :
Stores returned-word address in the subroutine call mode.
(1) Page address register and page buffer register :
Address one of pages #0 to #15 in the EPROM by the 4-bit binary counter.
Unlike the program counter, the page address register is usually unchanged
so that the program will repeat on the same page unless a page changing
command is issued. To change the page address, take two steps such as
(1) writing in the page buffer what page to jump (execution of LPBI) and
(2) execution of BR or CAL, because instruction code is of eight bits so
that page and word can not be specified at the same time.
In case a return instruction (RTN) is executed within the subroutine that has
been called in the other page, the page address will be changed at the
same time.
(2) Program counter :
This 6-bit binary counter increments for each fetch to address a word in the
currently addressed page having an instruction to be next executed.
For easier programming, at turning on the power, the program counter is
reset to the zero location. The PA is also set to "0". Then the program
counter specifies the next EPROM address in random sequence.
When BR, CAL or RTN instructions are decoded, the switches on each step
are turned off not to update the address. Then, for BR or CAL, address
data are taken in from the instruction operands (a0 to a5), or for RTN, and
address is fetched from stack register No. 1.
(3) Stack register :
This stack register provides two stages each for the program counter (6
bits) and the page address register (4bits) so that subroutine nesting can be
made on two levels.
2 - 2
Chapter 2. Architecture
Data memory (RAM)
¡ ¿
¡ ¿
4bits) is incorporated for storing data.
Up to 32 nibbles (16 words
2pages
The whole data memory area is indirectly specified by a data pointer (X,Y). Page
number is specified by zero bit of X register, and words in the page by 4 bits in
Y-register. Data memory is composed in 16 nibbles/page. Figure 2-2 shows the
configuration.
D0
D9 R0 R3 REMOUT
Data memory page (0~1)
Output port
0
1
2
3
Page 0
Page 1
15
4
A0~A3
0
1
Y-register (Y)
X-register (X)
4
2
Fig 2-2 Composition of Data Memory
X-register (X)
X-register is consist of 2bit, X0 is a data pointer of page in the RAM, X1 is only
used for selecting of D8~D9 with value of Y-register
X1=0
D0
X1=1
D8
Y=0
Y=1
D1
D9
Table 2-1 Mapping table between X and Y register
2 - 3
Chapter 2. Architecture
Y-register (Y)
Y-register has 4 bits. It operates as a data pointer or a general-purpose register.
Y-register specifies and address (a0~a3) in a page of data memory, as well as it
is used to specify an output port. Further it is used to specify a mode of carrier
signal outputted from the REMOUT port. It can also be treated as a general-
purpose register on a program.
Accumulator (ACC
)
The 4-bit register for holding data and calculation results.
Arithmetic and Logic Unit (ALU)
In this unit, 4bits of adder/comparator are connected in parallel as it's main
components and they are combined with status latch and status logic (flag.)
(1) Operation circuit (ALU) :
The adder/comparator serves fundamentally for full addition and data
comparison. It executes subtraction by making a complement by processing
an inversed output of ACC (ACC+1)
(2) Status logic :
This is to bring an ST, or flag to control the flow of a program. It occurs when
a specified instruction is executed in three cases such as overflow or
underflow in operation and two inputs unequal.
2 - 4
Chapter 2. Architecture
State Counter (SC)
A fundamental machine cycle timing chart is shown below. Every instruction is
one byte length. Its execution time is the same. Execution of one instruction
takes 6 clocks for fetch cycle and 6 clocks for execute cycle (12 clocks in total).
Virtually these two cycles proceed simultaneously, and thus it is apparently
completed in 6 clocks (one machine cycle). Exceptionally BR, CAL and RTN
instructions is normal execution time since they change an addressing
sequentially. Therefore, the next instruction is prefetched so that its execution
is completed within the fetch cycle.
T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T6
Fetch cycle N
Execute cycle N
Fetch cycle N-1
Execute cycle N-1
¥°
Phase
¥±
Phase
¥²
Phase
Machine
Cycle
Machine
Cycle
Fig. 2-3 Fundamental timing chart
2 - 5
Chapter 2. Architecture
Clock Generator
The GMS34XXXT series has an internal clock oscillator. The oscillator circuit is
designed to operate with an external ceramic resonator. Internal capacitors are
available at KHz version. Oscillator circuit is able to organize by connecting
ceramic resonator to outside.
* It is necessary to connect capacitor to outside in order to change ceramic
resonator, you must refer to a manufacturer`s resonator matching guide.
OSC1
OSC2
OSC1
23
OSC2
22
23
22
C1
C2
<Circuit 1>
<Circuit 2>
Version
Operating Frequency
Oscillation Circuit
Internal capacitor
No Internal capacitor
No Internal capacitor
No Internal capacitor
Circuit 2
KHz
300KHz ~ 500KHz
Circuit 1
Circuit 1
Circuit 1
MHz
2.4MHz ~ 4MHz
WIDE
300KHz ~ 4.2MHz
2 - 6
Chapter 2. Architecture
Pulse generator
The following frequency and duty ratio are selected for carrier signal outputted
from the REMOUT port depending on a PMR (Pulse Mode Register) value set in
a program.
T
T1
PMR
REMOUTsignal
0
1
2
3
4
5
6
7
T=1/fPUL = 12/fOSC [96/fOSC],
T1/T = 1/2
T1/T = 1/3
T1/T = 1/2
T1/T = 1/4
T1/T = 4/11
T=1/fPUL = 12/fOSC [96/fOSC],
T=1/fPUL = 8/fOSC [64/fOSC],
T=1/fPUL = 8/fOSC [64/fOSC],
T=1/fPUL = 11/fOSC [88/fOSC],
No Pulse (same to D0~D9)
T=1/fPUL = 12/fOSC [96/fOSC],
No pulse (same to D0 ~ D9)
T1/T = 1/4
* Default value is "0"
* [ ] means the value of "T", when Instruction cycle is fOSC/48 in MHz version
Table 2-2 PMR selection table
2 - 7
Chapter 2. Architecture
Initial Reset Circuit
RESET pin must be down to "L" more than 4 machine cycle by outside
capacitor or other for power on reset.
The mean of 1 machine cycle is 6/fOSC or 48/fOSC, however, operating voltage
must be in recommended operating conditions, and clock oscillating stability.
* It is required to adjust C value depending on rising time of power supply.
(Example shows the case of rising time shorter than 10ms.)
1
RESET
0.1uF
Watch Dog Timer (WDT)
Watch dog timer is organized binary of 14 steps. The signal of fOSC/6 cycle comes
in the first step of WDT after WDT reset. If this counter was overflowed, reset
signal automatically come out so that internal circuit is initialized.
¡ ¿
¡ ¿ ¡ ¿
The overflow time is 6
8
2
13/fOSC (108.026ms at fOSC=455KHz.)
13
6
2 /fOSC (108.026ms at fOSC = 3.64MHz)
Normally, the binary counter must be reset before the overflow by using reset
instruction (WDTR) or / and REMOUT port HIGH(Y-reg=8, So instruction execution).
* It is constantly reset in STOP mode. When STOP is released, counting is
restarted. (Refer to 2-9 STOP function>)
Binary counter
(14 steps)
RESET (edge-trigger)
CPU reset
fOSC/6 or fOSC/48
Reset
by instruction
REMOUT
output
2 - 8
Chapter 2. Architecture
STOP Operation
Stop mode can be achieved by STOP instructions.
In stop mode :
1. Oscillator is stopped, the operating current is low.
2. Watch dog timer is reset, D8~D9 output and REMOUT output are "L".
3. Part other than WDT, D8~D9 output and REMOUT output have a value before
come into stop mode.
Stop mode is released when one of K or R input is going to "L".
1. State of D0~D7 output and REMOUT output is return to state of before stop mode
is achieved.
¡ ¿
2. After 1,024 8 enable clocks for stable oscillating, First instruction start to operate.
3. In return to normal operation, WDT is counted from zero again.
But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction
is same to NOP instruction.
Port Operation
Value of X-reg
Value of X-reg
Operation
¡ ç
¡ ç
0
0 or 1
0 ~ 7
S0 : D(Y)
1, R0 : D(Y)
REMOUT port repeats "H" and "L" in pulse
frequency. (When PMR = 5, it is fixed at "H")
0 or 1
8
¡ ç
S0 : REMOUT(PMR)
R0 : REMOUT(PMR)
1
0
¡ ç
¡ ç
¡ ç
0 or 1
0 or 1
0 or 1
0 or 1
2 or 3
2 or 3
9
S0 : D0 ~ D9
R0 : D0 ~ D9
1 (High-Z)
0
¡ ç
¡ ç
A ~ D
S0 : R(Y-Ah)
R0 : R(Y-Ah)
1
0
¡ ç
¡ ç
E
F
0
1
S0 : R0 ~ R3
R0 : R0 ~ R3
1
0
¡ ç
¡ ç
¡ ç
¡ ç
S0 : D0 ~ D9
R0 : D0 ~ D9
1, R0 ~ R3
0, R0 ~ R3
1
0
¡ ç
¡ ç
S0 : D(8)
R0 : D(8)
1
0
¡ ç
¡ ç
S0 : D(9)
R0 : D(9)
1
0
2 - 9
INTRODUCTION
ARCHITECTURE
INSTRUCTION
EPROM
1
2
3
4
Chapter 3. Instruction
CHAPTER 3. Instruction
InstructionTable
The GMS34XXXT series provides the following 43 basic instructions.
Category Mnemonic
Function
ST*1
S
S
S
S
S
S
S
S
S
S
S
S
S
E
S
S
S
S
C
B
C
B
S
C
B
¡ ç
¡ ç
¡ ç
1
LAY
A
Y
A
Y
A
0
Register to
LYA
Register
LAZ
2
3
¡ ç
¡ ç
4
LMA
M(X,Y)
M(X,Y)
A
¡ ç
Y+1
5
LMAIY
A, Y
RAM to
LYM
Register
LAM
¡ ç
¡ ç
¡ ê
¡ ç
6
Y
A
A
Y
M(X,Y)
M(X,Y)
M(X,Y)
i
7
8
XMA
LYI i
9
¡ ç
¡ ç
Y+1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LMIIY i
LXI n
SEM n
REM n
TM n
BR a
CAL a
RTN
LPBI i
AM
M(X,Y)
i, Y
Immediate
¡ ç
X
n
¡ ç
¡ ç
M(n)
M(n)
1
RAM Bit
Manipulation
0
TEST M(n) = 1
if ST = 1 then Branch
if ST = 1 then Subroutine call
Return from Subroutine
ROM
Address
¡ ç
PB
i
¡ ç
A
A
A
A
A
Y
A
A + M(X,Y)
¡ ç
¡ ç
¡ ç
¡ ç
¡ ç
¡ ç
SM
M(X,Y) - A
M(X,Y) + 1
M(X,Y) - 1
A + 1
IM
Arithmetic
DM
IA
IY
Y + 1
DA
A - 1
3 - 1
Chapter 3. Instruction
Category Mnemonic
Function
ST*1
B
¡ ç
¡ ç
¡ ç
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DY
Y
A
A
Y - 1
Arithmetic
EORM
NEGA
ALEM
ALEI i
MNEZ
YNEA
YNEI i
KNEZ
RNEZ
LAK
A + M (X,Y)
A + 1
S
Z
¡ Â
¡ Â
TEST A
TEST A
M(X,Y)
E
i
E
¡ Á
TEST M(X,Y)
0
N
N
N
N
N
S
Comparison
¡ Á
¡ Á
¡ Á
¡ Á
TEST Y
TEST Y
TEST K
TEST R
A
i
0
0
¡ ç
¡ ç
A
A
K
R
LAR
S
Input /
Output
1*2
0*2
S
¡ ç
¡ ç
SO
Output(Y)
Output(Y)
RO
S
WDTR
STOP
LPY
Watch Dog Timer Reset
Stop operation
S
S
Control
¡ ç
PMR
Y
S
NOP
No operation
S
Note) i = 0~f, n = 0~3, a = 6bit PC Address
*1 Column ST indicates conditions for changing status. Symbols have the following
meanings
S : On executing an instruction, status is unconditionally set.
C : Status is only set when carry or borrow has occurred in operation.
B : Status is only set when borrow has not occurred in operation.
E : Status is only set when equality is found in comparison.
N : Status is only set when equality is not found in comparison.
Z : Status is only set when the result is zero.
*2 Operation is settled by a value of Y-register.
3 - 2
INTRODUCTION
ARCHITECTURE
INSTRUCTION
EPROM
1
2
3
4
Chapter 4. EPROM
CHAPTER 4. EPROM
GMS34004TK / 34112TK / 34140TK
Mode define
Item
Device operation
Modesetting
User mode
Exact User pgm
RESETB = 0 ~ 3V
Vcc=3V
RESETB
=12.5V
EPROM read mode
Address in, Data out
K3~0=0110
Vcc=6.0V
1Byte PGM Write Address in, Data in
2Byte PGM Write Address in, Data in
K3~0=0110
K3~0=0111
-
EPROM
Program
mode
RESETB
=12.5V
Vcc=6.0V
Program verify
Lock bit Write
Lock bit Read
Address in, Data out
Lock bit write(set D5 to 1)
Lock bit out
K3~0=0100
K3~0=0101
Lock bit
Program
mode
Vcc=6.0V,
Lock bit is D5.
(Default : unlock)
RESETB
=12.5V
4 - 1
Chapter 4. EPROM
Port define
Port Name
User Mode
EPROMMode
VDD
RESETB
OSC1
K0
3.0V
6.0V
Reset (0, 3.0V)
Clock input
K0(Input)
K1(Input)
K2(Input)
K3(Input)
D0(Output)
D1(Output)
D2(Output)
D3(Output)
D4(Output)
D5(Output)
0V
Vpp (0, 12.5V)
Clock input
K1
Read / Write Control
Address / Data Control
K2
K3
D0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Da0
Da1
Da2
Da3
-
Da4
Da5
Da6
Da7
-
D1
NMOS open drain I/O
in EPROM mode
D2
D3
D4
D5
Lock bit output
GND
* Undefined ports in this table are N.C (No Connection)
Programming data
Blank data
Device Name ROM Size
Lock bit Device address File address
(HEX)
GMS34004TK
GMS34112TK
GMS34140TK
512bytes
FF
Yes
Yes
Yes
0000 ~ 01FF
0000 ~ 03FF
0000 ~ 03FF
0000 ~ 01FF
0000 ~ 03FF
0000 ~ 03FF
1,024bytes
1,024bytes
FF
FF
- If lock bit is set, the EPROM of the device can not be read, because output is always FF.
- Input file : Intel Hexa format ( *.RHX )
4 - 2
Chapter 4. EPROM
Write / Read data conversion
¡ ê
- You must change MSB ~ LSB
- Example
LSB ~ MSB.
File / buffer data
Device (D3 ~ D0)
Hex
Binary (MSB~LSB)
Hex
Binary (MSB~LSB)
Write
Read
2C
E4
8D
0010 1100
1110 0100
1000 1101
34
27
B1
0011 0100
0010 0111
1011 0001
Checksum
- It is calculated from the Buffer of the programmer.
- Address range is the same as device address.
- Calculate method is the same as normal EPROM devices (ex:27C128, 256 etc)
Programming control
- OSC1 & RESETB control OTP device, so you must count OSC1 clocks in every state.
- K ports control the internal state of the OTP device(ex: Read, Write...).
- D5~D0 ports are NMOS open drain I/O in EPROM mode.
It must be pulled up by resistors (about 4.7~ 47K ohm).
- The frequency rate of the OSC1 clock is 10KHz ~ 500KHz.
You can hold OSC1 HIGH or LOW state when you need.
Programming DC specification
Item
Range
¡ ¾
VCC
0 ~ 6.0V
0.25V
¡ ¾
RESETB
0 ~ 12.5V
0.5V
K-port
D-port
0 ~ 0.2VCC(Low)
0.8VCC ~ VCC (High)
4 - 3
Chapter 4. EPROM
EPROM read mode (1/2)
For device verify or read.
If you set Lock bit, output data is always FF.
14.5clocks
¨ ç ¨ è
2us at 500KHz
¨ ô ¨ õ
OSC
CK1
CK2
CK3
6V
0V
VCC
RESETB
12.5V
0110
0000
1101
0000
1101
0000
1101
0000
1101
K3 ~ K0
D4 ~ D0
AH AL
OH OL AH AL
OH OL AH AL
OH OL AH AL
OH OL
Addr. 0
Addr. 1
Addr. 2
Addr. 3
1
2
3
AH : High Address (A9~5) Input Latch
AL : Low Address (A4~0) Input Latch
OH : High Data (D7~4) Output
OL : Low Data (D3~0) Output
* Note : 1. AH, AL, DH, DL Inputs released at 100~200nS after OSC rising edge and
width is 1OSC cycle ( if OSC is 500KHz, width is 2uS ).
EPROM read mode (2/2)
START
¨ ç
Reset
(Set EPROM read mode)
Address=First address
¨ è
Set address
Read data
¨ é
Address ++
Address > Last address
RESETB=0V
VCC=0V
END
4 - 4
Chapter 4. EPROM
EPROM write mode (1/2)
14.5clocks
2us at 500KHz
¨ ç ¨ è
¨ ô ¨ õ
OSC
CK1
CK2
CK3
6V
0V
VCC
RESETB
12.5V
9.5V
PGM Write ( 0110 )
0000
1000
1110
1101
0000
1000
K3 ~ K0
D4 ~ D0
AH AL DH DL
OH OL AH AL DH DL
10times Repeat
12us X 10 = 120us
Verify
Next Write
1
2
3
4
AH : High bit Address Input Latch
AL : Low bit Address Input Latch
DH : High bit Data Input Latch
DL : Low bit Data Input Latch
OH : High bit Data Output
OL : Low bit Data Output
* Note : 1. AH, AL, DH, DL Inputs are released at 100~200nS after OSC rising edge and
width is 1OSC cycle ( if OSC is 500KHz, width is 2uS ).
EPROM write mode (2/2)
START
¨ é
EPROM write
(Write one more time)
¨ ç
Reset
(Set EPROM write mode)
Address ++
Address=First address
No
Address > Last address
Yes
¨ è
Set address & data
Count=0
RESETB=0V
VCC=0V
Pass
EPROM read mode
Verify all
¨ é
EPROM write
Repeat until near 100uS.
When 500KHz OSC1, repeat 10
times (12uS*10=120uS)
Fail
Device fail
Device OK
Count ++
RESETB=0V
VCC=0V
Pass
¨ ê
Verify
Fail
END
No
Yes
Count=25?
4 - 5
Chapter 4. EPROM
Lock bit write mode (1/2)
14.5clocks
¨ ç ¨ è
2us at 500KHz
¨ ô ¨ õ
OSC
CK1
CK2
CK3
6V
0V
VCC
RESETB
K3 ~ K0
12.5V
Lock Write ( 0100 )
0000
1110
10 times Repeat
12us X 10 = 120us
Lock bit write
1
2
3
Lock bit write mode (2/2)
START
¨ ç
(Set Lock bit write mode)
Reset
¨ è
Wait cycle
Count=0
*1 Repeat until near 100uS.
When 500KHz OSC1, repeat 10times
(12uS * 10 = 120uS)
¨ é
Write cycle *1
Count++
No
Count=10?
Yes
RESETB=0V
VCC=0V
END
4 - 6
Chapter 4. EPROM
Lock bit read mode (1/2)
14.5clocks
¨ ç ¨ è
2us at 500KHz
¨ ô ¨ õ
OSC1
6V
0V
VCC
12.5V
Lock Read ( 0101 )
Lock bit output
1
2
Lock bit read mode (2/2)
START
¨ ç
(Set Lock bit read mode)
Reset
¨ è
Read Lock bit (D5)
RESETB=0V
VCC=0V
END
4 - 7
Chapter 4. EPROM
GMS34004T/112T/140T (Pin assignment & Package)
RESETB
GND
K0
1
2
3
4
5
6
7
8
16 VDD
16DIP (Standard TTL DIP Size)
15 OSC1
- Width 300mil
- Pin to pin 100mil
14
13
-
-
K1
K2
12 D5
11 D4
10 D3
K3
D0
D1
9
D2
K0
K1
K2
K3
D0
D1
D2
D3
D4
1
2
3
4
5
6
7
8
9
20
19
18
17
-
-
-
-
20DIP (Standard TTL DIP Size)
- Width 300mil
- Pin to pin 100mil
16 GND
15 RESETB
14 VDD
20SOP (Standard TTL SOP Size)
13 OSC1
12
11
-
-
D5 10
RESETB
1
2
3
4
5
6
7
8
9
24 VDD
24DIP (Skinny DIP Size)
GND
23 OSC1
- Width 300mil
- Pin to pin 100mil
-
-
22
21
20
19
-
-
-
-
-
-
24SOP (Standard SOP Size)
K0
K1
K2
18 D5
17 D4
16 D3
15 D2
14 D1
K3 10
D0 11
- 12
13
-
4 - 8
Chapter 4. EPROM
EPROM(KHz) mode
EPROM write only mode
14.5clocks
2us at 500KHz
¨ ç ¨ è
¨ ô ¨ õ
OSC
CK1
CK2
CK3
6V
0V
VCC
RESETB
12.5V
PGM Write ( 0110 )
0000
1000
1110
0000
1000
1110
K3 ~ K0
D4 ~ D0
AH AL DH DL
AH AL DH DL
10times Repeat
12us X 10 = 120us
Next Write
5times Repeat
EPROM write
4 - 9
Chapter 4. EPROM
GMS34004TM / 34112TM / 34140TM
Mode define
Item
Device operation
Modesetting
User mode
Execute User pgm
RESETB = 0 ~ 3V
Vcc=3V
RESETB
=12.5V
EPROM read mode
Address in, Data out
K3~0=0010
Vcc=6.0V
1Byte PGM Write Address in, Data in
2Byte PGM Write Address in, Data in
K3~0=0110
K3~0=0111
-
EPROM
Program
mode
RESETB
=12.5V
Vcc=6.0V
Program verify
Lock bit Write
Lock bit Read
Address in, Data out
Lock bit write(set D5 to 1)
Lock bit out
K3~0=0100
K3~0=0101
Lock bit
Program
mode
Vcc=6.0V,
Lock bit is D5.
(Default : unlock)
RESETB
=12.5V
4 - 10
Chapter 4. EPROM
Port define
Port Name
User Mode
EPROMMode
VDD
RESETB
OSC1
K0
3.0V
6.0V
Reset (0, 3.0V)
Clock input
K0(Input)
K1(Input)
K2(Input)
K3(Input)
D0(Output)
D1(Output)
D2(Output)
D3(Output)
D4(Output)
D5(Output)
0V
Vpp (0, 12.5V)
Clock input
K1
Read / Write Control
Address / Data Control
K2
K3
D0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Da0
Da1
Da2
Da3
-
Da4
Da5
Da6
Da7
-
D1
NMOS open drain I/O
in EPROM mode
D2
D3
D4
D5
Lock bit output
GND
* Undefined ports in this table are N.C (No Connection)
Programming data
Blank data
Device Name ROM Size
Lock bit Device address File address
(HEX)
GMS34004TK
GMS34112TK
GMS34140TK
512bytes
FF
Yes
Yes
Yes
0000 ~ 01FF
0000 ~ 03FF
0000 ~ 03FF
0000 ~ 01FF
0000 ~ 03FF
0000 ~ 03FF
1,024bytes
1,024bytes
FF
FF
- If lock bit is set, the EPROM of the device can not be read, because output is always FF.
- Input file : Intel Hexa format ( *.RHX )
4 - 11
Chapter 4. EPROM
Write / Read data conversion
¡ ê
- You must change MSB ~ LSB
- Example
LSB ~ MSB.
File / buffer data
Device (D3 ~ D0)
Hex
Binary (MSB~LSB)
Hex
Binary (MSB~LSB)
Write
Read
2C
E4
8D
0010 1100
1110 0100
1000 1101
34
27
B1
0011 0100
0010 0111
1011 0001
Checksum
- It is calculated from the Buffer of the programmer.
- Address range is the same as device address.
- Calculate mathod is the same as normal EPROM devices (ex:27C128, 256 etc)
Programming control
- OSC1 & RESETB control OTP device, so you must count OSC1 clocks in every state.
- K ports control the internal state of the OTP device(ex: Read, Write...).
- D5~D0 ports are NMOS open drain I/O in EPROM mode.
It must be pulled up by resistors (about 4.7~ 47K ohm).
- The frequency rate of the OSC1 clock is 10KHz ~ 500KHz.
You can hold OSC1 HIGH or LOW state when you need.
Programming DC specification
Item
Range
¡ ¾
VCC
0 ~ 6.0V
0.25V
¡ ¾
RESETB
0 ~ 12.5V
0.5V
K-port
D-port
0 ~ 0.2VCC(Low)
0.8VCC ~ VCC (High)
4 - 12
Chapter 4. EPROM
EPROM read mode (1/2)
For device verify or read.
If you set Lock bit, output data is all 'FF’
12Clock
8Clock
OSC1
Address setting
Data read
1
2
3
Data
Strobe
point
Data
Strobe
point
5Clock
5Clock
6V
0V
VCC
RESETB
12.5V
ROM Dump Mode ( 0010 )
K3 ~ K0
D4 ~ D0
D5
A9~A5
A4~A0
D7~D4
D3~D0
Port Operation
K Port Latch
High bit
Address
Latch
Low bit
Address
Latch
Sense
AMP.
Operation
High bit
Instruction
Output
Low bit
Instruction
Output
Repeat
EPROM read mode (2/2)
START
¨ ç
Reset
(Set EPROM read mode)
Address=First address
¨ è
Set address
Read data
¨ é
Address ++
Address > Last address
RESETB=0V
VCC=0V
END
4 - 13
Chapter 4. EPROM
EPROM write mode (1/4)
12Clock
8Clock
OSC1
1
2
2
6V
0V
VCC
RESETB
12.5V
PGM Write ( 0110 (1B))
0000
1000
K3 ~ K0
D4 ~ D0
A9~A5
A4~A0
D7~D4
D3~D0
High bit
Address
Latch
Low bit
Address
Latch
High bit
Instruction
Latch
Low bit
Instruction
Latch
K Port Latch
First Address Input
First Data Input
EPROM write mode (2/4)
OSC1
3
3
4
6V
VCC
12.5V
RESETB
1110
1110
1101
K3 ~ K0
D4 ~ D0
Verify
EPROM write time
4 - 14
Chapter 4. EPROM
EPROM write mode (3/4)
OSC1
4
2
2
Data
Data
Strobe
point
Strobe
point
5Clock
5Clock
6V
VCC
Verify
12.5V
RESETB
1101
0000
1000
K3 ~ K0
D4 ~ D0
A9~A5
A4~A0
D7~D4
D3~D0
D7~D4
D3~D0
High bit
Instruction
Output
Low bit
Instruction
Output
High bit
Address
Latch
Low bit
Address
Latch
High bit
Instruction
Latch
Low bit
Instruction
Latch
Next Address Input
Next Data Input
EPROM write mode (4/4)
START
¨ é
EPROM write
(Write one more time)
¨ ç
Reset
(Set EPROM write mode)
Address ++
Address=First address
No
Address > Last address
Yes
¨ è
Set address & data
Count=0
RESETB=0V
VCC=0V
Pass
EPROM read mode
Verify all
¨ é
EPROM write
Repeat until near 100uS.
When 4MHz OSC1, repeat 10
times (12uS*10=120uS)
Fail
Device fail
Device OK
Count ++
RESETB=0V
VCC=0V
Pass
Yes
¨ ê
Verify
Fail
END
No
Count=25?
4 - 15
Chapter 4. EPROM
Lock bit write mode (1/3)
12Clock
8Clock
OSC1
1
2
2
6V
0V
VCC
RESETB
12.5V
EPROM Mode Lock Write ( 0100 )
0000
0000
K3 ~ K0
K Port Latch
Lock bit write mode (2/3)
OSC1
3
4
6V
VCC
RESETB
K3 ~ K0
12.5V
1110
1100
Write cycle
Repeat 2 times
Repeat 10 times
Lock bit Write
4 - 16
Chapter 4. EPROM
Lock bit write mode (3/3)
START
¨ ç
(Set Lock bit write mode)
Reset
¨ è
Wait cycle
Count=0
*1 Repeat until near 100uS.
When 4MHz OSC1, repeat 10 times
(12uS * 10 = 120uS)
¨ é
Write cycle *1
Delay cycle
¨ ê
(Repeat 2 times)
Count++
No
Count=10
Yes
RESETB=0V
VCC=0V
END
4 - 17
Chapter 4. EPROM
Lock bit read mode (1/2)
12Clock
8Clock
OSC1
1
2
3
You can strobe at any time from here
6V
0V
VCC
RESETB
K3 ~ K0
D5
12.5V
Lock Read Mode ( 0101 )
1101
1101
Lock bit output
K Port Latch
Lock bit read mode (2/2)
START
¨ ç
(Set Lock bit read mode)
Reset
¨ è
Wait cycle
¨ é
Read Lock bit (D5)
RESETB=0V
VCC=0V
END
4 - 18
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