TJ2132GQ_技术文档

2.0A Low Output Voltage Ultra LDO Regulator

TJ2132

FEATURES

 Works with 1.1V ~ 5.5V V_IN

 Ultra Low Dropout Voltage

 Low Quiescent Current

SOP8-PP

 Excellent Line and Load Regulation

 Guaranteed Output Current of 2.0A

 Adjustable Output Voltage Down to 0.6V

 V_OUTPower OK Signal

 Programmable Soft-Start

 Logic Controlled Shutdown Option

 Over-Temperature/Over-Current Protection

 -40℃ to 125℃ Junction Temperature Range

DFN 3x3-8L

APPLICATION

 Motherboards and Graphic Cards

 Microprocessor and Chipset Power Supplies

 Peripheral Cards

 Low Voltage Digital ICs

 High Efficiency Linear Regulators

 SMPS Post Regulators

DESCRIPSION

The TJ2132 is a 2.0A high performance ultra low-dropout

ORDERING INFORMATION

linear regulator ideal for powering core voltages of low-

power microprocessors. The TJ2132 implements a dual

supply configuration allowing for very low output

impedance. The TJ2132 requires a bias input supply and a

main input supply, allowing for ultra-low input voltages on

the main supply rail. The input supply operates from 1.1V

to 5.5V and the bias supply requires between 2.7V and 5.5V

for proper operation. The Soft-Start reduces inrush current

of the load capacitors and minimizes stress on the input

power source during start-up. The TJ2132 delivers high

current and ultra-low-dropout output voltage as low as 0.6V

for applications where V_OUTis very close to V_IN. The TJ2132

is developed on a CMOS technology which allows low

quiescent current operation independent of output current.

This technology also allows the TJ2132 to operate under

extremely low dropout conditions.

Device

Package

SOP8-PP

TJ2132GDP

DFN 3x3-8L

TJ2132GQ

OPERATING RATINGS

CHARACTERISTIC

SYMBOL

MIN.

MAX.

UNIT

Recommend Operating Input Voltage

Recommend Operating Bias Voltage

Enable Input Voltage

V_IN

V_BIAS

1.1

V_OUT+2.1

0

5.5

125

V

V_EN

V

℃

Operating Junction Temperature Range

Package Thermal Resistance^*

^*Calculated from package in sill air, mounted to 2.6mm X 3.5mm(minimum foot print) 2 layer PCB without thermal vias per JESD51 standards.

T_JOPR

-40

℃/W

Ɵ_JA-SOP8-PP

68

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2.0A Low Output Voltage Ultra LDO Regulator

TJ2132

MAXIMUM RATINGS

CHARACTERISTIC

Lead Temperature (Soldering, 5 sec)

Storage Temperature Range

SYMBOL

T_SOL

MIN.

-65

MAX.

260

UNIT

℃

T_STG

150

ORDERING INFORMATION

Compliance

Package

Order No.

Description

Package Marking

Supplied As

2.0A, Enable,

Adjustable, Power OK,

Soft start

SOP8-PP

TJ2132GDP

TJ2132G

RoHS, Halogen Free

Reel

2.0A, Enable,

Adjustable, Power OK,

Soft start

DFN 3x3-8L

TJ2132GQ

2132

Reel

ORDERING INFORMATION (Continued)

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2.0A Low Output Voltage Ultra LDO Regulator

TJ2132

PIN CONFIGURATION

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

POK

EN

GND

FB

Top view

IN

OUT

SS

BIAS

SOP8-PP

DFN 3x3-8L

PIN DESCRIPTION

Pin No.

Pin Name

Pin Function

Power OK Indication. This pin is an Open-drain output and is set high impedance

once V_OUTreaches 92% of its rating voltage.

1

2

3

4

5

6

7

8

-

POK

EN

Enable Input. Pulling this pin below 0.4V turns the regulator off.

Do not float.

Power Input. This pin is the drain input to the power device that supply current

to output pin.

IN

Supply Input for Internal Circuit. Input Bias Voltage for powering all circuitry on

the regulator except the output power TR.

BIAS

SS

Soft-Start Pin. Connect a capacitor between this pin and the ground to

determine the soft-start time. If soft-start is not needed, the SS pin can be left

floating. (Do not connect to ground directly.)

OUT

FB

Power Output. This pin is power output of the device.

Feedback Voltage. A resistor divider from the output to GND is used to set the

regulation voltage as V_OUT= 0.6V x (1+R2/R1)

GND

Ground

Thermal Exposed

PAD

Connect to Ground.

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2.0A Low Output Voltage Ultra LDO Regulator

TJ2132

BLOCK DIAGRAM

TYPICAL APPLICATION

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2.0A Low Output Voltage Ultra LDO Regulator

TJ2132

ELECTRICAL CHARACTERISTICS

Unless otherwise specified: V_BIAS= 5V, V_IN= V_O(NOM)+ 0.5V, V_EN=V_BIAS, I_L= 10 mA, T_J=25℃.

PARAMETER

SYMBOL

V_IN

TEST CONDITION

MIN.

1.1

TYP.

MAX. UNIT

Power Input Voltage

V_OUT=V_REF

-

5.5

V

V_OUT=V_REF

V_OUT>V_REF

2.7

5.5

V

Bias Input Voltage

V_BIAS

V_OUT+2.1

V_BIAS=V_IN=V_EN=5.0V, I_OUT=10mA,

V_OUT=V_REF

Reference Voltage

V_REF

0.588

0.6

0.612

0.10

0.35

V

V_INLine Regulation^{(Note 1)}

V_BIASLine Regulation^{(Note 2)}

Load Regulation^{(Note 3)}

ΔV_LINE(IN)

V_OUT+0.5V<V_IN<5.5V, I_OUT=10mA

-

0.02

0.05

%/V

%/A

ΔV_LINE(BIAS)V_IN=3.3V, I_OUT=10mA, V_OUT=V_REF

10mA < I_L<2A, V_BIAS=V_IN=V_EN=5.0V,

V_OUT=V_REF

ΔV_LOAD

I_L= 0.5A, V_BIAS=V_EN=5.0V, V_OUT=V_REF

-

65

130

250

0.1

100

180

380

0.5

Dropout Voltage

V_DROP

mV

I_L= 1.0A, V_BIAS=V_EN=5.0V, V_OUT=V_REF

I_L= 2.0A, V_BIAS=V_EN=5.0V, V_OUT=V_REF

I_L= 10mA

mA

uA

I_GND1

Ground Pin Current^{(Note 4)}

I_L= 2.0 A

0.5

I_GND2

Logic High V_IH

Logic Low V_IL

V_EN< 0.4 V, POK=open ^(Note5)

-

0.1

1.0

Output=High

Output=Low

1.5

-

V

Enable Threshold

0.4

EN Input Current

I_EN

V_EN=V_BIAS=5.0V

-

0.5

-

uA

%

FB Power OK Threshold

Power OK Hysteresis

OCP Threshold Level

V_POKTH

V_POKHYS

I_OCP

V_BIAS=V_IN=V_EN=5.0V, V_OUT=V_REF

92

7

-

3.5

165

20

A

℃

Thermal Shutdown Temperature T_SD

Thermal Shutdown Hysteresis ΔT_SD

-

Note 1. Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the

input line voltage.

Note 2. Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the

bias line voltage.

Note 3. Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in

load current. Regulation is measured at constant junction temperature by using a 10ms current pulse. Devices are

tested for load regulation in the load range from 10mA to 2.0A

Note 4. I_GND= I_BIAS+ (I_IN– I_OUT). The total current drawn from the supply is the sum of the load current plus the ground

current.

Note 5. When POK pin is applied to V_BIASthrough the resistor R3, I_GND2should be added to the bias current (V_BIAS- V_POK) / R3.

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2.0A Low Output Voltage Ultra LDO Regulator

TYPICAL OPERATING CHARACTERISTICS

- TEST Circuit

TJ2132

Circuit #01

Circuit #03

Circuit #05

Circuit #02

Circuit #04

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2.0A Low Output Voltage Ultra LDO Regulator

TJ2132

V_IN

V_OUT

POK

V_OUT

POK

- V_IN: 1V/div, V_OUT: 1V/div, POK: 5V/div, 500us/div

Start up @ I_OUT=10mA, Circuit #1

- V_IN: 1V/div, V_OUT: 1V/div, POK: 5V/div, 500us/div

Start up @ I_OUT=2A, Circuit #1

(C_ff=10nF, C_SS=470pF, R1=R2=10kΩ, V_EN=V_BIAS=5.0V)

V_IN

V_BIAS

V_OUT

- V_IN: 2V/div, V_BIAS: 5V/div, V_OUT: 500mV/div, 500us/div

Start up @ I_OUT=10mA, Circuit #2

- V_IN: 2V/div, V_BIAS: 5V/div, V_OUT: 500mV/div, 500us/div

Start up @ I_OUT=2A, Circuit #2

(C_ff=10nF, C_SS=470pF, R1=R2=10kΩ, V_IN=1.7V, V_EN=5.0V)

V_EN

V_OUT

POK

V_OUT

POK

- V_EN: 2V/div, V_OUT: 500mV/div, POK: 2V/div, 500us/div

Start up @ I_OUT=10mA, Circuit #1

- V_EN: 2V/div, V_OUT: 500mV/div, POK: 2V/div, 500us/div

Start up @ I_OUT=2A, Circuit #1

(C_ff=10nF, C_SS=470pF, R1=R2=10kΩ, V_IN=1.7V, V_BIAS=5.0V)

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2.0A Low Output Voltage Ultra LDO Regulator

TJ2132

V_BIAS

V_EN

470pF

1nF

470pF

1nF

5.6nF

10nF

5.6nF

10nF

V_OUT

2.7nF

- V_BIAS: 3V/div, V_EN: 2V/div, V_OUT: 500mV/div, 2ms/div

Start up @ I_OUT=10mA, Circuit #1

- V_BIAS: 3V/div, V_EN: 2V/div, V_OUT: 500mV/div, 2ms/div

Start up @ I_OUT=2A, Circuit #1

(C_SSis varied, C_ff=10nF, R1=R2=10kΩ, V_IN=1.7V, V_EN=V_BIAS=5.0V)

(CSS is varied, C_ff=10nF, R1=R2=10kΩ, V_IN=1.7V, V_EN=V_BIAS=5.0V)

10nF

100nF

V_EN

100nF

10nF

330nF

V_OUT

- V_EN: 2V/div, V_OUT: 500mV/div, 1ms/div

Start up @ I_OUT=10mA, Circuit #1

- V_EN: 2V/div, V_OUT: 500V/div, 2ms/div

Start up @ I_OUT=10mA, Circuit #5

(C_ffis varied, C_SS=open, R1=R2=10kΩ, V_IN=1.7V, V_BIAS=5.0V)

(C_delayis varied, C_SS=open, R1=R2=10kΩ, V_IN=1.7V, V_BIAS=5.0V)

V_OUT

I_OUT

- V_OUT: 100mV/div, I_OUT: 1A/div, 200us/div

Load Transient Response

- V_OUT: 100mV/div, I_OUT: 1A/div, 200us/div

Load Transient Response

(C_ff=10nF, C_SS=470pF, R1=R2=10kΩ, V_IN=1.7V, V_EN=V_BIAS=5.0V)

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2.0A Low Output Voltage Ultra LDO Regulator

TJ2132

- x-axis: V_OUT[V], y-axis: V_IN[V]

V_OUTvs. V_IN@ V_BIAS=5.5V

- x-axis: V_OUT[V], y-axis: V_BIAS[V]

V_OUTvs. V_BIAS@ V_IN=5.5V

350

300

250

200

150

100

50

350

300

250

200

150

100

50

V_OUT=2.5V

V_OUT=1.8V

V_OUT=1.2V

VBIAS=5V

VBIAS=3.3V

0

0.5

1.5

2

IOUT¹[A]

0

0.5

1

1.5

2

IOUT [A]

Dropout Voltage

V_DROPvs. V_BIAS@ V_OUT=1.2V

350

300

250

200

150

100

50

350

300

250

200

150

100

50

VBIAS=5V

VBIAS=3.9V

VBIAS=4.6V

0

0.5

1

1.5

2

0

0.5

1

1.5

2

IOUT [A]

V_DROPvs. V_BIAS@ V_OUT=1.8V

V_DROPvs. V_BIAS@ V_OUT=2.5V

Aug. 2014 – Rev.1.1.3

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2.0A Low Output Voltage Ultra LDO Regulator

TJ2132

APPLICATION INFORMATION

The TJ2132 is a high performance, low dropout linear regulator, designed for high current application that

requires fast transient response. The TJ2132 operates from two input supply voltages, significantly reducing

dropout voltage. The TJ2132 is designed so that a minimum of external component are necessary.

Bias Supply Voltage

The TJ2132 control circuitry is supplied by the BIAS pin which requires a very low bias current even at

the maximum output current level. A bypass capacitor on the bias pin is recommended to improve the

performance of the TJ2132 during line and load transient. A small ceramic capacitor from BIAS pin to

ground reduces high frequency noise that could be injected into the control circuitry from the bias rail.

In practical applications, a 1uF capacitor and smaller valued capacitors such as 0.01uF or 0.001uF in

parallel with that larger capacitor may be used to decouple the bias supply. The BIAS input voltage must

be 2.1V above the output voltage, with a minimum BIAS input voltage of 2.7V.

Adjustable Regulator Design

An adjustable output device has output voltage range of 0.6V to V_BIAS-2.1V. To obtain a desired output

voltage, the following equation can be used two external resistors as presented in the typical application

circuit. The resistor values are given by;

푅₂= 푅₁× (^푉^푂푈푇− ꢀ)

(1)

0.6

It is suggested to use R1 values lower than 10kΩ to obtain better load transient performances. Even,

higher values up to 100 kΩ are suitable.

Enable

The TJ2132 feature an active high Enable input (EN) that allows on/off control of the regulator. The

enable function of TJ2132 has hysteresis characteristics. Pulling V_ENlower than 0.4V disables the chip.

Pulling V_ENhigher than 1.5V enables the output voltage.

Supply Power Sequencing

In common applications where the power on transient of V_INand V_BIASvoltages are not particularly fast

(Tr > 100us), no power sequencing is required. Where voltage transient input is very fast(Tr<100us), it

is recommended to have the V_INvoltage present before or, at least, at the same time as the V_BIASvoltage

in order to avoid over voltage spikes during the power on transient.

Output Capacitors

The TJ2132 requires an of output capacitance to maintain stability. The output capacitor must meet

both requirements for minimum amount of capacitance and ESR in all LDOs application. The TJ2132 is

designed specifically to work with low ESR ceramic output capacitor in space-saving and performance

consideration. Using a ceramic capacitor which value is at least 10uF on the TJ2132 output ensures

stability. Output capacitor of larger capacitance can reduce noise and improve load transient response,

stability, and PSRR. A minimum ceramic capacitor over than 10uF should be very closely placed to the

output voltage pin of the TJ2132.

Input Capacitor

A large bulk capacitance over than 10uF should be closely placed to the input supply pin of the TJ2132

to ensure that the input supply voltage does not sag. Also a minimum of 10uF ceramic capacitor is

recommended to be placed directly next to the IN pin. It allows for the device being some distance from

Aug. 2014 – Rev.1.1.3

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2.0A Low Output Voltage Ultra LDO Regulator

TJ2132

any bulk capacitor on the rail. Additionally, input droop due to load transients is reduced, improving load

transient response. Additional capacitance may be added if required by the application.

Soft Start Time

The TJ2132 has an internal current source that charges an external slow start capacitor to implement a

slow start time. Equation 2 and Table 1 shows how to select a slow start capacitor based on an expected

slow start time. The R is 302kΩ, V_Ois 0.6V and i(t) is 40nA.

( )

_ꢁꢁ(ꢂ) =ꢃ−ꢄꢅ_ꢁꢁ× ꢆꢇ ^{ꢈ ꢉ ꢊ}

(2)

푉

푂

Table 1. Capacitor Values for the soft-start time

C_SS

Calculated Soft-Start Time

Measured Soft-Start Time

470pF

1nF

0.56ms

1.18ms

3.18ms

6.6ms

0.64ms

1.23ms

3.44ms

7.1ms

2.7nF

5.6nF

10nF

11.8ms

12.0ms

Decoupling (Bypass) Capacitor

In very electrically noisy environments, it is recommended that additional ceramic capacitors be placed

from VIN to GND. The use of multiple lower value ceramic capacitors in parallel with output capacitor also

allows to achieve better transient performance and stability if required by the application. (See Fig.1)

Feed-Forward Capacitor

To get the higher PSRR than the inherent performance of TJ2132, it is recommended that additional

ceramic feed-forward capacitor be placed from OUT pin to FB pin. The capacitance of feed-forward

capacitor with range of 10pF to 1uF allows to achieve better PSRR performance when required by the

application. (See Fig.1)

Fig.1 Application with Decoupling & Feed-Forward Capacitor

Maximum Output Current Capability

The TJ2132 can deliver a continuous current of 2A over the full operating junction temperature range.

However, the output current is limited by the restriction of power dissipation which differs from packages.

A heat sink may be required depending on the maximum power dissipation and maximum ambient

Aug. 2014 – Rev.1.1.3

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2.0A Low Output Voltage Ultra LDO Regulator

TJ2132

temperature of application. With respect to the applied package, the maximum output current of 2A may

be still undeliverable due to the restriction of the power dissipation of TJ2132. Under all possible

conditions, the junction temperature must be within the range specified under operating conditions.

The temperatures over the device are given by:

T_C= T_A+ P_DX θ_CA

T_J= T_C+ P_DX θ_JC

T_J= T_A+ P_DX θ_JA

where T_Jis the junction temperature, T_Cis the case temperature, T_Ais the ambient temperature, P_Dis the

total power dissipation of the device, θ_CAis the thermal resistance of case-to-ambient, θ_JCis the thermal

resistance of junction-to-case, and θ_JAis the thermal resistance of junction to ambient.

The total power dissipation of the device is given by:

P_D= P_IN– P_OUT= {(V_INX I_IN)+(V_BIASX I_BIAS)} – (V_OUTX I_OUT

)

where I_GNDis the operating ground current of the device which is specified at the Electrical Characteristics.

The maximum allowable temperature rise (T_Rmax) depends on the maximum ambient temperature (T_Amax

of the application, and the maximum allowable junction temperature (T_Jmax):

)

T_Rmax= T_Jmax– T_Amax

The maximum allowable value for junction-to-ambient thermal resistance, θ_JA, can be calculated using the

formula:

θ_JA= T_Rmax/ P_D

TJ2132 is available in SOP8-PP packages. The thermal resistance depends on amount of copper area or

heat sink, and on air flow.

If proper cooling solution such as heat sink, copper plane area, or air flow is applied, the maximum

allowable power dissipation could be increased. However, if the ambient temperature is increased, the

allowable power dissipation would be decreased.

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2.0A Low Output Voltage Ultra LDO Regulator

TJ2132

The graph above is valid for the thermal impedance specified in the Absolute Maximum Ratings section

on page 1.

The θ_JAcould be decreased with respect to the copper plane area. So, the specification of maximum

power dissipation for an application is fixed, the proper plane area could be estimated by following

graphs. Wider copper plane area leads lower θ_JA.

The maximum allowable power dissipation is also influenced by the ambient temperature. With the θ_JA-

Copper plane area relationship, the maximum allowable power dissipation could be evaluated with

respect to the ambient temperature. As shown in graph, the higher copper plane area leads θ_JA. And the

higher ambient temperature leads lower maximum allowable power dissipation.

Aug. 2014 – Rev.1.1.3

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型号：	TJ2132GQ
厂家：	HTC KOREA TAEJIN TECHNOLOGY CO.
描述：	2.0A Low Output Voltage Ultra LDO Regulator
文件：	总13页 (文件大小：1904K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TJ2132GQ [HTC]

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