TJ2132GQ [HTC]
2.0A Low Output Voltage Ultra LDO Regulator;型号: | TJ2132GQ |
厂家: | HTC KOREA TAEJIN TECHNOLOGY CO. |
描述: | 2.0A Low Output Voltage Ultra LDO Regulator |
文件: | 总13页 (文件大小:1904K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
2.0A Low Output Voltage Ultra LDO Regulator
TJ2132
FEATURES
Works with 1.1V ~ 5.5V VIN
Ultra Low Dropout Voltage
Low Quiescent Current
SOP8-PP
Excellent Line and Load Regulation
Guaranteed Output Current of 2.0A
Adjustable Output Voltage Down to 0.6V
VOUT Power OK Signal
Programmable Soft-Start
Logic Controlled Shutdown Option
Over-Temperature/Over-Current Protection
-40℃ to 125℃ Junction Temperature Range
DFN 3x3-8L
APPLICATION
Motherboards and Graphic Cards
Microprocessor and Chipset Power Supplies
Peripheral Cards
Low Voltage Digital ICs
High Efficiency Linear Regulators
SMPS Post Regulators
DESCRIPSION
The TJ2132 is a 2.0A high performance ultra low-dropout
ORDERING INFORMATION
linear regulator ideal for powering core voltages of low-
power microprocessors. The TJ2132 implements a dual
supply configuration allowing for very low output
impedance. The TJ2132 requires a bias input supply and a
main input supply, allowing for ultra-low input voltages on
the main supply rail. The input supply operates from 1.1V
to 5.5V and the bias supply requires between 2.7V and 5.5V
for proper operation. The Soft-Start reduces inrush current
of the load capacitors and minimizes stress on the input
power source during start-up. The TJ2132 delivers high
current and ultra-low-dropout output voltage as low as 0.6V
for applications where VOUT is very close to VIN. The TJ2132
is developed on a CMOS technology which allows low
quiescent current operation independent of output current.
This technology also allows the TJ2132 to operate under
extremely low dropout conditions.
Device
Package
SOP8-PP
TJ2132GDP
DFN 3x3-8L
TJ2132GQ
OPERATING RATINGS
CHARACTERISTIC
SYMBOL
MIN.
MAX.
UNIT
Recommend Operating Input Voltage
Recommend Operating Bias Voltage
Enable Input Voltage
VIN
VBIAS
1.1
VOUT+2.1
0
5.5
5.5
5.5
125
V
V
VEN
V
℃
Operating Junction Temperature Range
Package Thermal Resistance*
* Calculated from package in sill air, mounted to 2.6mm X 3.5mm(minimum foot print) 2 layer PCB without thermal vias per JESD51 standards.
TJOPR
-40
℃/W
ƟJA-SOP8-PP
68
Aug. 2014 – Rev.1.1.3
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HTC
2.0A Low Output Voltage Ultra LDO Regulator
TJ2132
MAXIMUM RATINGS
CHARACTERISTIC
Lead Temperature (Soldering, 5 sec)
Storage Temperature Range
SYMBOL
TSOL
MIN.
-65
MAX.
260
UNIT
℃
℃
TSTG
150
ORDERING INFORMATION
Compliance
Package
Order No.
Description
Package Marking
Supplied As
2.0A, Enable,
Adjustable, Power OK,
Soft start
SOP8-PP
TJ2132GDP
TJ2132G
RoHS, Halogen Free
RoHS, Halogen Free
Reel
2.0A, Enable,
Adjustable, Power OK,
Soft start
DFN 3x3-8L
TJ2132GQ
2132
Reel
ORDERING INFORMATION (Continued)
Aug. 2014 – Rev.1.1.3
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HTC
2.0A Low Output Voltage Ultra LDO Regulator
TJ2132
PIN CONFIGURATION
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
POK
EN
GND
FB
Top view
IN
OUT
SS
BIAS
SOP8-PP
DFN 3x3-8L
PIN DESCRIPTION
Pin No.
Pin Name
Pin Function
Power OK Indication. This pin is an Open-drain output and is set high impedance
once VOUT reaches 92% of its rating voltage.
1
2
3
4
5
6
7
8
-
POK
EN
Enable Input. Pulling this pin below 0.4V turns the regulator off.
Do not float.
Power Input. This pin is the drain input to the power device that supply current
to output pin.
IN
Supply Input for Internal Circuit. Input Bias Voltage for powering all circuitry on
the regulator except the output power TR.
BIAS
SS
Soft-Start Pin. Connect a capacitor between this pin and the ground to
determine the soft-start time. If soft-start is not needed, the SS pin can be left
floating. (Do not connect to ground directly.)
OUT
FB
Power Output. This pin is power output of the device.
Feedback Voltage. A resistor divider from the output to GND is used to set the
regulation voltage as VOUT= 0.6V x (1+R2/R1)
GND
Ground
Thermal Exposed
PAD
Connect to Ground.
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2.0A Low Output Voltage Ultra LDO Regulator
TJ2132
BLOCK DIAGRAM
TYPICAL APPLICATION
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2.0A Low Output Voltage Ultra LDO Regulator
TJ2132
ELECTRICAL CHARACTERISTICS
Unless otherwise specified: VBIAS = 5V, VIN = VO(NOM) + 0.5V, VEN=VBIAS, IL = 10 mA, TJ=25℃.
PARAMETER
SYMBOL
VIN
TEST CONDITION
MIN.
1.1
TYP.
MAX. UNIT
Power Input Voltage
VOUT=VREF
-
-
5.5
V
VOUT=VREF
VOUT>VREF
2.7
5.5
5.5
V
V
Bias Input Voltage
VBIAS
VOUT+2.1
VBIAS=VIN=VEN=5.0V, IOUT=10mA,
VOUT=VREF
Reference Voltage
VREF
0.588
0.6
0.612
0.10
0.10
0.35
V
VIN Line Regulation(Note 1)
VBIAS Line Regulation(Note 2)
Load Regulation(Note 3)
ΔVLINE(IN)
VOUT+0.5V<VIN<5.5V, IOUT=10mA
-
-
-
0.02
0.02
0.05
%/V
%/V
%/A
ΔVLINE(BIAS) VIN=3.3V, IOUT=10mA, VOUT=VREF
10mA < IL <2A, VBIAS=VIN=VEN=5.0V,
VOUT=VREF
ΔVLOAD
IL = 0.5A, VBIAS=VEN=5.0V, VOUT=VREF
-
-
-
-
-
65
130
250
0.1
0.1
100
180
380
0.5
Dropout Voltage
VDROP
mV
IL = 1.0A, VBIAS=VEN=5.0V, VOUT=VREF
IL = 2.0A, VBIAS=VEN=5.0V, VOUT=VREF
IL = 10mA
mA
mA
uA
IGND1
Ground Pin Current(Note 4)
IL = 2.0 A
0.5
IGND2
Logic High VIH
Logic Low VIL
VEN < 0.4 V, POK=open (Note5)
-
0.1
1.0
Output=High
Output=Low
1.5
-
-
-
-
V
V
Enable Threshold
0.4
EN Input Current
IEN
VEN=VBIAS=5.0V
-
-
-
-
-
-
-
0.5
-
uA
%
%
FB Power OK Threshold
Power OK Hysteresis
OCP Threshold Level
VPOKTH
VPOKHYS
IOCP
VBIAS=VIN=VEN=5.0V, VOUT=VREF
VBIAS=VIN=VEN=5.0V, VOUT=VREF
VBIAS=VIN=VEN=5.0V, VOUT=VREF
92
7
-
-
3.5
165
20
A
℃
℃
Thermal Shutdown Temperature TSD
Thermal Shutdown Hysteresis ΔTSD
-
-
Note 1. Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the
input line voltage.
Note 2. Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the
bias line voltage.
Note 3. Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in
load current. Regulation is measured at constant junction temperature by using a 10ms current pulse. Devices are
tested for load regulation in the load range from 10mA to 2.0A
Note 4. IGND = IBIAS + (IIN – IOUT). The total current drawn from the supply is the sum of the load current plus the ground
current.
Note 5. When POK pin is applied to VBIAS through the resistor R3, IGND2 should be added to the bias current (VBIAS - VPOK ) / R3.
Aug. 2014 – Rev.1.1.3
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2.0A Low Output Voltage Ultra LDO Regulator
TYPICAL OPERATING CHARACTERISTICS
- TEST Circuit
TJ2132
Circuit #01
Circuit #03
Circuit #05
Circuit #02
Circuit #04
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2.0A Low Output Voltage Ultra LDO Regulator
TJ2132
VIN
VIN
VOUT
POK
VOUT
POK
- VIN: 1V/div, VOUT: 1V/div, POK: 5V/div, 500us/div
Start up @ IOUT=10mA, Circuit #1
- VIN: 1V/div, VOUT: 1V/div, POK: 5V/div, 500us/div
Start up @ IOUT=2A, Circuit #1
(Cff=10nF, CSS=470pF, R1=R2=10kΩ, VEN=VBIAS=5.0V)
(Cff=10nF, CSS=470pF, R1=R2=10kΩ, VEN=VBIAS=5.0V)
VIN
VIN
VBIAS
VBIAS
VOUT
VOUT
- VIN: 2V/div, VBIAS: 5V/div, VOUT: 500mV/div, 500us/div
Start up @ IOUT=10mA, Circuit #2
- VIN: 2V/div, VBIAS: 5V/div, VOUT: 500mV/div, 500us/div
Start up @ IOUT=2A, Circuit #2
(Cff=10nF, CSS=470pF, R1=R2=10kΩ, VIN=1.7V, VEN=5.0V)
(Cff=10nF, CSS=470pF, R1=R2=10kΩ, VIN=1.7V, VEN=5.0V)
VEN
VEN
VOUT
POK
VOUT
POK
- VEN: 2V/div, VOUT: 500mV/div, POK: 2V/div, 500us/div
Start up @ IOUT=10mA, Circuit #1
- VEN: 2V/div, VOUT: 500mV/div, POK: 2V/div, 500us/div
Start up @ IOUT=2A, Circuit #1
(Cff=10nF, CSS=470pF, R1=R2=10kΩ, VIN=1.7V, VBIAS=5.0V)
(Cff=10nF, CSS=470pF, R1=R2=10kΩ, VIN=1.7V, VBIAS=5.0V)
Aug. 2014 – Rev.1.1.3
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2.0A Low Output Voltage Ultra LDO Regulator
TJ2132
VBIAS
VBIAS
VEN
VEN
470pF
1nF
470pF
1nF
5.6nF
10nF
5.6nF
10nF
VOUT
VOUT
2.7nF
2.7nF
- VBIAS: 3V/div, VEN: 2V/div, VOUT: 500mV/div, 2ms/div
Start up @ IOUT=10mA, Circuit #1
- VBIAS: 3V/div, VEN: 2V/div, VOUT: 500mV/div, 2ms/div
Start up @ IOUT=2A, Circuit #1
(CSS is varied, Cff=10nF, R1=R2=10kΩ, VIN=1.7V, VEN=VBIAS=5.0V)
(CSS is varied, Cff=10nF, R1=R2=10kΩ, VIN=1.7V, VEN=VBIAS=5.0V)
10nF
100nF
VEN
VEN
100nF
10nF
330nF
VOUT
VOUT
- VEN: 2V/div, VOUT: 500mV/div, 1ms/div
Start up @ IOUT=10mA, Circuit #1
- VEN: 2V/div, VOUT: 500V/div, 2ms/div
Start up @ IOUT=10mA, Circuit #5
(Cff is varied, CSS=open, R1=R2=10kΩ, VIN=1.7V, VBIAS=5.0V)
(Cdelay is varied, CSS=open, R1=R2=10kΩ, VIN=1.7V, VBIAS=5.0V)
VOUT
VOUT
IOUT
IOUT
- VOUT: 100mV/div, IOUT: 1A/div, 200us/div
Load Transient Response
- VOUT: 100mV/div, IOUT: 1A/div, 200us/div
Load Transient Response
(Cff=10nF, CSS=470pF, R1=R2=10kΩ, VIN=1.7V, VEN=VBIAS=5.0V)
(Cff=10nF, CSS=470pF, R1=R2=10kΩ, VIN=1.7V, VEN=VBIAS=5.0V)
Aug. 2014 – Rev.1.1.3
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2.0A Low Output Voltage Ultra LDO Regulator
TJ2132
- x-axis: VOUT [V], y-axis: VIN [V]
VOUT vs. VIN @ VBIAS=5.5V
- x-axis: VOUT [V], y-axis: VBIAS[V]
VOUT vs. VBIAS @ VIN=5.5V
350
300
250
200
150
100
50
350
300
250
200
150
100
50
VOUT=2.5V
VOUT=1.8V
VOUT=1.2V
VBIAS=5V
VBIAS=3.3V
0
0
0
0.5
1.5
2
IOUT1 [A]
0
0.5
1
1.5
2
IOUT [A]
Dropout Voltage
VDROP vs. VBIAS @ VOUT=1.2V
350
300
250
200
150
100
50
350
300
250
200
150
100
50
VBIAS=5V
VBIAS=5V
VBIAS=3.9V
VBIAS=4.6V
0
0
0
0.5
1
1.5
2
0
0.5
1
1.5
2
IOUT [A]
IOUT [A]
VDROP vs. VBIAS @ VOUT=1.8V
VDROP vs. VBIAS @ VOUT=2.5V
Aug. 2014 – Rev.1.1.3
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2.0A Low Output Voltage Ultra LDO Regulator
TJ2132
APPLICATION INFORMATION
The TJ2132 is a high performance, low dropout linear regulator, designed for high current application that
requires fast transient response. The TJ2132 operates from two input supply voltages, significantly reducing
dropout voltage. The TJ2132 is designed so that a minimum of external component are necessary.
Bias Supply Voltage
The TJ2132 control circuitry is supplied by the BIAS pin which requires a very low bias current even at
the maximum output current level. A bypass capacitor on the bias pin is recommended to improve the
performance of the TJ2132 during line and load transient. A small ceramic capacitor from BIAS pin to
ground reduces high frequency noise that could be injected into the control circuitry from the bias rail.
In practical applications, a 1uF capacitor and smaller valued capacitors such as 0.01uF or 0.001uF in
parallel with that larger capacitor may be used to decouple the bias supply. The BIAS input voltage must
be 2.1V above the output voltage, with a minimum BIAS input voltage of 2.7V.
Adjustable Regulator Design
An adjustable output device has output voltage range of 0.6V to VBIAS-2.1V. To obtain a desired output
voltage, the following equation can be used two external resistors as presented in the typical application
circuit. The resistor values are given by;
푅2 = 푅1 × (푉푂푈푇 − ꢀ)
(1)
0.6
It is suggested to use R1 values lower than 10kΩ to obtain better load transient performances. Even,
higher values up to 100 kΩ are suitable.
Enable
The TJ2132 feature an active high Enable input (EN) that allows on/off control of the regulator. The
enable function of TJ2132 has hysteresis characteristics. Pulling VEN lower than 0.4V disables the chip.
Pulling VEN higher than 1.5V enables the output voltage.
Supply Power Sequencing
In common applications where the power on transient of VIN and VBIAS voltages are not particularly fast
(Tr > 100us), no power sequencing is required. Where voltage transient input is very fast(Tr<100us), it
is recommended to have the VIN voltage present before or, at least, at the same time as the VBIAS voltage
in order to avoid over voltage spikes during the power on transient.
Output Capacitors
The TJ2132 requires an of output capacitance to maintain stability. The output capacitor must meet
both requirements for minimum amount of capacitance and ESR in all LDOs application. The TJ2132 is
designed specifically to work with low ESR ceramic output capacitor in space-saving and performance
consideration. Using a ceramic capacitor which value is at least 10uF on the TJ2132 output ensures
stability. Output capacitor of larger capacitance can reduce noise and improve load transient response,
stability, and PSRR. A minimum ceramic capacitor over than 10uF should be very closely placed to the
output voltage pin of the TJ2132.
Input Capacitor
A large bulk capacitance over than 10uF should be closely placed to the input supply pin of the TJ2132
to ensure that the input supply voltage does not sag. Also a minimum of 10uF ceramic capacitor is
recommended to be placed directly next to the IN pin. It allows for the device being some distance from
Aug. 2014 – Rev.1.1.3
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2.0A Low Output Voltage Ultra LDO Regulator
TJ2132
any bulk capacitor on the rail. Additionally, input droop due to load transients is reduced, improving load
transient response. Additional capacitance may be added if required by the application.
Soft Start Time
The TJ2132 has an internal current source that charges an external slow start capacitor to implement a
slow start time. Equation 2 and Table 1 shows how to select a slow start capacitor based on an expected
slow start time. The R is 302kΩ, VO is 0.6V and i(t) is 40nA.
( )
ꢁꢁ(ꢂ) =ꢃ−ꢄꢅꢁꢁ × ꢆꢇ ꢈ ꢉ ꢊ
(2)
푉
푂
Table 1. Capacitor Values for the soft-start time
CSS
Calculated Soft-Start Time
Measured Soft-Start Time
470pF
1nF
0.56ms
1.18ms
3.18ms
6.6ms
0.64ms
1.23ms
3.44ms
7.1ms
2.7nF
5.6nF
10nF
11.8ms
12.0ms
Decoupling (Bypass) Capacitor
In very electrically noisy environments, it is recommended that additional ceramic capacitors be placed
from VIN to GND. The use of multiple lower value ceramic capacitors in parallel with output capacitor also
allows to achieve better transient performance and stability if required by the application. (See Fig.1)
Feed-Forward Capacitor
To get the higher PSRR than the inherent performance of TJ2132, it is recommended that additional
ceramic feed-forward capacitor be placed from OUT pin to FB pin. The capacitance of feed-forward
capacitor with range of 10pF to 1uF allows to achieve better PSRR performance when required by the
application. (See Fig.1)
Fig.1 Application with Decoupling & Feed-Forward Capacitor
Maximum Output Current Capability
The TJ2132 can deliver a continuous current of 2A over the full operating junction temperature range.
However, the output current is limited by the restriction of power dissipation which differs from packages.
A heat sink may be required depending on the maximum power dissipation and maximum ambient
Aug. 2014 – Rev.1.1.3
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2.0A Low Output Voltage Ultra LDO Regulator
TJ2132
temperature of application. With respect to the applied package, the maximum output current of 2A may
be still undeliverable due to the restriction of the power dissipation of TJ2132. Under all possible
conditions, the junction temperature must be within the range specified under operating conditions.
The temperatures over the device are given by:
TC = TA + PD X θCA
TJ = TC + PD X θJC
TJ = TA + PD X θJA
where TJ is the junction temperature, TC is the case temperature, TA is the ambient temperature, PD is the
total power dissipation of the device, θCA is the thermal resistance of case-to-ambient, θJC is the thermal
resistance of junction-to-case, and θJA is the thermal resistance of junction to ambient.
The total power dissipation of the device is given by:
PD = PIN – POUT = {(VIN X IIN)+(VBIAS X IBIAS)} – (VOUT X IOUT
)
where IGND is the operating ground current of the device which is specified at the Electrical Characteristics.
The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax
of the application, and the maximum allowable junction temperature (TJmax):
)
TRmax = TJmax – TAmax
The maximum allowable value for junction-to-ambient thermal resistance, θJA, can be calculated using the
formula:
θJA = TRmax / PD
TJ2132 is available in SOP8-PP packages. The thermal resistance depends on amount of copper area or
heat sink, and on air flow.
If proper cooling solution such as heat sink, copper plane area, or air flow is applied, the maximum
allowable power dissipation could be increased. However, if the ambient temperature is increased, the
allowable power dissipation would be decreased.
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2.0A Low Output Voltage Ultra LDO Regulator
TJ2132
The graph above is valid for the thermal impedance specified in the Absolute Maximum Ratings section
on page 1.
The θJA could be decreased with respect to the copper plane area. So, the specification of maximum
power dissipation for an application is fixed, the proper plane area could be estimated by following
graphs. Wider copper plane area leads lower θJA.
The maximum allowable power dissipation is also influenced by the ambient temperature. With the θJA-
Copper plane area relationship, the maximum allowable power dissipation could be evaluated with
respect to the ambient temperature. As shown in graph, the higher copper plane area leads θJA. And the
higher ambient temperature leads lower maximum allowable power dissipation.
Aug. 2014 – Rev.1.1.3
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HTC
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