HX6228TSHT [HONEYWELL]
128K x 8 STATIC RAM-SOI HX6228; 128K x 8静态RAM - SOI HX6228型号: | HX6228TSHT |
厂家: | Honeywell |
描述: | 128K x 8 STATIC RAM-SOI HX6228 |
文件: | 总12页 (文件大小:153K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Military & Space Products
128K x 8 STATIC RAM—SOI
HX6228
FEATURES
RADIATION
OTHER
• Fabricated with RICMOS™ IV Silicon on Insulator (SOI) • Read/Write Cycle Times
≤ 16 ns (Typical)
≤ 25 ns (-55 to 125°C)
0.7 µm Process (Leff = 0.55 µm)
• Total Dose Hardness through 1x106 rad(SiO2)
• Neutron Hardness through 1x1014 cm-2
• Typical Operating Power <25 mW/MHz
• Asynchronous Operation
• Dynamic and Static Transient Upset Hardness
through 1x1011 rad (Si)/s
• CMOS or TTL Compatible I/O
• Single 5 V 10% Power Supply
• Packaging Options
• Dose Rate Survivability through <1x1012 rad(Si)/s
• Soft Error Rate of <1x10-10 upsets/bit-day in
Geosynchronous Orbit
- 32-Lead Flat Pack (0.820 in. x 0.600 in.)
- 40-Lead Flat Pack (0.775 in. x 0.710 in.)
• No Latchup
GENERAL DESCRIPTION
The 128K x 8 Radiation Hardened Static RAM is a high
performance 131,072 word x 8-bit static random access
memory with industry-standard functionality. It is fabricated
with Honeywell’s radiation hardened technology, and is
designed for use in systems operating in radiation environ-
ments. The RAM operates over the full military temperature
rangeandrequiresonlyasingle5V 10%powersupply.The
RAM is wire bond programmable for either TTL or CMOS
compatible I/O. Power consumption is typically less than 25
mW/MHz in operation, and less than 5 mW in the low power
disabled mode. The RAM read operation is fully asynchro-
nous, with an associated typical access time of 15 ns at 5V.
Honeywell’senhancedSOIRICMOS™IV(RadiationInsen-
sitive CMOS) technology is radiation hardened through the
useofadvancedandproprietarydesign,layoutandprocess
hardening techniques. The RICMOS™ IV process is an
advanced 5-volt, SIMOX CMOS technology with a 150 Å
gate oxide and a minimum feature size of 0.7 µm (0.55 µm
effective gate length—Leff). Additional features include
Honeywell’sproprietarySHARPplanarizationprocess, and
a lightly doped drain (LDD) structure for improved short
channelreliability.A7transistor(7T)memorycellisusedfor
superior single event upset hardening, while three layer
metal power bussing and the low collection volume SIMOX
substrate provide improved dose rate hardening.
HX6228
FUNCTIONAL DIAGRAM
131,072 x 8
Memory
Array
•
•
•
A:3-7,12,14-16
Row
Decoder
9
CE
•
•
•
NCS
8
Column Decoder
Data Input/Output
DQ:0-7
8
NWE
NOE
WE • CS • CE
1 = enabled
Signal
NWE • CS • CE • OE
(0 = high Z)
Signal
#
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
A:0-2, 8-11, 13
8
SIGNAL DEFINITIONS
A: 0-16
DQ: 0-7
Address input pins which select a particular eight-bit word within the memory array.
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Not chip select, when at a low level allows normal operation. When at a high level NCS forces the SRAM to
a precharge condition, holds the data output drivers in a high impedance state and disables all the input
buffers except CE. If this signal is not used it must be connected to VSS.
NWE
NOE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in
a high impedance state. When at a high level NWE allows normal read operation.
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
CE
Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
prechargecondition, holdsthedataoutputdriversinahighimpedancestateanddisablesalltheinputbuffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
TRUTH TABLE
CE
NCS
NWE
NOE
MODE
DQ
H
H
X
L
L
L
H
L
L
Read
Write
Data Out
Data In
Notes:
X
X: VI=VIH or VIL
XX: VSS≤VI≤VDD
NOE=H: High Z output state maintained
for NCS=X, CE=X, NWE=X
H
X
XX
XX
XX
XX
Deselected High Z
Disabled High Z
2
HX6228
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose
The SRAM will meet any functional or electrical specifica-
tion after exposure to a radiation pulse up to the transient
dosesurvivabilityspecification,whenappliedunderrecom-
mended operating conditions. Note that the current con-
ducted during the pulse by the RAM inputs, outputs, and
power supply may significantly exceed the normal operat-
ing levels. The application design must accommodate
these effects.
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature range
afterthespecifiedtotalionizingradiationdose. Allelectrical
and timing performance parameters will remain within
specifications after rebound at VDD = 5.5 V and T =125°C
extrapolatedtotenyearsofoperation. Totaldosehardness
isassuredbywaferleveltestingofprocessmonitortransis-
tors and RAM product using 10 KeV X-ray and Co60
radiation sources. Transistor gate threshold shift correla-
tions have been made between 10 KeV X-rays applied at
a dose rate of 1x105 rad(SiO2)/min at T = 25°C and gamma
rays (Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
Neutron Radiation
The SRAM will meet any functional or timing specification
after exposure to the specified neutron fluence under
recommended operating or storage conditions. This as-
sumes an equivalent neutron energy of 1 MeV.
Soft Error Rate
Transient Pulse Ionizing Radiation
The SRAM is capable of meeting the specified Soft Error
Rate (SER), under recommended operating conditions.
This hardness level is defined by the Adams 90% worst
case cosmic ray environment for geosynchronous orbits.
The SRAM is capable of writing, reading, and retaining
storeddataduringandafterexposuretoatransientionizing
radiation pulse up to the specified transient dost rate upset
specification, when applied under recommended operat-
ing conditions. To ensure validity of all specified perfor-
mance parameters before, during, and after radiation (tim-
ing degradation during transient pulse radiation is ≤20%),
it is suggested that stiffening capacitance be placed on or
near the package VDD and VSS, with a maximum induc-
tance between the package (chip) and stiffening capaci-
tance of 0.7 nH per part. If there are no operate-through or
valid stored data requirements, typical circuit board
mounted de-coupling capacitors are recommended.
Latchup
TheSRAMwillnotlatchupduetoanyoftheaboveradiation
exposure conditions when applied under recommended
operating conditions. Fabrication with the SIMOX sub-
strate material provides oxide isolation between adjacent
PMOS and NMOS transistors and eliminates any potential
SCR latchup structures. Sufficient transistor body tie con-
nections to the p- and n-channel substrates are made to
ensure no source/drain snapback occurs.
RADIATION HARDNESS RATINGS (1)
Test Conditions
Limits (2)
Units
Parameter
Total Dose
≥1x106
≥1x1011
≥1x1012
<1x10-10
≥1x1014
rad(SiO2)
rad(Si)/s
TA=25°C
Pulse width ≤1 µs
Transient Dose Rate Upset (3)
Transient Dose Rate Survivability
Soft Error Rate
Pulse width ≤50 ns, X-ray,
VDD=6.0 V, TA=25°C
rad(Si)/s
TA=125°C, Adams 90%
upsets/bit-day
N/cm2
worst case environment
1 MeV equivalent energy,
Unbiased, TA=25°C
Neutron Fluence
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, -55°C to 125°C.
(3) Applies to 40-lead flat pack only. Assume ≥1x1009 rad(Si))/s for 32-lead flat pack. Stiffening capacitance is suggested for optimum expected
dose rate upset performance as stated above.
3
HX6228
ABSOLUTE MAXIMUM RATINGS (1)
Rating
Symbol
Parameter
Units
Min
-0.5
-0.5
-65
Max
6.5
VDD
Supply Voltage Range (2)
V
V
VPIN
Voltage on Any Pin (2)
VDD+0.5
150
TSTORE
TSOLDER
PD
Storage Temperature (Zero Bias)
Soldering Temperature (5 Seconds)
Maximum Power Power Dissipation (3)
DC or Average Output Current
ESD Input Protection Voltage (4)
Thermal Resistance (Jct-to-Case)
Junction Temperature
°C
°C
W
270
2.5
IOUT
25
mA
V
VPROT
ΘJC
1500
2
°C/W
°C
TJ
175
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification.
(4) Class 1 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description
Parameter
Symbol
Units
Min
4.5
Typ
5.0
25
Max
5.5
VDD
TA
Supply Voltage (referenced to VSS)
Ambient Temperature
V
°C
V
-55
-0.3
125
VPIN
Voltage on Any Pin (referenced to VSS)
VDD+0.3
CAPACITANCE (1)
Worst Case
Symbol
Parameter
Test Conditions
Typical
Units
Max
Min
CI
Input Capacitance
Output Capacitance
6
8
7
9
pF
pF
VI=VDD or VSS, f=1 MHz
VIO=VDD or VSS, f=1 MHz
CO
(1) This parameter is tested during initial design characterization only.
DATA RETENTION CHARACTERISTICS
Worst Case (2)
Typical
(1)
Symbol
Parameter
Test Conditions
Units
Max
Min
NCS=VDR
VDR
IDR
Data Retention Voltage (3)
Data Retention Current
2.5
V
VI=VDR or VSS
NCS=VDD=VDR
VI=VDR or VSS
200
1.0
mA
(1) Typical operating conditions: TA= 25°C, pre-radiation.
(2) Worst case operating conditions: TA= -55°C to +125°C, past total dose at 25°C.
(3) To maintain valid data storage during transient radiation, VDD must be held within the recommended operating range.
4
HX6228
DC ELECTRICAL CHARACTERISTICS
Worst Case (2)
Typical
Symbol
Parameter
Units
Test Conditions
(1)
Min
Max
VIH=VDD, IO=0,
VIL=VSS, f=0MHz
NCS=VDD, IO=0,
f=40 MHz,
IDDSB
Static Supply Current
0.4
0.4
4.5
2.8
2.0
mA
mA
mA
mA
µA
IDDSBMF Standby Supply Current - Deselected
IDDOPW Dynamic Supply Current, Selected (Write)
IDDOPR Dynamic Supply Current, Selected (Read)
2.0
6.0
4.5
+5
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
VSS≤VI≤VDD
II
Input Leakage Current
Output Leakage Current
Low-Level Input Voltage
-5
VSS≤VIO≤VDD
IOZ
VIL
-10
+10
µA
Output=high Z
CMOS
TTL
1.7
3.2
0.3xVDD
V
V
March Pattern
VDD = 4.5V
0.8
CMOS
TTL
0.7xVDD
V
V
March Pattern
VDD = 5.5V
VIH
High-Level Input Voltage
2.2
0.3
0.005
0.4
0.1
V
V
VDD = 4.5V, IOL = 10 mA
VOL
VOH
Low-Level Output Voltage
High-Level Output Voltage
VDD = 4.5V, IOL = 200 µA
4.3
4.5 VDD-0.1
4.2
V
V
VDD = 4.5V, IOH = -5 mA
VDD = 4.5V, IOH = -200 µA
(1) Typical operating conditions: VDD= 5.0 V,TA=25°C, pre-radiation.
(2) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55°C to +125°C, post total dose at 25°C.
(3) All inputs switching. DC average current.
2.9 V
Valid high
output
+
-
Vref1
Vref2
249
+
-
Valid low
output
DUT
output
C >50 pF*
L
*C = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
L
Tester Equivalent Load Circuit
5
HX6228
READ CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
Symbol
Parameter
Typical
(2)
-55 to 125°C
Units
Min
Max
TAVAVR Address Read Cycle Time
16
15
12
16
12
5
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TAVQV
TAXQX
TSLQV
TSLQX
TSHQZ
TEHQV
TEHQX
TELQZ
TGLQV
TGLQX
TGHQZ
Address Access Time
25
25
Address Change to Output Invalid Time
Chip Select Access Time
3
5
Chip Select Output Enable Time
Chip Select Output Disable Time
Chip Enable Access Time
10
25
16
12
6
Chip Enable Output Enable Time
Chip Enable Output Disable Time
Output Enable Access Time
5
2
10
9
4
Output Enable Output Enable Time
Output Enable Output Disable Time
4
4
9
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading CL >50 pF, or equivalent
capacitive output loading CL=5 pF for TSHQZ, TELQZ TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical).
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55°C to 125°C, post total dose at 25°C.
TAVAVR
ADDRESS
TAVQV
TSLQV
TAXQX
NCS
TSLQX
TSHQZ
HIGH
IMPEDANCE
DATA OUT
DATA VALID
TEHQX
TEHQV
TELQZ
CE
TGLQX
TGLQV
TGHQZ
NOE
(NWE = high)
6
HX6228
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
-55 to 125°C
Symbol
Parameter
Typical
(2)
Units
Min
Max
TAVAVW Write Cycle Time (4)
13
9
25
20
20
15
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TWLWH Write Enable Write Pulse Width
TSLWH
TDVWH
TAVWH
TWHDX
TAVWL
TWHAX
TWLQZ
Chip Select to End of Write Time
12
9
Data Valid to End of Write Time
Address Valid to End of Write Time
Data Hold Time after End of Write Time
Address Valid Setup to Start of Write Time
Address Valid Hold after End of Write Time
Write Enable to Output Disable Time
10
0
0
0
0
0
5
0
9
TWHQX Write Disable to Output Enable Time
TWHWL Write Recovery Time
12
4
5
5
TEHWH
Chip Enable to End of Write Time
11
20
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive
load of 5 pF for TWLQZ.
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125°C, post total dose at 25°C.
(4) TAVAVW = TWLWH + TWHWL.
T
AVAVW
ADDRESS
T
AVWH
TWHAX
T
AVWL
T
WHWL
TWLWH
NWE
T
WLQZ
T
WHQX
DATA OUT
DATA IN
HIGH
IMPEDANCE
T
DVWH
TWHDX
DATA VALID
T
SLWH
NCS
CE
T
EHWH
7
HX6228
DYNAMIC ELECTRICAL CHARACTERISTICS
Read Cycle
Write Cycle
The RAM is asynchronous in operation, allowing the read
cycletobecontrolledbyaddress, chipselect(NCS), orchip
enable (CE) (refer to Read Cycle timing diagram). To
perform a valid read operation, both chip select and output
enable (NOE) must be low and chip enable and write
enable (NWE) must be high. The output drivers can be
controlled independently by the NOE signal. Consecutive
read cycles can be executed with NCS held continuously
low, and with CE held continuously high, and toggling the
addresses.
The write operation is synchronous with respect to the
address bits, and control is governed by write enable
(NWE), chip select (NCS), or chip enable (CE) edge
transitions (refer to Write Cycle timing diagrams). To per-
form a write operation, both NWE and NCS must be low,
and CE must be high. Consecutive write cycles can be
performed with NWE or NCS held continuously low, or CE
held continuously high. At least one of the control signals
must transition to the opposite state between consecutive
write operations.
For an address activated read cycle, NCS and CE must be
valid prior to or coincident with the activating address edge
transition(s). Any amount of toggling or skew between ad-
dress edge transitions is permissible; however, data outputs
will become valid TAVQV time following the latest occurring
address edge transition. The minimum address activated
read cycle time is TAVAV. When the RAM is operated at the
minimum address activated read cycle time, the data out-
puts will remain valid on the RAM I/O until TAXQX time
following the next sequential address transition.
The write mode can be controlled via three different control
signals: NWE, NCS, and CE. All three modes of control are
similar except the NCS and CE controlled modes actually
disable the RAM during the write recovery pulse. Both CE
and NCS fully disable the RAM decode logic and input
buffers for power savings. Only the NWE controlled mode
is shown in the table and diagram on the previous page for
simplicity; however, each mode of control provides the
same write cycle timing characteristics. Thus, some of the
parameter names referenced below are not shown in the
write cycle table or diagram, but indicate which control pin
is in control as it switches high or low.
To control a read cycle with NCS, all addresses and CE
must be valid prior to or coincident with the enabling NCS
edge transition. Address or CE edge transitions can occur
later than the specified setup times to NCS, however, the
valid data access time will be delayed. Any address edge
transition, which occurs during the time when NCS is low,
will initiate a new read access, and data outputs will not
become valid until TAVQV time following the address edge
transition. Data outputs will enter a high impedance state
TSHQZ time following a disabling NCS edge transition.
TowritedataintotheRAM,NWEandNCSmustbeheldlow
and CE must be held high for at least TWLWH/TSLSH/
TEHEL time. Any amount of edge skew between the
signals can be tolerated, and any one of the control signals
can initiate or terminate the write operation. For consecu-
tivewriteoperations, writepulsesmustbeseparatedbythe
minimumspecifiedTWHWL/TSHSL/TELEHtime.Address
inputs must be valid at least TAVWL/TAVSL/TAVEH time
before the enabling NWE/NCS/CE edge transition, and
must remain valid during the entire write time. A valid data
overlapofwritepulsewidthtimeofTDVWH/TDVSH/TDVEL,
and an address valid to end of write time of TAVWH/
TAVSH/TAVEL also must be provided for during the write
operation. Hold times for address inputs and data inputs
with respect to the disabling NWE/NCS/CE edge transition
must be a minimum of TWHAX/TSHAX/TELAX time and
TWHDX/TSHDX/TELDX time, respectively. The minimum
write cycle time is TAVAV.
To control a read cycle with CE, all addresses and NCS
must be valid prior to or coincident with the enabling CE
edgetransition.AddressorNCSedgetransitionscanoccur
later than the specified setup times to CE; however, the
valid data access time will be delayed. Any address edge
transition which occurs during the time when CE is high will
initiate a new read access, and data outputs will not
become valid until TAVQV time following the address edge
transition. Data outputs will enter a high impedance state
TELQZ time following a disabling CE edge transition.
8
HX6228
TESTER AC TIMING CHARACTERISTICS
TTL I/O Configuration
CMOS I/O Configuration
3 V
VDD-0.5 V
1.5 V
VDD/2
Input
Levels*
0 V
0.5 V
1.5 V
VDD/2
Output
Sense
Levels
VDD-0.4V
0.4 V
VDD-0.4V
High Z
High Z
0.4 V
3.4 V
2.4 V
3.4 V
2.4 V
High Z
High Z
High Z = 2.9V
High Z = 2.9V
* Input rise and fall times <1 ns/V
QUALITY AND RADIATIONHARDNESS
ASSURANCE
Honeywellmaintainsahighlevelofproductintegritythrough
process control, utilizing statistical process control, a com-
plete “Total Quality Assurance System,” a computer data
base process performance tracking system, and a radia-
tion hardness assurance strategy.
procurement by eliminating the need to create detailed
specifications and offer benefits of improved quality and
cost savings through standardization.
RELIABILITY
The radiation hardness assurance strategy starts with a
technology that is resistant to the effects of radiation.
Radiation hardness is assured on every wafer by irradiat-
ing test structures as well as SRAM product, and then
monitoring key parameters which are sensitive to ionizing
radiation. Conventional MIL-STD-883 TM 5005 Group E
testing, which includes total dose exposure with Cobalt 60,
may also be performed as required. This Total Quality
approach ensures our customers of a reliable product by
engineering in reliability, starting with process develop-
ment and continuing through product qualification and
screening.
Honeywell understands the stringent reliability require-
ments that space and defense systems require and has
extensive experience in reliability testing on programs of
this nature. This experience is derived from comprehen-
sive testing of VLSI processes. Reliability attributes of the
RICMOS™ process were characterized by testing spe-
cially designed irradiated and non-irradiated test struc-
tures from which specific failure mechanisms were evalu-
ated. These specific mechanisms included, but were not
limited to, hot carriers, electromigration and time depend-
ent dielectric breakdown. This data was then used to make
changes to the design models and process to ensure more
reliable products.
SCREENING LEVELS
In addition, the reliability of the RICMOS™ process and
product in a military environment was monitored by testing
irradiated and non-irradiated circuits in accelerated dy-
namic life test conditions. Packages are qualified for prod-
uct use after undergoing Groups B & D testing as outlined
in MIL-STD-883, TM 5005, Class S. The product is quali-
fied by following a screening and testing flow to meet the
customer’s requirements. Quality conformance testing is
performed as an option on all production lots to ensure the
ongoing reliability of the product.
Honeywell offers several levels of device screening to
meet your system needs. “Engineering Devices” are avail-
able with limited performance and screening for bread-
boarding and/or evaluation testing. Hi-Rel Level B and S
devices undergo additional screening per the require-
ments of MIL-STD-883. As a QML supplier, Honeywell
also offers QML Class Q and V devices per MIL-PRF-
38535 and are available per the applicable Standard
Microcircuits Drawing (SMD). QML devices offer ease of
9
HX6228
PACKAGING
The 128K x 8 SOI SRAM is offered in a custom 32-lead or
40-leadFlatPack.Thepackageisconstructedofmultilayer
ceramic (Al2O3) and features internal power and ground
planes.
board packing density. These capacitors effectively attach
to the internal package power and ground planes. This
design minimizes resistance and inductance of the bond
wire and package, both of which are critical in a transient
radiation environment. All NC (no connect) pins should be
connected to VSS to prevent charge build up in the
radiation environment.
Ceramicchipcapacitorscanbemountedtothepackageby
theusertomaximizesupplynoisedecouplingandincrease
32-LEAD FLAT PACK PINOUT
40-LEAD FLAT PACK PINOUT
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
A15
CE
NWE
A13
A8
A15
VSS
VDD
NWE
CE
A13
A8
A16
VSS
VDD
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
NC
VDD
VSS
NC
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
2
2
3
3
4
4
5
5
6
6
7
7
A9
Top
View
A9
8
8
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
NC
9
9
10
11
12
13
14
15
16
17
18
19
20
10
11
12
13
14
15
16
Top
View
32-LEAD FLAT PACK
All dimensions in inches
Optional capacitors
in cutout
VDD VSS VDD
A
b
C
D
e
0.135 ± 0.015
0.017 ± 0.002
0.004 to 0.009
0.820 ± 0.008
0.050 ± 0.005 [1]
0.600 ± 0.008
E
22018533-001
1
1
Z
b
(width)
E
E2 0.500 ± 0.008
E3 0.040 ref
TOP
VIEW
BOTTOM
VIEW
D
F
F
L
0.750 ± 0.005 [2]
0.295 min [3]
0.026 to 0.045
0.035 ± 0.010
0.080 ref
e
(pitch)
Q
S
U
V
W
X
Y
Z
S
U
0.380 ref
L
Y
X
W
0.050 ref
0.075 ref
Kovar
Lid [4]
Cutout
Area
Ceramic
Body
0.010 ref
A
Lead
Alloy 42
Q
C
0.135 ref
[1] BSC - Basic lead spacing between centers
[2] Where lead is brazed to package
[3] Parts delivered with leads unformed
[4] Lid connected to VSS
V
E2
E3
10
HX6228
40-LEAD FLAT PACK
E
S
1
40
Top
View
b
D
(width)
21
20
e
(pitch)
L
All dimensions are in inches
Ceramic Body
Kovar Lid [3]
A
b
c
D
E
e
F
G
H
I
L
N
S
T
U
V
W
X
Z
0.131 ± .015
0.008 ± 0.002
0.006 ± 0.0015
0.710 ±0.010
0.775 ± 0.007
0.025 ± 0.004
0.475 ± 0.005
0.760 ± 0.008
0.135 ± 0.005
0.030 ± 0.005
0.285 ± 0.015
0.050 ± 0.004
0.1175 ref
I
C
X
A
N
(Pedestal)
Capacitor Pads
Non-Conductive
Tie-Bar
0.064 ref
0.006 ref
0.028 ref
0.125 ref
0.500 ± 0.005
0.140 ref
[1] Parts delivered with leads unformed
[2] At tie bar
[3] Lid tied to VSS
Bottom
View
F
G
W
H
Z
V
T
U
11
HX6228
DYNAMIC BURN-IN DIAGRAM*
STATIC BURN-IN DIAGRAM*
VDD
VDD
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
VDD
A15
CE
NWE
A13
A8
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
NC
VDD
A15
CE
NWE
A13
A8
R
R
F18
F19
F0
F15
F12
F11
F10
F19
F9
F19
F1
F1
F1
F1
R
R
R
R
R
F17
F16
F7
F6
F5
F4
F3
F2
F8
F13
F14
F1
F1
F1
R
3
R
R
R
R
3
R
R
R
R
4
R
R
R
R
4
5
5
6
6
R
R
R
R
7
A9
7
R
R
R
R
R
A9
8
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
R
R
8
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
9
9
R
R
10
11
12
13
14
15
16
10
11
12
13
14
15
16
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
F1
VDD = 5.6V, R ≤ 10 KΩ, VIH = VDD, VIL = VSS
Ambient Temperature ≥ 125 °C, F0 ≥ 100 KHz Sq Wave
Frequency of F1 = F0/2, F2 = F0/4, F3 = F0/8, etc.
VDD = 5.5V, R ≤ 10 KΩ
Ambient Temperature ≥ 125 °C
*40-Lead Flat Pack burn-in diagrams have similar connections and are available upon request.
ORDERING INFORMATION (1)
6228
H
X
T
S
C
R
SCREEN LEVEL
V=QML Class V
Q=QML Class Q
S=Level S
B=Level B
E=Engr Device (2)
PART NUMBER
PROCESS
X=SOI
TOTAL DOSE
HARDNESS
SOURCE
H=HONEYWELL
PACKAGE DESIGNATION
T=32-Lead FP
A=40-Lead FP
K=Known Good Die
- =Bare die (No Package)
INPUT
BUFFER TYPE
C=CMOS Level
T=TTL Level
R=1x105 rad(SiO2)
F=3x105 rad(SiO2)
H=1x106 rad(SiO2)
N=No Level Guaranteed
(1) Orders may be faxed to 612-954-2051. For technical assistance, contact our Customer Logistics Department at 612-954-2888.
(2) Engineering Device description: Parameters are tested from -55 to 125°C, 24 hr burn-in, IDDSB = 10mA, no radiation guaranteed.
Contact Factory with other needs.
To lea r n m or e a bou t Hon eyw ell Solid Sta te Electr on ics Cen ter ,
visit ou r w eb site a t h ttp ://w w w .ssec.h on eyw ell.com
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability
arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
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