概述
规格参数
数据手册HX6228-SRC 概述
Standard SRAM, 128KX8, 25ns, CMOS, DIE SRAM
HX6228-SRC 规格参数
| 生命周期： | Active | 零件包装代码： | DIE |
| 包装说明： | DIE, | Reach Compliance Code： | unknown |
| ECCN代码： | 3A001.A.2.C | HTS代码： | 8542.32.00.41 |
| 风险等级： | 5.62 | 最长访问时间： | 25 ns |
| JESD-30 代码： | R-XUUC-N | 内存密度： | 1048576 bit |
| 内存集成电路类型： | STANDARD SRAM | 内存宽度： | 8 |
| 功能数量： | 1 | 字数： | 131072 words |
| 字数代码： | 128000 | 工作模式： | ASYNCHRONOUS |
| 最高工作温度： | 125 °C | 最低工作温度： | -55 °C |
| 组织： | 128KX8 | 封装主体材料： | UNSPECIFIED |
| 封装代码： | DIE | 封装形状： | RECTANGULAR |
| 封装形式： | UNCASED CHIP | 并行/串行： | PARALLEL |
| 认证状态： | Not Qualified | 筛选级别： | MIL-STD-883 Class S |
| 最大供电电压 (Vsup)： | 5.5 V | 最小供电电压 (Vsup)： | 4.5 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | MILITARY |
| 端子形式： | NO LEAD | 端子位置： | UPPER |
| 总剂量： | 100k Rad(Si) V | Base Number Matches： | 1 |
HX6228-SRC 数据手册
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PDF下载HX6228
128K x 8 STATIC RAM - SOI
The 128K x 8 Radiation Hardened Static RAM is a high performance 131,072 word
x 8-bit static random access memory with industry-standard functionality. It is
fabricated with Honeywell’s radiation hardened SOI-CMOS technology, and is
designed for use in systems operating in radiation environments. The RAM operates
over the full military temperature range and requires only a single 5 V ± 10% power
supply. The RAM is wire bond programmable for either TTL or CMOS compatible
I/O. Power consumption is typically less than 25 mW/MHz in operation, and less
than 5 mW in the low power disabled mode. The RAM read operation is fully
asynchronous, with an associated typical access time of 16 ns at 5V.
Honeywell’s enhanced SOI-IV CMOS technology is radiation hardened through the use of advanced and proprietary
design, layout and process hardening techniques. The SOI-IV process is an advanced 5-volt, SOI CMOS technology with
a 150 Å gate oxide and a minimum feature size of 0.7 µm (0.55 µm effective gate length—Leff). Additional features
include Honeywell’s proprietary SHARP planarization process, and a lightly doped drain (LDD) structure for improved
short channel reliability. A 7 transistor (7T) memory cell is used for superior single event upset hardening, while three
layer metal power bussing and the low collection volume SOI substrate provide improved dose rate hardening.
FEATURES
RADIATION
OTHER
•
Fabricated with SOI-IV CMOS 0.7 µm
(Leff = 0.55 µm)
•
Read/Write Cycle Times
o ≤ 16 ns (Typical)
o ≤ 25 ns (-55 to 125°C)
•
•
•
Total Dose Hardness through 1x106 rad(Si)
Neutron Hardness through 1x1014 N/cm2
•
•
•
•
•
Asynchronous Operation
Typical Operating Power <25 mW/MHz
CMOS or TTL Compatible I/O
Single 5 V ± 10% Power Supply
Dynamic and Static Transient Upset Hardness
through 1x1011 rad(SiO2)/s
•
•
Dose Rate Survivability through 1x1012 rad(SiO2)/s
Soft Error Rate of <1x10-10 upsets/bit-day in
Geosynchronous Orbit
Packaging Options
o 32-Lead Flat Pack (0.820 in. x 0.600 in.)
o 40-Lead Flat Pack (0.775 in. x 0.710 in.)
•
No Latchup
HX6228
FUNCTIONAL DIAGRAM
SIGNAL DEFINITIONS
A: 0-16 Address input pins which select a particular eight-bit word within the memory array.
DQ: 0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables
all input buffers except CE. If this signal is not used it must be connected to VSS.
NWE
NOE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in a high
impedance state. When at a high level NWE allows normal read operation.
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a
low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must be
connected to VSS.
CE
Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
TRUTH TABLE
Notes:
X:
XX:
CE
H
NCS
NWE
H
NOE
L
MODE
Read
DQ
VI=VIH or VIL
VSS≤VI≤VDD
L
L
Data Out
Data In
High Z
High Z
NOE=H: High Z output state
maintained for NCS=X,
CE=X, NWE=X
H
L
X
Write
X
H
X
XX
XX
XX
XX
Deselected
Disabled
L
2
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HX6228
RADIATION CHARACTERISTICS
The SRAM will meet any functional or electrical
specification after exposure to a radiation pulse of up to
the transient dose rate survivability specification, when
applied under recommended operating conditions. Note
that the current conducted during the pulse by the RAM
inputs, outputs and power supply may significantly
exceed the normal operating levels. The application
design must accommodate these effects.
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature
range after the specified total ionizing radiation dose. All
electrical and timing performance parameters will remain
within specifications after rebound at VDD = 5.5 V and T
=125°C extrapolated to ten years of operation. Total
dose hardness is assured by wafer level testing of
process monitor transistors and RAM product using 10
keV X-ray and Co60 radiation sources. Transistor gate
threshold shift correlations have been made between 10
keV X-rays applied at a dose rate of 1x105 rad(SiO2)/min
at T = 25°C and gamma rays (Cobalt 60 source) to
ensure that wafer level X-ray testing is consistent with
standard military radiation test environments.
Neutron Radiation
The SRAM will meet any functional or timing
specification after exposure to the specified neutron
fluence under recommended operating or storage
conditions. This assumes equivalent neutron energy of 1
MeV.
Soft Error Rate
Transient Pulse Ionizing Radiation
The SRAM is immune to single event upsets (SEU’s) to
the specified soft error rate (SER), under recommended
operating conditions. This hardness level is defined by
the Adams 10% worst case cosmic ray environment for
geosynchronous orbits.
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse up to the transient dose rate
upset specification, when applied under recommended
operating conditions. To ensure validity of all specified
performance parameters before, during, and after
radiation (timing degradation during transient pulse
radiation is ≤20%), it is suggested that stiffening
capacitance be placed on or near the package VDD and
VSS, with a maximum inductance between the package
(chip) and stiffening capacitance of 0.7 nH per part. If
there are no operate-through or valid stored data
requirements, typical circuit board mounted de-coupling
capacitors are recommended.
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under
recommended operating conditions. Fabrication with the
SOI-IV substrate material provides oxide isolation
between adjacent PMOS and NMOS transistors and
eliminates any potential SCR latchup structures.
Sufficient transistor body tie connections to the p- and n-
channel substrates are made to ensure no source/drain
snapback occurs.
RADIATION HARDNESS RATINGS
Parameter
Limits (2)
≥1x106
Units
Test Conditions
Total Dose
rad(Si)
TA=25°C
Transient Dose Rate Upset (3)
Transient Dose Rate Survivability (3)
Soft Error Rate (SER)
≥1x1011
≥1x1012
<1x10-10
≥1x1014
rad(SiO2)/s
rad(Si O2)/s
Pulse width ≤1 μs
Pulse width ≤50 ns, X-ray, VDD=6.0V, TA=25°C
upsets/bit-day TA=25°C, Adams 90% worst case environment
N/cm2
1 MeV equivalent energy, Unbiased, TA=25°C
Neutron Fluence
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55°C to 125°C.
(3) Applies to 40-lead flat pack only. Assume ≥1x109 rad(SiO2)/s for 32-lead flat pack. Stiffening capacitance is suggested for optimum
expected dose rate upset performance as stated above.
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HX6228
ABSOLUTE MAXIMUM RATINGS (1)
Rating
Symbol
VDD
Parameter
Positive Supply Voltage (2)
Min
-0.5
-0.5
-65
Max
6.5
Units
V
VPIN
Voltage on Any Pin (2)
VDD +0.5
150
V
TSTORE
TSOLDER
PD
Storage Temperature (Zero Bias)
Soldering Temperature (5 seconds)
Maximum Package Power Dissipation (3)
DC or Average Output Current
ESD Input Protection Voltage (4)
Thermal Resistance (Jct-to-Case)
Junction Temperature
°C
270
°C
2.5
W
IOUT
25
mA
V
VPROT
ΘJC
2000
2
°C/W
TJ
175
°C
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these
levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this
specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description
Symbol
VDD
Parameter
Min
Typical
Max
Units
Supply Voltage (referenced to VSS)
4.5
5.0
5.5
V
TA
Ambient Temperature
-55
25
125
50
°C
ms
V
VDDRAMP
VPIN
VDD Turn On Ramp Time
Voltage On Any Pin (referenced to VSS)
-0.3
VDD+0.3
VDD Ramp
Time
Supply Voltage Ramp Rate
50
ms
CAPACITANCE (1)
Worst Case
Min Max
Symbol
Parameter
Units
Test Conditions
CI
Input Capacitance
7
9
pF
VI=VDD or VSS, f=1 MHz
VIO=VDD or VSS, f=1 MHz
CO
Output Capacitance
pF
(1) This parameter is tested during initial design characterization only.
DATA RETENTION CHARACTERISTICS (1)
Worst Case (2)
Min
Max
Symbol
Parameter
Units
Test Conditions
VDR
Data Retention Voltage(3)
2.5
V
NCS=VDR, VI=VDR or VSS
IDR
Data Retention Current
700
μA
NCS=VDD=VDR, VI=VDD or VSS
(1) Typical operating conditions: TA= 25°C, pre-radiation.
(2) Worst case operating conditions: TA= -55°C to +125°C, post total dose at 25°C.
(3) To maintain valid data storage during transient radiation, VDD must be held within the recommended operating range.
4
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HX6228
DC ELECTRICAL CHARACTERISTICS
Typical
(1)
Worst Case (2)
Min
Max
Symbol
Parameter
Units
Test Conditions
VIH=VDD, IO=0
IDDSB
Static Supply Current
0.4
0.4
2.0
mA
VIL=VSS, f=0MHz
Standby Supply Current –
Deselected
NCS=VDD, IO=0,
f=40 MHz
IDDSBMF
IDDOPW
2.0
mA
mA
Dynamic Supply Current, Selected
(Write)
1 MHz
6
VDD=max, Iout=0mA,
2 MHz
10 MHz
25 MHz
40 MHz
NSL=VIH, NCS=VIL (1) (3)
12
60
150
240
IDDOPR
Dynamic Supply Current, Selected
(Read)
1 MHz
2 MHz
4.5
9
mA
VDD=max, Iout=0mA,
NSL=VIH, NCS=VIL (1) (3)
10 MHz
25 MHz
40 MHz
45
112
180
VSS ≤ VI ≤ VDD
II
Input Leakage Current
Output Leakage Current
-5
+5
μA
μA
V
VSS ≤ VI ≤ VDD
Output = high Z
IOZ
VIL
VIH
VOL
VOH
-10
+10
Low-Level Input Voltage CMOS
TTL
0.3xVDD
0.8
March Pattern
VDD = 4.5V
High-Level Input Voltage CMOS
TTL
0.7xVDD
2.2
March Pattern
VDD = 5.5V
V
0.4
0.1
VDD=4.5V, IOL = 10 mA
VDD=4.5V, IOL = 200 μA
Low-Level Output Voltage
High-Level Output Voltage
V
VDD - 0.3
VDD - 0.1
VDD=4.5V, IOL = -5 mA
VDD=4.5V, IOL = -200 μA
V
(1) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(2) Worst case operating conditions: VDD=4.5 V to 5.5 V, TA=-55°C to +125°C, post total dose at 25°C.
(3) All inputs switching. DC average current.
Valid High
Output
2.9V
Vref1
Vref2
249
Valid Low
Output
DUT
Output
CL ≥ 50 pf *
* CL = 5 pf for TWLQZ, TSHQZ, TELQZ, and TGHQZ
Tester Equivalent Load Circuit
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5
HX6228
READ CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
-55 to 125° C
Min
Max
Symbol
TAVAVR
Parameter
Typical (2)
Units
Address Read Cycle Time
25
ns
TAVQV
TAXQX
TSLQV
TSLQX
TSHQZ
TEHQV
TEHQX
TELQZ
TGLQV
TGLQX
TGHQZ
Address Access Time
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Change to Output Invalid Time
Chip Select Access Time
3
5
Chip Select Output Enable Time
Chip Select Output Disable Time
Chip Select Access Time
10
25
Chip Select Output Enable Time
Chip Select Output Disable Time
Output Enable Access Time
5
0
10
9
Output Enable Output Enable Time
Output Enable Output Disable Time
9
(1) Test conditions: input switching levels,VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels
shown in the Tester AC Timing Characteristics table, capacitive output loading CL>50 pF, or equivalent capacitive output loading
CL=5 pF for TSHQZ, TELQZ TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical).
(2) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=3.0 V to 3.6 V, post total dose at 25°C.
6
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HX6228
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
-55 to 125° C
Typical
(2)
Min
25
20
20
15
20
0
Max
Symbol
Parameter
Write Cycle Time (4)
Units
TAVAVW
ns
TWLWH
TSLWH
TDVWH
TAVWH
TWHDX
TAVWL
TWHAX
TWLQZ
TWHQX
TWHWL
TEHWH
Write Enable Write Pulse Width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write Time
Data Valid to End of Write Time
Address Valid to End of Write Time
Data Hold Time after End of Write Time
Address Valid Setup to Start of Write Time
Address Valid Hold after End of Write Time
Write Enable to Output Disable Time
Write Disable to Output Enable Time
Write Disable to Write Enable Pulse Width (5)
Chip Enable to End of Write Time
0
0
0
9
5
5
20
(1) Test conditions: input switching levels, VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels
shown in the Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive load of 5 pF for
TWLQZ.
(2) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=3.0 V to 3.6 V, -55 to 125°C, post total dose at 25°C.
(4) TAVAVW = TWLWH + TWHWL
(5) Guaranteed but not tested.
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7
HX6228
DYNAMIC ELECTRICAL CHARACTERISTICS
Read Cycle
Write Cycle
The RAM is asynchronous in operation, allowing the
read cycle to be controlled by address, chip select
(NCS), or chip enable (CE) (refer to Read Cycle timing
diagram). To perform a valid read operation, both chip
select and output enable (NOE) must be low and chip
enable and write enable (NWE) must be high. The
output drivers can be controlled independently by the
NOE signal. Consecutive read cycles can be executed
with NCS held continuously low, and with CE held
continuously high, and toggling the addresses.
The write operation is synchronous with respect to the
address bits, and control is governed by write enable
(NWE), chip select (NCS), or chip enable (CE) edge
transitions (refer to Write Cycle timing diagrams). To
perform a write operation, both NWE and NCS must be
low, and CE must be high. Consecutive write cycles can
be performed with NWE or NCS held continuously low,
or CE held continuously high. At least one of the control
signals must transition to the opposite state between
consecutive write operations.
For an address activated read cycle, NCS and CE must
be valid prior to or coincident with the activating address
edge transition(s). Any amount of toggling or skew
between address edge transitions is permissible;
however, data outputs will become valid TAVQV time
following the latest occurring address edge transition.
The minimum address activated read cycle time is
TAVAV. When the RAM is operated at the minimum
address activated read cycle time, the data outputs will
remain valid on the RAM I/O until TAXQX time following
the next sequential address transition.
The write mode can be controlled via three different
control signals: NWE, NCS, and CE. All three modes of
control are similar except the NCS and CE controlled
modes actually disable the RAM during the write
recovery pulse. Both CE and NCS fully disable the RAM
decode logic and input buffers for power savings. Only
the NWE controlled mode is shown in the table and
diagram on the previous page for simplicity. However,
each mode of control provides the same write cycle
timing characteristics. Thus, some of the parameter
names referenced below are not shown in the write cycle
table or diagram, but indicate which control pin is in
control as it switches high or low.
To control a read cycle with NCS, all addresses and CE
must be valid prior to or coincident with the enabling
NCS edge transition. Address or CE edge transitions
can occur later than the specified setup times to NCS,
however, the valid data access time will be delayed. Any
address edge transition, which occurs during the time
when NCS is low, will initiate a new read access, and
data outputs will not become valid until TAVQV time
following the address edge transition. Data outputs will
enter a high impedance state TSHQZ time following a
disabling NCS edge transition.
To write data into the RAM, NWE and NCS must be held
low and CE must be held high for at least
TWLWH/TSLSH/TEHEL time. Any amount of edge skew
between the signals can be tolerated, and any one of the
control signals can initiate or terminate the write
operation. For consecutive write operations, write pulses
must be separated by the minimum specified
TWHWL/TSHSL/TELEH time. Address inputs must be
valid at least TAVWL/TAVSL/TAVEH time before the
enabling NWE/NCS/CE edge transition, and must
remain valid during the entire write time. A valid data
To control a read cycle with CE, all addresses and NCS
must be valid prior to or coincident with the enabling CE
edge transition. Address or NCS edge transitions can
occur later than the specified setup times to CE;
however, the valid data access time will be delayed. Any
address edge transition which occurs during the time
when CE is high will initiate a new read access, and data
outputs will not become valid until TAVQV time following
the address edge transition. Data outputs will enter a
high impedance state TELQZ time following a disabling
CE edge transition.
overlap
of
write
pulse
width
time
of
TDVWH/TDVSH/TDVEL, and an address valid to end of
write time of TAVWH/TAVSH/TAVEL also must be
provided for during the write operation. Hold times for
address inputs and data inputs with respect to the
disabling NWE/NCS/CE edge transition must be a
minimum
TWHDX/TSHDX/TELDX
minimum write cycle time is TAVAV.
of
TWHAX/TSHAX/TELAX
time
and
The
time,
respectively.
8
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HX6228
TESTER AC TIMING CHARACTERISTICS
QUALITY AND RADIATION HARDNESS
ASSURANCE
RELIABILITY
Honeywell
understands the
stringent reliability
requirements for space and defense systems and has
extensive experience in reliability testing on programs of
this nature. This experience is derived from
comprehensive testing of VLSI processes. Reliability
attributes of the SOI-IV process were characterized by
testing specially designed irradiated and non-irradiated
test structures from which specific failure mechanisms
were evaluated. These specific mechanisms included,
but were not limited to, hot carriers, electromigration and
time dependent dielectric breakdown. This data was
then used to make changes to the design models and
process to ensure more reliable products.
Honeywell maintains a high level of product integrity
through process control, utilizing statistical process
control, a complete “Total Quality Assurance System,” a
computer data base process performance tracking
system, and a radiation- hardness assurance strategy.
The radiation hardness assurance strategy starts with a
technology that is resistant to the effects of radiation.
Radiation hardness is assured on every wafer by
irradiating test structures as well as SRAM product, and
then monitoring key parameters which are sensitive to
ionizing radiation. Conventional MIL-STD-883 TM 5005
Group E testing, which includes total dose exposure with
Cobalt 60, may also be performed as required. This
Total Quality approach ensures our customers of a
reliable product by engineering in reliability, starting with
process development and continuing through product
qualification and screening.
In addition, the reliability of the SOI CMOS process and
product in a military environment was monitored by
testing irradiated and non-irradiated circuits in
accelerated dynamic life test conditions. Packages are
qualified for product use after undergoing Groups B & D
testing as outlined in MIL-STD-883, TM 5005, Class S.
The product is qualified by following a screening and
testing flow to meet the customer’s requirements. Quality
conformance testing is performed as an option on all
production lots to ensure the ongoing reliability of the
product.
SCREENING LEVELS
Honeywell offers several levels of device screening to
meet your system needs. “Engineering Devices” are
available with limited performance and screening for
breadboarding and/or evaluation testing. Hi-Rel Level B
and S devices undergo additional screening per the
requirements of MILSTD-883. As a QML supplier,
Honeywell also offers QML Class Q and V devices per
MIL-PRF-38535 and are available per the applicable
Standard Microcircuit Drawing (SMD). QML devices offer
ease of procurement by eliminating the need to create
detailed specifications and offer benefits of improved
quality and cost savings through standardization.
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HX6228
Ceramic chip capacitors can be mounted to the package
by the user to maximize supply noise decoupling and
increase board packing density. These capacitors attach
directly to the internal package power and ground
planes. This design minimizes resistance and
inductance of the bond wire and package. All NC (no
connect) pins must be connected to VDD, VSS or an
active driver to prevent charge build up in the radiation
environment.
PACKAGING
The 128K x 8 SRAM is offered in a 32-Lead or 40-Lead
Flatpack type package. Each package is constructed of
multilayer ceramic (Al2O3) and features internal power
and ground planes.
32-LEAD FLATPACK PINOUT
40-LEAD FP PINOUT
BURN-IN CONFIGURATION
10
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HX6228
32-LEAD FLAT PACK
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11
HX6228
40-LEAD FLAT PACK
12
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HX6228
ORDERING INFORMATION (1)
The HX6228 may be ordered through the SMD Drawing 5962-98537.
H
X
6228
A
S
H
H
SCREEN LEVEL
V = QML Class V
W = QML Class Q+
S = Class S
Part Number
Process
X = SOI
Input Buffer Type
C = CMOS
T = TTL
B = Class B
E = Eng. Model (2)
Source
TOTAL DOSE HARDNESS
R = 1x105 rad (Si)
H = Honeywell
PACKAGE DESIGNATION
T = 32 Lead FP
A = 40 Lead FP
K = Known Good Die
- = Bare Die (no package)
F = 3x105 rad (Si)
H = 1x106 rad (Si)
N = No Level Guaranteed (2)
(1) Orders may be faxed to 763-954-2257.
(2) Engineering Device description: Parameters are tested from -55 to 125°C, 24 hr burn-in, no radiation guaranteed.
FIND OUT MORE
For more information on Honeywell’s Microelectronic products, visit us online at www.honeywell.com/microelectronics
or contact us at 800-323-8295 (763-954-2474 internationally).
The application circuits herein constitute typical usage and interface of Honeywell product. Honeywell does not warranty or assume liability of customer-
designed circuits derived from this description or depiction.
Honeywell reserves the right to make changes to improve reliability, function or design. Honeywell does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Honeywell
12001 Highway 55
Plymouth, MN 55441
Tel: 800-323-8295
www.honeywell.com/microelectronics
Form #900918
July 2012
©2012 Honeywell International Inc.
www.honeywell.com
13
HX6228-SRC 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| HX6228-SRT | HONEYWELL | Standard SRAM, 128KX8, 25ns, CMOS, DIE | 获取价格 |
|
| HX6228-VHC | HONEYWELL | Standard SRAM, 128KX8, 25ns, CMOS, DIE | 获取价格 |
|
| HX6228-VRC | HONEYWELL | Standard SRAM, 128KX8, 25ns, CMOS, DIE | 获取价格 |
|
| HX6228ABFC | HONEYWELL | 128K x 8 STATIC RAM-SOI HX6228 | 获取价格 |
|
| HX6228ABFT | HONEYWELL | 128K x 8 STATIC RAM-SOI HX6228 | 获取价格 |
|
| HX6228ABHC | HONEYWELL | 128K x 8 STATIC RAM-SOI HX6228 | 获取价格 |
|
| HX6228ABHT | HONEYWELL | 128K x 8 STATIC RAM-SOI HX6228 | 获取价格 |
|
| HX6228ABNC | HONEYWELL | 128K x 8 STATIC RAM-SOI HX6228 | 获取价格 |
|
| HX6228ABNT | HONEYWELL | 128K x 8 STATIC RAM-SOI HX6228 | 获取价格 |
|
| HX6228ABRC | HONEYWELL | 128K x 8 STATIC RAM-SOI HX6228 | 获取价格 |
|
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