HX2080 [HONEYWELL]
RICMOS⑩ SOI GATE ARRAYS; RICMOS ™ SOI门阵列
| 型号： | HX2080 |
| 厂家： | 
Honeywell |
| 描述： | RICMOS⑩ SOI GATE ARRAYS |
| 文件： | 总2页 (文件大小：23K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RICMOS™ SOI GATE ARRAYS
HX2000
HX2000r
FAMILY
FEATURES
• Fabricated on Honeywell’s Radiation Hardened
– 0.65 µmLeff RICMOS™ IV SOI Process, HX2000
– 0.55 µmLeff RICMOS™ IV SOI Process, HX2000r
• Total Dose Hardness ≥1x106 rad(SiO2)
• Dose Rate Upset Hardness:
≥1x1010 rad(Si)/sec, HX2000*
≥1x109 rad(Si)/sec, HX2000r*
• Array Sizes from 40K to 390K Available Gates (Raw)
• HX2000 Supports 5V Core Operation
Option Available for:
≥1x1011 rad(Si)/sec, HX2000*
≥1x1010 rad(Si)/sec, HX2000r*
• HX2000r Supports 3.3V Core Operation
• HX2000r Supports Mixed Voltage I/O Buffers
• TTL (5V) or CMOS (5V/3.3V) Compatible I/O
• Configurable Multi-Port Gate Array SRAM
• Single or Dual Port Custom SRAM Drop-In Capability
• Supports Chip Level Power Down for Cold Sparing
• Supports System Speeds Beyond 100 MHz
• Dose Rate Survivability ≥1x1012 rad(Si)/sec*
• Soft Error Rate
≤1x10-11 Errors/Bit/Day, HX2000
≤1x10-10 Errors/Bit/Day, HX2000r
• Neutron Fluence Hardness to 1x1014/cm2
• No Latchup
*Projected
GENERAL DESCRIPTION
The HX2000 and HX2000r gate arrays are performance
oriented sea-of-transistor arrays, fabricated on
Honeywell’s RICMOS™ IV Silicon On Insulator (SOI) pro-
cess. The HX2000 arrays are for 5V designs only. The
HX2000r arrays support 5V and 3.3V operation. High
density is achieved with the standard 3-layer metal or
optional 4-layer metal process, providing up to 290,000
usable gates. The high density and performance charac-
teristics of the RICMOS (Radiation Insensitive CMOS) SOI
process make possible device operation beyond 100 MHz
over the full military temperature range, even after expo-
Designers can choose from a wide variety of I/O types.
Output buffer options include 8 drive strengths, CMOS/TTL
levels, IEEE 1149.1 boundary scan, pull-up/pull-down re-
sistors, and three-state capability. Input buffers can be
selected for CMOS/TTL/Schmitt trigger levels, IEEE
1149.1 boundary scan and pull-up/pull-down resistors.
Bi-directional buffers are also available.
An important feature of HX2000r is the dual voltage I/O
capability in which the designer has complete flexibility in
terms of placement of I/O buffers. This feature allows
adjacent I/O buffers with different supply voltages.
sure to ionizing radiation exceeding 1x106 rad(SiO ). Flip-
2
Flops have been designed for a Soft Error Rate (SER) of
less than 1x10-11 errors/bit/day in the Adams 90% worst
case environment.
The HX2000/HX2000r families provide options for config-
urable multi-port SRAMs. Word widths can be selected in
single bit increments. A variety of SRAM read and write port
options are available to serve most applications. Custom
drop-in macrocells can also be implemented to further
increase chip density. Word widths can be selected in two
bit increments. Single port and two port options are avail-
able.
Each HX2000/HX2000r design is founded on our proven
RICMOS ASIC library of SSI and MSI logic elements,
configurable RAM cells, and selectable I/O pads. The gate
arrays feature a global clock network capable of handling
multiple clock signals with low clock skew between regis-
ters. This family is fully compatible with Honeywell’s high
reliability screening procedures and consistent with QML
Class Q and V requirements.
The HX2000/HX2000r families have a special feature to
allow a chip level power down mode, in which the associ-
ated buses connected to the chip can remain active. This
Solid State Electronics Center • 12001 State Highway 55, Plymouth, MN 55441 • (800) 323-8295 • http://www.ssec.honeywell.com
HX2000/HX2000r
HX2000 Characteristics
HX2040*
HX2080
HX2160
HX2300
HX2400
Total Core Gate Count
40K
85K
160K
295K
390K
Usable Gate Count
3-Layer Metal
4-Layer Metal (1)
27K
36K
53K
71K
91K
132K
156K
226K
200K
290K
Maximum Die I/O
132
176
176
240
240
336
320
372
320
Maximum Package I/O (2)
Typical Delay—2 Input NAND
Selectable I/O
TBD
270 ps at 5.0V, 290 ps at 3.3V
Driver, Receiver, Bi-Directional, Three-State
CMOS, TTL, Schmitt Trigger
I/O Interface Levels
Typical Power Dissipation, µW/Gate/MHz
0.6 @ 5.0V, 0.22 @ 3.3V
Operating Voltage
HX2000 5.0V ± 10%
HX2000r 3.3V ± 10% (Core & I/O) and/or 5.0V ± 10% (I/O)
Operating Temperature
-55° C to 125° C
Process Technology
Minimum Geometry
RICMOS™ IV SOI
HX2000 0.65 µm Leff / 0.8 µm Drawn (5V)
HX2000r 0.55 µm Leff / 0.7 µm Drawn (3.3V)
(1) Projected
* Planned Array
(2) Design and package dependent.
high impedance off-state buffer feature allows users to Honeywell can perform design translations to the HX2000
power down portions of their system for power savings or for arraysfromotherCADplatforms.Oursynthesiscapabilities
cold sparing.
allow customers to use familiar CAD tools and libraries to
map existing designs to Honeywell library components.
Logic designers need not have prior experience in radiation
hardening.Honeywell’sVDS™ToolkitandRICMOSIVSOI TheHX2000familyofgatearraysistherightchoiceforyour
libraries provide the necessary guidance to achieve first high reliability applications demanding high density and
pass design success. The VDS Toolkit supports industry radiation performance. To learn more about Honeywell’s
standard platforms including those offered by Mentor variety of space components, call us at 612-954-2888.
Graphicsand Synopsys.
To lea r n m or e a bou t Hon eyw ell Solid Sta te Electr on ics Cen ter , visit ou r w eb site a t
h ttp ://w w w .ssec.h on eyw ell.com
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability
arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
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