HI-8383PDTF [HOLTIC]
Line Driver;
| 型号： | HI-8383PDTF |
| 厂家： | 
HOLT INTEGRATED CIRCUITS |
| 描述： | Line Driver 驱动 接口集成电路 |
| 文件： | 总11页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-8382, HI-8383
ARINC 429
Differential Line Driver
September 2013
GENERAL DESCRIPTION
PIN CONFIGURATION (Top View)
The HI-8382 and HI-8383 bus interface products are silicon
gate CMOS devices designed as a line driver in accordance
with the ARINC 429 bus specifications.
VREF 1
STROBE 2
SYNC 3
DATA(A) 4
CA 5
16 V1
15 N/C
14 CLOCK
13 DATA(B)
12 CB
Inputs are provided for clocking and synchronization. These
signals are AND'd with the DATA inputs to enhance system
performance and allow the HI-8382 to be used in a variety of
applications. Both logic and synchronization inputs feature
built-in 2,000V minimum ESD input protection as well as TTL
and CMOS compatibility.
AOUT 6
-V 7
11 BOUT
10 N/C
GND 8
9 +V
The differential outputs of the HI-8382 are independently
programmable to either the high speed or low speed ARINC
429 output rise and fall time specifications through the use of
two external capacitors. The output voltage swing is also
adjustable by the application of an external voltage to the VREF
input. The HI-8382 has on-chip Zener diodes in series with a
fuse to each differential output protecting the ARINC bus from
an overvoltage failure. The outputs each have a series
resistance of 37.5 ohms. The HI-8383 is identical to the HI-
8382 except that the series resistors are 13 ohms and the
overvoltage protection circuitry has been eliminated.
HI-8382C / CT / CM-01 / CM-03
SMD # 5962-8687901EA
16 - PIN CERAMIC SIDE-BRAZED DIP
(See Page 6 for additional package pin configurations)
FUNCTION
The updated HI-318X and HI-8585 ARINC 429 line drivers are
recommended for all new designs where logic signals must be
converted to ARINC 429 levels such as a user ASIC, the
HI-3282 or HI-8282A ARINC 429 Serial Transmitter/Dual
Receiver, the HI-6010 ARINC 429 Transmitter/Receiver or the
HI-8783 ARINC interface device. Holt products are readily
available for both industrial and extended temperature ranges.
Please contact the Holt Sales Department for additional
information, including data sheets for any of the Holt products
mentioned above.
+
HI-8382
_
ARINC 429 DIFFERENTIAL LINE DRIVER
FEATURES
TRUTH TABLE
! Low power CMOS
! TTL and CMOS compatible inputs
! Programmable output voltage swing
! Adjustable ARINC rise and fall times
! Operates at data rates up to 100 Kbits
! Overvoltage protection
SYNC CLOCK DATA(A) DATA(B) AOUT BOUT COMMENTS
X
L
L
X
H
H
H
H
X
X
L
X
X
L
0V
0V
0V
0V
0V
0V
NULL
NULL
NULL
LOW
HIGH
NULL
H
H
H
H
L
H
L
-VREF +VREF
+VREF -VREF
H
H
! Industrial and extended temperature ranges
! DSCC SMD part number
H
0V
0V
HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS8382 Rev. G)
09/13
HI-8382, HI-8383
switch capacitors must be done with analog switches that
allow voltages below their ground.
FUNCTIONAL DESCRIPTION
The SYNC and CLOCK inputs establish data synchronization
utilizing two AND gates, one for each data input. Each logic
input, including the power enable (STROBE) input, are
TTL/CMOS compatible. Besides reducing chip current drain,
STROBE also floats each output. However the overvoltage
fuses and diodes of the HI-8382 are not switched out.
Both ARINC outputs of the HI-8382 are protected by internal
fuses capable of sinking between 800 - 900 mA for short
periods of time (125µs).
POWER SUPPLY SEQUENCING
The power supplies should be controlled to prevent large
currents during supply turn-on and turn-off. The recom-
mended sequence is +V followed by V1, always ensuring that
+V is the most positive supply. The -V supply is not critical
and can be asserted at any time.
Figure 1 illustrates a typical ARINC 429 bus application.
Three power supplies are necessary to operate the HI-8382;
typically +15V, -15V and +5V. The chip also works with 12V
supplies. The +5V supply can also provide a reference
voltage that determines the output voltage swing. The
differential output voltage swing will equal 2VREF. If a value of
VREF other than +5V is needed, a separate +5V power supply
is required for pin V1.
+5V
+15V
With the DATA(A) input at a logic high and DATA(B) input at a
logic low, AOUT will switch to the +VREF rail and BOUT will
switch to the -VREF rail (ARINC HIGH state). With both data
input signals at a logic low state, the outputs will both switch to
0V (ARINC NULLstate).
V
REF
A
OUT
V
1
SYNC
CLOCK
DATA (A)
INPUTS
DATA (B)
+V
-V
TO ARINC BUS
The driver output impedance, ROUT, is nominally 75 ohms.
The rise and fall times of the outputs can be calibrated through
the selection of two external capacitor values that are
connected to the CA and CB input pins. Typical values for
high-speed operation (100KBPS) are CA = CB = 75pF and for
low-speed operation (12.5 to 14KBPS) CA = CB = 500pF.
The driver can be externally powered down by applying a logic
high to the STROBE input pin. If this feature is not being used,
the pin should be tied to ground.
STROBE
GND
C
B
C
A
B
OUT
-15V
Figure 1. ARINC 429 BUS APPLICATION
The CA and CB pins are inputs to unity gain amplifiers.
Therefore they must be allowed to swing to -5V. Provision to
A
+V
V
REF
C
A
OUT
DATA (A)
CLOCK
SYNC
LEVEL SHIFTER
AND SLOPE
CONTROL (A)
ROUT / 2
FA
OUTPUT
DRIVER (A)
RL
CL
LEVEL SHIFTER
AND SLOPE
CONTROL (B)
FB
ROUT / 2
DATA (B)
OUTPUT
DRIVER (B)
CURRENT
REGULATOR
OVER VOLTAGE
CLAMPS
V1
Not included on HI-8383
STROBE
B
-V
GND
C
B
OUT
Figure 2. FUNCTIONAL BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
2
HI-8382, HI-8383
PIN DESCRIPTIONS
SYMBOL
VREF
FUNCTION
POWER
INPUT
DESCRIPTION
THE REFERENCE VOLTAGE USED TO DETERMINE THE OUTPUT VOLTAGE SWING
STROBE
SYNC
DATA (A)
CA
A LOGIC HIGH ON THIS INPUT PLACES THE DRIVER IN POWER DOWN MODE
INPUT
SYNCHRONIZES DATA INPUTS
DATA INPUT TERMINAL A
CONNECTION FOR DATA (A) SLEW-RATE CAPACITOR
ARINC OUTPUT TERMINAL A
-12V to -15V
INPUT
INPUT
AOUT
OUTPUT
POWER
POWER
POWER
OUTPUT
INPUT
-V
GND
0.0V
+V
+12V to +15V
BOUT
ARINC OUTPUT TERMINAL B
CONNECTION FOR DATA (B) SLEW-RATE CAPACITOR
DATA INPUT TERMINAL B
SYNCHRONIZES DATA INPUTS
+5V 5ꢀ
CB
DATA (B)
CLOCK
V1
INPUT
INPUT
POWER
ABSOLUTE MAXIMUM RATINGS
All Voltages referenced to GND, TA = Operating Temperature Range (unless otherwise specified)
PARAMETER
Differential Voltage
Supply Voltage
SYMBOL
CONDITIONS
OPERATING RANGE
MAXIMUM
UNIT
VDIF
Voltage between +V and -V terminals
40
V
+V
-V
V1
+10.8 to +16.5
-10.8 to -16.5
+5 5ꢀ
V
V
V
+7
Voltage Reference
VREF
For ARINC 429
For Applications other than ARINC
+5 5ꢀ
0 to 6
6
6
V
V
Input Voltage Range
VIN
> GND -0.3
< V1 +0.3
V
V
Output Short-Circuit Duration
Output Overvoltage Protection
Operating Temperature Range
See Note: 1
See Note: 2
TA
Extended
Industrial
-55 to +125
-40 to +85
°C
°C
Storage Temperature Range
TSTG
Ceramic & Plastic
-65 to +150
°C
Lead Temperature
Junction Temperature
Power Dissipation
Soldering, 10 seconds
+275
+175
°C
°C
TJ
PD
16-Pin Ceramic DIP
28-Pin Ceramic LCC
28-Pin Plastic PLCC
32-Pin CERQUAD
See Note: 3
See Note: 3
See Note: 3
See Note: 3
1.725
1.120
2.143
1.725
W
W
W
W
Thermal Resistance,
(Junction-to-Ambient)
ØJA
16-Pin Ceramic DIP
28-Pin Ceramic LCC
28-Pin Plastic PLCC
32-Pin CERQUAD
86.5
133.7
70.0
°C/W
°C/W
°C/W
°C/W
86.5
Note 1. Heatsinking may be required for Output Short Circuit at +125°C and for 100KBPS at +125°C.
Note 2. The fuses used for Output Overvoltage Protection may be blown by the presence of a voltage at either output that is greater
than 12.0V with respect to GND. (HI-8382 only)
Note 3. Derate above +25°C, 11.5mW/°C for 16-PIN DIP and 32-PIN CERQUAD, 7.5 mW/°C for 28-PIN LCC, 14.2 mW/°C for 28-PIN PLCC
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
HOLT INTEGRATED CIRCUITS
3
HI-8382, HI-8383
DC ELECTRICAL CHARACTERISTICS
+V = +15V, -V = -15V, V1 = VREF = +5.0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
Supply Current +V (Operating)
SYMBOL
CONDITION
(0 - 100KBPS)
MIN TYP MAX UNITS
ICCOP (+V)
ICCOP (-V)
ICCOP (V1)
No Load
No Load
No Load
+11
mA
mA
µA
µA
uA
uA
mA
mA
mA
mA
µA
µA
V
Supply Current -V (Operating)
Supply Current V1 (Operating)
Supply Current VREF (Operating)
Supply Current +V (Power Down)
Supply Current -V (Power Down)
Supply Current +V (During Short Circuit Test)
Supply Current -V (During Short Circuit Test)
Output Short Circuit Current (Output High)
Output Short Circuit Current (Output Low)
Input Current (Input High)
(0 - 100KBPS)
(0 - 100KBPS)
(0 - 100KBPS)
-11
500
500
475
ICCOP (VREF) No Load
ICCPD (+V)
ICCPD (-V)
ISC (+V)
ISC (-V)
IOHSC
IOLSC
IIH
STROBE = HIGH
STROBE = HIGH
-475
-150
+80
Short to Ground (See Note: 1)
150
-80
Short to Ground (See Note: 1)
Short to Ground VMIN=0 (See Note: 2)
Short to Ground VMIN=0 (See Note: 2)
1.0
Input Current (Input Low)
IIL
-1.0
Input Voltage High
VIH
2.0
Input Voltage Low
VIL
0.5
V
Output Voltage High (Output to Ground)
VOH
No Load
No Load
(0 -100KBPS)
(0 -100KBPS)
(0-100KBPS)
+VREF
-.25
+VREF
+.25
V
Output Voltage Low (Output to Ground)
VOL
-VREF
-.25
-VREF
+.25
V
Output Voltage Null
Input Capacitance
VNULL
CIN
No Load
-250
+250
mV
pF
See Note 1
15
Note 1. Not tested, but characterized at initial device design and after major process and/or design change which affects this parameter.
Note 2. Interchangeability of force and sense is acceptable.
AC ELECTRICAL CHARACTERISTICS
+V = +15V, -V = -15V, V1 = VREF = +5.0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
t R
CONDITION
MIN TYP MAX UNITS
Rise Time (AOUT, BOUT)
CA = CB = 75pF
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
1.0
1.0
2.0
2.0
3.0
3.0
µs
µs
µs
µs
Fall Time (AOUT, BOUT)
t F
CA = CB = 75pF
CA = CB = 75pF
CA = CB = 75pF
Propagtion Delay Input to Output
Propagtion Delay Input to Output
t PLH
t PHL
2.0V
50ꢀ
0.5V
2.0V
0.5V
DATA (A) 0V
50ꢀ
DATA (B) 0V
ADJUST
BY CA
VREF
+4.75V to +5.25V
AOUT 0V
ADJUST
BY CA
-VREF
+VREF
-4.75V to -5.25V
+4.75V to +5.25V
ADJUST
BY CB
t PHL
50ꢀ
BOUT 0V
ADJUST
BY CB
50ꢀ
-4.75V to -5.25V
+9.5V to +10.5V
-VREF
t PLH
HIGH
2VREF
t R
NULL
LOW
DIFFERENTIAL
OUTPUT 0V
(AOUT - BOUT)
-9.5V to -10.5V
-2VRE
t F
NOTE: OUTPUTS UNLOADED
Figure 3. SWITCHING WAVEFORMS
HOLT INTEGRATED CIRCUITS
4
HI-8382, HI-8383
HI-8382 PACKAGE THERMAL CHARACTERISTICS
7
MAXIMUM ARINC LOAD
SUPPLY CURRENT (mA)2
ARINC 429
DATA RATE
JUNCTION TEMP, Tj (°C)
Ta = 85°C Ta = 125°C
1
PACKAGE STYLE
28 Lead PLCC
Ta = 25°C Ta = 85°C Ta = 125°C Ta = 25°C
3
Low Speed
High Speed
Low Speed
17. 6
25. 4
17. 9
25. 8
17. 2
24. 5
17. 4
24. 8
17. 0
24. 2
17. 1
24. 4
48
56
41
47
107
110
103
112
142
150
145
147
4
16 Lead Ceramic SB DIP
High Speed
5, 6, 7
AOUT and BOUT Shorted To Ground
ARINC 429
DATA RATE
SUPPLY CURRENT (mA)2
JUNCTION TEMP, Tj (°C)
Ta = 85°C Ta = 125°C
1
PACKAGE STYLE
Ta = 25°C Ta = 85°C Ta = 125°C Ta = 25°C
3
Low Speed
High Speed
Low Speed
60. 1
63. 1
62. 1
64. 0
55. 7
56. 3
56. 2
56. 2
52. 4
52. 3
53. 0
52. 2
110
100
90
157
150
145
144
194
182
180
176
28 Lead PLCC
4
16 Lead Ceramic SB DIP
High Speed
86
Notes:
1. All data taken in still air on devices soldered to a single layer copper PCB (3" X 4.5" X .062").
2. At 100ꢀ duty cycle, 15V power supplies. For 12V power supplies multiply all tabulated values by 0.8.
3. Low Speed: Data Rate = 12.5 Kbps, Load: R = 400 Ohms, C = 30 nF.
4. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms, C = 10 nF. Data not presented for C = 30 nF
as this is considered unrealistic for high speed operation.
5. Similar results would be obtained with AOUT shorted to BOUT.
6. For applications requiring survival with continuous short circuit, operation above Tj = 175°C is not recommended.
7. Data will vary depending on air flow and the method of heat sinking employed.
ORDERING INFORMATION
HI - 838x x x - xx (Ceramic)
PART
NUMBER
TEMPERATURE
RANGE
BURN
IN
FLOW
NOTES
I
Blank
T
-40°C to +85°C
-55°C to +125°C
No
No
T
M-01
M-03
-55°C to +125°C
-55°C to +125°C
M
Yes
Yes
(1)
DSCC
(1) & (2)
PART
NUMBER
PACKAGE
DESCRIPTION
LEAD
FINISH
NOTES
C
S
U
16 PIN CERAMIC SIDE BRAZED DIP (16C)
28 PIN CERAMIC LEADLESS CHIP CARRIER (28S)
Gold
Gold
(3) & (1)
(3) & (1)
32 PIN CERQUAD (32U) not available with ‘M’ flow Tin/Lead Solder
PART
NUMBER
OUTPUT SERIES
RESISTANCE
FUSE
Yes
No
8382
8383
37.5 Ohms
13 Ohms
(1) Process Flows M and DSCC always have Tin/Lead (Sn/Pb) solder lead finish.
(2) DSCC SMD# 5962-8687901EA. Only available in “C” package with Sn/Pb solder lead finish.
(3) Gold terminal finish is Pb-Free, RoHS compliant.
HOLT INTEGRATED CIRCUITS
5
HI-8382, HI-8383
HI - 838xJ x x (Plastic)
PART
NUMBER
LEAD
FINISH
Tin / Lead (Sn / Pb) Solder
Blank
F
100ꢀ Matte Tin (Pb-free, RoHS compliant)
PART
NUMBER
TEMPERATURE
RANGE
BURN
IN
FLOW
I
Blank
T
-40°C to +85°C
-55°C to +125°C
No
No
T
PART
NUMBER
PACKAGE
DESCRIPTION
OUTPUT SERIES
RESISTANCE
FUSE
Yes
No
8382J
8383J
28 PIN PLASTIC PLCC (28J) (1)
28 PIN PLASTIC PLCC (28J) (1)
37.5 Ohms
13 Ohms
(1) NOT RECOMMENDED FOR NEW DESIGNS. The newer HI-3182PJxx and HI-3183PJxx are drop-in replacements for the
older HI-8382Jxx and HI-8383Jxx respectively.
HI - 838x PDx x (Plastic DIP)
PART
NUMBER
LEAD
FINISH
Tin / Lead (Sn / Pb) Solder
Blank
F
100ꢀ Matte Tin (Pb-free, RoHS compliant)
PART
NUMBER
TEMPERATURE
RANGE
BURN
IN
FLOW
I
I
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
No
No
T
M
T
M
Yes
PART
NUMBER
PACKAGE
DESCRIPTION
OUTPUT SERIES
RESISTANCE
FUSE
Yes
No
8382
8383
16 PIN PLASTIC DIP
16 PIN PLASTIC DIP
37.5 Ohms
13 Ohms
HOLT INTEGRATED CIRCUITS
6
HI-8382, HI-8383
ADDITIONAL PIN CONFIGURATIONS
(See page 1 for the 16-pin Ceramic Side-Brazed DIP Package )
4
3
2
1 28 27 26
29 28 27 26 25 24 23 22 21
N/C
DATA (A)
N/C
5
6
25 CLOCK
24 N/C
20
19
18
17
16
15
14
30
31
CLOCK
V1
N/C
N/C
+V
23
22
21
20
DATA (B)
CB
N/C 32
7
HI-8382U
HI-8382UT
HI-8382S
HI-8382ST
VREF
STROBE
SYNC
1
2
3
4
GND
N/C
-V
N/C
8
N/C
CA
9
N/C
N/C
10
11
N/C
N/C
19 N/C
N/C
5
6 7 8 9 10 11 12 13
12 13 14 15 16 17 18
32-PIN J-LEAD CERQUAD
28-PIN CERAMIC LCC
VREF 1
STROBE 2
SYNC 3
DATA(A) 4
CA 5
16 V1
15 N/C
4
3
2
1 2 8 2 7 26
5
6
25
24
23
22
21
20
19
N/C
DATA (A)
N/C
CLOCK
N/C
14 CLOCK
13 DATA(B)
12 CB
7
DATA (B)
CB
N/C
HI-8382J
HI-8382JT
8
N/C
CA
9
AOUT 6
-V 7
11 BOUT
10 N/C
10
11
N/C
N/C
N/C
N/C
12 13 14 15 16 17 18
GND 8
9 +V
16-PIN PLASTIC DIP
28-PIN PLASTIC PLCC
HOLT INTEGRATED CIRCUITS
7
HI-8382, HI-8383
REVISION HISTORY
P/N
Rev
Date
Description of Change
DS8382
E
F
02/26/09 Clarified the temperature ranges, and Note (1) in the Ordering Information.
09/16/11 Realigned pin names and numbers with package pin locations in Additional Pin
Configuration drawings.
G
09/10/13 Added Plastic DIP package option.
HOLT INTEGRATED CIRCUITS
8
HI-8382 PACKAGE DIMENSIONS
16-PIN CERAMIC SIDE-BRAZED DIP
inches (millimeters)
Package Type: 16C
.810
(20.574)
max
.295 ±.010
(7.493 ±.254)
.050 ±.005
PIN 1
max
(1.270 ±.127)
.035 .010
.200
(5.080)
(.889 ±.254)
BASE
PLANE
.125
(3.175)
min
.010 ±.002
(.254 ±.051)
SEATING
PLANE
.018 .002
(.457 ±.051)
.100
(2.54)
.300 .010
(7.620 ±.254)
BSC
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
28-PIN PLASTIC PLCC
inches (millimeters)
Package Type: 28J
PIN NO. 1 IDENT
PIN NO. 1
.050
(1.27)
BSC
.045 x 45°
.045 x 45°
.453 ± .003
.490 ± .005
(12.446 ±.127)
SQ.
.031 ±.005
(11.506 ±.076)
(.787 ±.127)
SQ.
.017 ±.004
(.432 ±.102)
See Detail A
.010 .001
(.254 .03)
.173 ±.008
.020
(.508)
(4.394 ±.203)
min
.410 ±.020
DETAILA
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
(10.414 ±.508)
.035
.889
R
HOLT INTEGRATED CIRCUITS
9
HI-8382 PACKAGE DIMENSIONS
28-PIN CERAMIC LEADLESS CHIP CARRIER
inches (millimeters)
Package Type: 28S
.080 ±.020
.020
(.508)
INDEX
(2.032 ±.508)
PIN 1
PIN 1
.050 ±.005
(1.270 ±.127)
.451 ±.009
(11.455 ±.229)
SQ.
.050
(1.270)
BSC
.008R .006
(.203R ±.152)
.025 ±.003
(.635 ±.076)
.040 x 45° 3PLS
(1.016 x 45° 3PLS)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
32-PIN J-LEAD CERQUAD
inches (millimeters)
Package Type: 32U
31
32
1
.450 ±.008
(11.430 ±.203)
.420 ±.012
.488 ±.008
(10.668 ±.305)
2
(12.395 ±.203)
.588 ±.008
(14.935 ±.203)
.550 ± .009
(13.970 ± .229)
.190
(4.826)
max
.040
(1.016)
typ
.083 ±.009
(2.108 ±.229)
.050
(1.270)
.019 ± .003
BSC
(.483 ± .076)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.520 ±.012
(13.208 ±.305)
HOLT INTEGRATED CIRCUITS
10
HI-8382 PACKAGE DIMENSIONS
16-PIN PLASTIC DUAL IN-LINE PACKAGE (PDIP)
(300mil Body)
inches (millimeters)
Package Type: 16PDIP
.255
(6.48)
.300
BSC
(7.62)
BSC
.100
(2.54)
BSC
0.755
(19.18)
BSC
.150 .020
(3.81 .508)
.130 .010
(3.302 .254)
.011 .002
(.279 .051)
.028 .013
(.711 .330)
.345 .035
(8.763 .889)
.058 .013
(1.473 .330)
.018 .002
(.457 .051)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
11
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